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Fix configurations with more than 4GB of memory
[qemu-kvm/fedora.git] / hw / ppc.c
blob8e7912e3cc93c59daf56b70663d6e56b1e3f67a0
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "m48t59.h"
26
27 //#define PPC_DEBUG_IRQ
28 //#define PPC_DEBUG_TB
29
30 extern FILE *logfile;
31 extern int loglevel;
32
33 void ppc_set_irq (CPUState *env, int n_IRQ, int level)
34 {
35 if (level) {
36 env->pending_interrupts |= 1 << n_IRQ;
37 cpu_interrupt(env, CPU_INTERRUPT_HARD);
38 } else {
39 env->pending_interrupts &= ~(1 << n_IRQ);
40 if (env->pending_interrupts == 0)
41 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
42 }
43 #if defined(PPC_DEBUG_IRQ)
44 if (loglevel & CPU_LOG_INT) {
45 fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
46 __func__, env, n_IRQ, level,
47 env->pending_interrupts, env->interrupt_request);
48 }
49 #endif
50 }
51
52 /* PowerPC 6xx / 7xx internal IRQ controller */
53 static void ppc6xx_set_irq (void *opaque, int pin, int level)
54 {
55 CPUState *env = opaque;
56 int cur_level;
57
58 #if defined(PPC_DEBUG_IRQ)
59 if (loglevel & CPU_LOG_INT) {
60 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
61 env, pin, level);
62 }
63 #endif
64 cur_level = (env->irq_input_state >> pin) & 1;
65 /* Don't generate spurious events */
66 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
67 switch (pin) {
68 case PPC6xx_INPUT_INT:
69 /* Level sensitive - active high */
70 #if defined(PPC_DEBUG_IRQ)
71 if (loglevel & CPU_LOG_INT) {
72 fprintf(logfile, "%s: set the external IRQ state to %d\n",
73 __func__, level);
74 }
75 #endif
76 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
77 break;
78 case PPC6xx_INPUT_SMI:
79 /* Level sensitive - active high */
80 #if defined(PPC_DEBUG_IRQ)
81 if (loglevel & CPU_LOG_INT) {
82 fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
83 __func__, level);
84 }
85 #endif
86 ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
87 break;
88 case PPC6xx_INPUT_MCP:
89 /* Negative edge sensitive */
90 /* XXX: TODO: actual reaction may depends on HID0 status
91 * 603/604/740/750: check HID0[EMCP]
92 */
93 if (cur_level == 1 && level == 0) {
94 #if defined(PPC_DEBUG_IRQ)
95 if (loglevel & CPU_LOG_INT) {
96 fprintf(logfile, "%s: raise machine check state\n",
97 __func__);
98 }
99 #endif
100 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
101 }
102 break;
103 case PPC6xx_INPUT_CKSTP_IN:
104 /* Level sensitive - active low */
105 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
106 if (level) {
107 #if defined(PPC_DEBUG_IRQ)
108 if (loglevel & CPU_LOG_INT) {
109 fprintf(logfile, "%s: stop the CPU\n", __func__);
110 }
111 #endif
112 env->halted = 1;
113 } else {
114 #if defined(PPC_DEBUG_IRQ)
115 if (loglevel & CPU_LOG_INT) {
116 fprintf(logfile, "%s: restart the CPU\n", __func__);
117 }
118 #endif
119 env->halted = 0;
120 }
121 break;
122 case PPC6xx_INPUT_HRESET:
123 /* Level sensitive - active low */
124 if (level) {
125 #if 0 // XXX: TOFIX
126 #if defined(PPC_DEBUG_IRQ)
127 if (loglevel & CPU_LOG_INT) {
128 fprintf(logfile, "%s: reset the CPU\n", __func__);
129 }
130 #endif
131 cpu_reset(env);
132 #endif
133 }
134 break;
135 case PPC6xx_INPUT_SRESET:
136 #if defined(PPC_DEBUG_IRQ)
137 if (loglevel & CPU_LOG_INT) {
138 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
139 __func__, level);
140 }
141 #endif
142 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
143 break;
144 default:
145 /* Unknown pin - do nothing */
146 #if defined(PPC_DEBUG_IRQ)
147 if (loglevel & CPU_LOG_INT) {
148 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
149 }
150 #endif
151 return;
152 }
153 if (level)
154 env->irq_input_state |= 1 << pin;
155 else
156 env->irq_input_state &= ~(1 << pin);
157 }
158 }
159
160 void ppc6xx_irq_init (CPUState *env)
161 {
162 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
163 }
164
165 /* PowerPC 970 internal IRQ controller */
166 static void ppc970_set_irq (void *opaque, int pin, int level)
167 {
168 CPUState *env = opaque;
169 int cur_level;
170
171 #if defined(PPC_DEBUG_IRQ)
172 if (loglevel & CPU_LOG_INT) {
173 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
174 env, pin, level);
175 }
176 #endif
177 cur_level = (env->irq_input_state >> pin) & 1;
178 /* Don't generate spurious events */
179 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
180 switch (pin) {
181 case PPC970_INPUT_INT:
182 /* Level sensitive - active high */
183 #if defined(PPC_DEBUG_IRQ)
184 if (loglevel & CPU_LOG_INT) {
185 fprintf(logfile, "%s: set the external IRQ state to %d\n",
186 __func__, level);
187 }
188 #endif
189 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
190 break;
191 case PPC970_INPUT_THINT:
192 /* Level sensitive - active high */
193 #if defined(PPC_DEBUG_IRQ)
194 if (loglevel & CPU_LOG_INT) {
195 fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
196 level);
197 }
198 #endif
199 ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
200 break;
201 case PPC970_INPUT_MCP:
202 /* Negative edge sensitive */
203 /* XXX: TODO: actual reaction may depends on HID0 status
204 * 603/604/740/750: check HID0[EMCP]
205 */
206 if (cur_level == 1 && level == 0) {
207 #if defined(PPC_DEBUG_IRQ)
208 if (loglevel & CPU_LOG_INT) {
209 fprintf(logfile, "%s: raise machine check state\n",
210 __func__);
211 }
212 #endif
213 ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
214 }
215 break;
216 case PPC970_INPUT_CKSTP:
217 /* Level sensitive - active low */
218 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
219 if (level) {
220 #if defined(PPC_DEBUG_IRQ)
221 if (loglevel & CPU_LOG_INT) {
222 fprintf(logfile, "%s: stop the CPU\n", __func__);
223 }
224 #endif
225 env->halted = 1;
226 } else {
227 #if defined(PPC_DEBUG_IRQ)
228 if (loglevel & CPU_LOG_INT) {
229 fprintf(logfile, "%s: restart the CPU\n", __func__);
230 }
231 #endif
232 env->halted = 0;
233 }
234 break;
235 case PPC970_INPUT_HRESET:
236 /* Level sensitive - active low */
237 if (level) {
238 #if 0 // XXX: TOFIX
239 #if defined(PPC_DEBUG_IRQ)
240 if (loglevel & CPU_LOG_INT) {
241 fprintf(logfile, "%s: reset the CPU\n", __func__);
242 }
243 #endif
244 cpu_reset(env);
245 #endif
246 }
247 break;
248 case PPC970_INPUT_SRESET:
249 #if defined(PPC_DEBUG_IRQ)
250 if (loglevel & CPU_LOG_INT) {
251 fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
252 __func__, level);
253 }
254 #endif
255 ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
256 break;
257 case PPC970_INPUT_TBEN:
258 #if defined(PPC_DEBUG_IRQ)
259 if (loglevel & CPU_LOG_INT) {
260 fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
261 level);
262 }
263 #endif
264 /* XXX: TODO */
265 break;
266 default:
267 /* Unknown pin - do nothing */
268 #if defined(PPC_DEBUG_IRQ)
269 if (loglevel & CPU_LOG_INT) {
270 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
271 }
272 #endif
273 return;
274 }
275 if (level)
276 env->irq_input_state |= 1 << pin;
277 else
278 env->irq_input_state &= ~(1 << pin);
279 }
280 }
281
282 void ppc970_irq_init (CPUState *env)
283 {
284 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
285 }
286
287 /* PowerPC 40x internal IRQ controller */
288 static void ppc40x_set_irq (void *opaque, int pin, int level)
289 {
290 CPUState *env = opaque;
291 int cur_level;
292
293 #if defined(PPC_DEBUG_IRQ)
294 if (loglevel & CPU_LOG_INT) {
295 fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
296 env, pin, level);
297 }
298 #endif
299 cur_level = (env->irq_input_state >> pin) & 1;
300 /* Don't generate spurious events */
301 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
302 switch (pin) {
303 case PPC40x_INPUT_RESET_SYS:
304 if (level) {
305 #if defined(PPC_DEBUG_IRQ)
306 if (loglevel & CPU_LOG_INT) {
307 fprintf(logfile, "%s: reset the PowerPC system\n",
308 __func__);
309 }
310 #endif
311 ppc40x_system_reset(env);
312 }
313 break;
314 case PPC40x_INPUT_RESET_CHIP:
315 if (level) {
316 #if defined(PPC_DEBUG_IRQ)
317 if (loglevel & CPU_LOG_INT) {
318 fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
319 }
320 #endif
321 ppc40x_chip_reset(env);
322 }
323 break;
324 case PPC40x_INPUT_RESET_CORE:
325 /* XXX: TODO: update DBSR[MRR] */
326 if (level) {
327 #if defined(PPC_DEBUG_IRQ)
328 if (loglevel & CPU_LOG_INT) {
329 fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
330 }
331 #endif
332 ppc40x_core_reset(env);
333 }
334 break;
335 case PPC40x_INPUT_CINT:
336 /* Level sensitive - active high */
337 #if defined(PPC_DEBUG_IRQ)
338 if (loglevel & CPU_LOG_INT) {
339 fprintf(logfile, "%s: set the critical IRQ state to %d\n",
340 __func__, level);
341 }
342 #endif
343 ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
344 break;
345 case PPC40x_INPUT_INT:
346 /* Level sensitive - active high */
347 #if defined(PPC_DEBUG_IRQ)
348 if (loglevel & CPU_LOG_INT) {
349 fprintf(logfile, "%s: set the external IRQ state to %d\n",
350 __func__, level);
351 }
352 #endif
353 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
354 break;
355 case PPC40x_INPUT_HALT:
356 /* Level sensitive - active low */
357 if (level) {
358 #if defined(PPC_DEBUG_IRQ)
359 if (loglevel & CPU_LOG_INT) {
360 fprintf(logfile, "%s: stop the CPU\n", __func__);
361 }
362 #endif
363 env->halted = 1;
364 } else {
365 #if defined(PPC_DEBUG_IRQ)
366 if (loglevel & CPU_LOG_INT) {
367 fprintf(logfile, "%s: restart the CPU\n", __func__);
368 }
369 #endif
370 env->halted = 0;
371 }
372 break;
373 case PPC40x_INPUT_DEBUG:
374 /* Level sensitive - active high */
375 #if defined(PPC_DEBUG_IRQ)
376 if (loglevel & CPU_LOG_INT) {
377 fprintf(logfile, "%s: set the debug pin state to %d\n",
378 __func__, level);
379 }
380 #endif
381 ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
382 break;
383 default:
384 /* Unknown pin - do nothing */
385 #if defined(PPC_DEBUG_IRQ)
386 if (loglevel & CPU_LOG_INT) {
387 fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
388 }
389 #endif
390 return;
391 }
392 if (level)
393 env->irq_input_state |= 1 << pin;
394 else
395 env->irq_input_state &= ~(1 << pin);
396 }
397 }
398
399 void ppc40x_irq_init (CPUState *env)
400 {
401 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
402 env, PPC40x_INPUT_NB);
403 }
404
405 /*****************************************************************************/
406 /* PowerPC time base and decrementer emulation */
407 struct ppc_tb_t {
408 /* Time base management */
409 int64_t tb_offset; /* Compensation */
410 int64_t atb_offset; /* Compensation */
411 uint32_t tb_freq; /* TB frequency */
412 /* Decrementer management */
413 uint64_t decr_next; /* Tick for next decr interrupt */
414 struct QEMUTimer *decr_timer;
415 #if defined(TARGET_PPC64H)
416 /* Hypervisor decrementer management */
417 uint64_t hdecr_next; /* Tick for next hdecr interrupt */
418 struct QEMUTimer *hdecr_timer;
419 uint64_t purr_load;
420 uint64_t purr_start;
421 #endif
422 void *opaque;
423 };
424
425 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, int64_t tb_offset)
426 {
427 /* TB time in tb periods */
428 return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
429 tb_env->tb_freq, ticks_per_sec);
430 }
431
432 uint32_t cpu_ppc_load_tbl (CPUState *env)
433 {
434 ppc_tb_t *tb_env = env->tb_env;
435 uint64_t tb;
436
437 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
438 #if defined(PPC_DEBUG_TB)
439 if (loglevel != 0) {
440 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
441 }
442 #endif
443
444 return tb & 0xFFFFFFFF;
445 }
446
447 static inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
448 {
449 ppc_tb_t *tb_env = env->tb_env;
450 uint64_t tb;
451
452 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
453 #if defined(PPC_DEBUG_TB)
454 if (loglevel != 0) {
455 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
456 }
457 #endif
458
459 return tb >> 32;
460 }
461
462 uint32_t cpu_ppc_load_tbu (CPUState *env)
463 {
464 return _cpu_ppc_load_tbu(env);
465 }
466
467 static inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, int64_t *tb_offsetp,
468 uint64_t value)
469 {
470 *tb_offsetp = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
471 - qemu_get_clock(vm_clock);
472 #ifdef PPC_DEBUG_TB
473 if (loglevel != 0) {
474 fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
475 *tb_offsetp);
476 }
477 #endif
478 }
479
480 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
481 {
482 ppc_tb_t *tb_env = env->tb_env;
483 uint64_t tb;
484
485 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
486 tb &= 0xFFFFFFFF00000000ULL;
487 cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, tb | (uint64_t)value);
488 }
489
490 static inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
491 {
492 ppc_tb_t *tb_env = env->tb_env;
493 uint64_t tb;
494
495 tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
496 tb &= 0x00000000FFFFFFFFULL;
497 cpu_ppc_store_tb(tb_env, &tb_env->tb_offset,
498 ((uint64_t)value << 32) | tb);
499 }
500
501 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
502 {
503 _cpu_ppc_store_tbu(env, value);
504 }
505
506 uint32_t cpu_ppc_load_atbl (CPUState *env)
507 {
508 ppc_tb_t *tb_env = env->tb_env;
509 uint64_t tb;
510
511 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
512 #if defined(PPC_DEBUG_TB)
513 if (loglevel != 0) {
514 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
515 }
516 #endif
517
518 return tb & 0xFFFFFFFF;
519 }
520
521 uint32_t cpu_ppc_load_atbu (CPUState *env)
522 {
523 ppc_tb_t *tb_env = env->tb_env;
524 uint64_t tb;
525
526 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
527 #if defined(PPC_DEBUG_TB)
528 if (loglevel != 0) {
529 fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
530 }
531 #endif
532
533 return tb >> 32;
534 }
535
536 void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
537 {
538 ppc_tb_t *tb_env = env->tb_env;
539 uint64_t tb;
540
541 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
542 tb &= 0xFFFFFFFF00000000ULL;
543 cpu_ppc_store_tb(tb_env, &tb_env->atb_offset, tb | (uint64_t)value);
544 }
545
546 void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
547 {
548 ppc_tb_t *tb_env = env->tb_env;
549 uint64_t tb;
550
551 tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
552 tb &= 0x00000000FFFFFFFFULL;
553 cpu_ppc_store_tb(tb_env, &tb_env->atb_offset,
554 ((uint64_t)value << 32) | tb);
555 }
556
557 static inline uint32_t _cpu_ppc_load_decr (CPUState *env, uint64_t *next)
558 {
559 ppc_tb_t *tb_env = env->tb_env;
560 uint32_t decr;
561 int64_t diff;
562
563 diff = tb_env->decr_next - qemu_get_clock(vm_clock);
564 if (diff >= 0)
565 decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
566 else
567 decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
568 #if defined(PPC_DEBUG_TB)
569 if (loglevel != 0) {
570 fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
571 }
572 #endif
573
574 return decr;
575 }
576
577 uint32_t cpu_ppc_load_decr (CPUState *env)
578 {
579 ppc_tb_t *tb_env = env->tb_env;
580
581 return _cpu_ppc_load_decr(env, &tb_env->decr_next);
582 }
583
584 #if defined(TARGET_PPC64H)
585 uint32_t cpu_ppc_load_hdecr (CPUState *env)
586 {
587 ppc_tb_t *tb_env = env->tb_env;
588
589 return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
590 }
591
592 uint64_t cpu_ppc_load_purr (CPUState *env)
593 {
594 ppc_tb_t *tb_env = env->tb_env;
595 uint64_t diff;
596
597 diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
598
599 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
600 }
601 #endif /* defined(TARGET_PPC64H) */
602
603 /* When decrementer expires,
604 * all we need to do is generate or queue a CPU exception
605 */
606 static inline void cpu_ppc_decr_excp (CPUState *env)
607 {
608 /* Raise it */
609 #ifdef PPC_DEBUG_TB
610 if (loglevel != 0) {
611 fprintf(logfile, "raise decrementer exception\n");
612 }
613 #endif
614 ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
615 }
616
617 static inline void cpu_ppc_hdecr_excp (CPUState *env)
618 {
619 /* Raise it */
620 #ifdef PPC_DEBUG_TB
621 if (loglevel != 0) {
622 fprintf(logfile, "raise decrementer exception\n");
623 }
624 #endif
625 ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
626 }
627
628 static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
629 struct QEMUTimer *timer,
630 void (*raise_excp)(CPUState *),
631 uint32_t decr, uint32_t value,
632 int is_excp)
633 {
634 ppc_tb_t *tb_env = env->tb_env;
635 uint64_t now, next;
636
637 #ifdef PPC_DEBUG_TB
638 if (loglevel != 0) {
639 fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
640 }
641 #endif
642 now = qemu_get_clock(vm_clock);
643 next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
644 if (is_excp)
645 next += *nextp - now;
646 if (next == now)
647 next++;
648 *nextp = next;
649 /* Adjust timer */
650 qemu_mod_timer(timer, next);
651 /* If we set a negative value and the decrementer was positive,
652 * raise an exception.
653 */
654 if ((value & 0x80000000) && !(decr & 0x80000000))
655 (*raise_excp)(env);
656 }
657
658
659 static inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
660 uint32_t value, int is_excp)
661 {
662 ppc_tb_t *tb_env = env->tb_env;
663
664 __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
665 &cpu_ppc_decr_excp, decr, value, is_excp);
666 }
667
668 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
669 {
670 _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
671 }
672
673 static void cpu_ppc_decr_cb (void *opaque)
674 {
675 _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
676 }
677
678 #if defined(TARGET_PPC64H)
679 static inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
680 uint32_t value, int is_excp)
681 {
682 ppc_tb_t *tb_env = env->tb_env;
683
684 __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
685 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
686 }
687
688 void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
689 {
690 _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
691 }
692
693 static void cpu_ppc_hdecr_cb (void *opaque)
694 {
695 _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
696 }
697
698 void cpu_ppc_store_purr (CPUState *env, uint64_t value)
699 {
700 ppc_tb_t *tb_env = env->tb_env;
701
702 tb_env->purr_load = value;
703 tb_env->purr_start = qemu_get_clock(vm_clock);
704 }
705 #endif /* defined(TARGET_PPC64H) */
706
707 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
708 {
709 CPUState *env = opaque;
710 ppc_tb_t *tb_env = env->tb_env;
711
712 tb_env->tb_freq = freq;
713 /* There is a bug in Linux 2.4 kernels:
714 * if a decrementer exception is pending when it enables msr_ee at startup,
715 * it's not ready to handle it...
716 */
717 _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
718 #if defined(TARGET_PPC64H)
719 _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
720 cpu_ppc_store_purr(env, 0x0000000000000000ULL);
721 #endif /* defined(TARGET_PPC64H) */
722 }
723
724 /* Set up (once) timebase frequency (in Hz) */
725 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
726 {
727 ppc_tb_t *tb_env;
728
729 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
730 if (tb_env == NULL)
731 return NULL;
732 env->tb_env = tb_env;
733 /* Create new timer */
734 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
735 #if defined(TARGET_PPC64H)
736 tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
737 #endif /* defined(TARGET_PPC64H) */
738 cpu_ppc_set_tb_clk(env, freq);
739
740 return &cpu_ppc_set_tb_clk;
741 }
742
743 /* Specific helpers for POWER & PowerPC 601 RTC */
744 clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
745 {
746 return cpu_ppc_tb_init(env, 7812500);
747 }
748
749 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
750 {
751 _cpu_ppc_store_tbu(env, value);
752 }
753
754 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
755 {
756 return _cpu_ppc_load_tbu(env);
757 }
758
759 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
760 {
761 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
762 }
763
764 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
765 {
766 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
767 }
768
769 /*****************************************************************************/
770 /* Embedded PowerPC timers */
771
772 /* PIT, FIT & WDT */
773 typedef struct ppcemb_timer_t ppcemb_timer_t;
774 struct ppcemb_timer_t {
775 uint64_t pit_reload; /* PIT auto-reload value */
776 uint64_t fit_next; /* Tick for next FIT interrupt */
777 struct QEMUTimer *fit_timer;
778 uint64_t wdt_next; /* Tick for next WDT interrupt */
779 struct QEMUTimer *wdt_timer;
780 };
781
782 /* Fixed interval timer */
783 static void cpu_4xx_fit_cb (void *opaque)
784 {
785 CPUState *env;
786 ppc_tb_t *tb_env;
787 ppcemb_timer_t *ppcemb_timer;
788 uint64_t now, next;
789
790 env = opaque;
791 tb_env = env->tb_env;
792 ppcemb_timer = tb_env->opaque;
793 now = qemu_get_clock(vm_clock);
794 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
795 case 0:
796 next = 1 << 9;
797 break;
798 case 1:
799 next = 1 << 13;
800 break;
801 case 2:
802 next = 1 << 17;
803 break;
804 case 3:
805 next = 1 << 21;
806 break;
807 default:
808 /* Cannot occur, but makes gcc happy */
809 return;
810 }
811 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
812 if (next == now)
813 next++;
814 qemu_mod_timer(ppcemb_timer->fit_timer, next);
815 env->spr[SPR_40x_TSR] |= 1 << 26;
816 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
817 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
818 #ifdef PPC_DEBUG_TB
819 if (loglevel != 0) {
820 fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
821 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
822 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
823 }
824 #endif
825 }
826
827 /* Programmable interval timer */
828 static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
829 {
830 ppcemb_timer_t *ppcemb_timer;
831 uint64_t now, next;
832
833 ppcemb_timer = tb_env->opaque;
834 if (ppcemb_timer->pit_reload <= 1 ||
835 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
836 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
837 /* Stop PIT */
838 #ifdef PPC_DEBUG_TB
839 if (loglevel != 0) {
840 fprintf(logfile, "%s: stop PIT\n", __func__);
841 }
842 #endif
843 qemu_del_timer(tb_env->decr_timer);
844 } else {
845 #ifdef PPC_DEBUG_TB
846 if (loglevel != 0) {
847 fprintf(logfile, "%s: start PIT 0x" REGX "\n",
848 __func__, ppcemb_timer->pit_reload);
849 }
850 #endif
851 now = qemu_get_clock(vm_clock);
852 next = now + muldiv64(ppcemb_timer->pit_reload,
853 ticks_per_sec, tb_env->tb_freq);
854 if (is_excp)
855 next += tb_env->decr_next - now;
856 if (next == now)
857 next++;
858 qemu_mod_timer(tb_env->decr_timer, next);
859 tb_env->decr_next = next;
860 }
861 }
862
863 static void cpu_4xx_pit_cb (void *opaque)
864 {
865 CPUState *env;
866 ppc_tb_t *tb_env;
867 ppcemb_timer_t *ppcemb_timer;
868
869 env = opaque;
870 tb_env = env->tb_env;
871 ppcemb_timer = tb_env->opaque;
872 env->spr[SPR_40x_TSR] |= 1 << 27;
873 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
874 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
875 start_stop_pit(env, tb_env, 1);
876 #ifdef PPC_DEBUG_TB
877 if (loglevel != 0) {
878 fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
879 "%016" PRIx64 "\n", __func__,
880 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
881 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
882 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
883 ppcemb_timer->pit_reload);
884 }
885 #endif
886 }
887
888 /* Watchdog timer */
889 static void cpu_4xx_wdt_cb (void *opaque)
890 {
891 CPUState *env;
892 ppc_tb_t *tb_env;
893 ppcemb_timer_t *ppcemb_timer;
894 uint64_t now, next;
895
896 env = opaque;
897 tb_env = env->tb_env;
898 ppcemb_timer = tb_env->opaque;
899 now = qemu_get_clock(vm_clock);
900 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
901 case 0:
902 next = 1 << 17;
903 break;
904 case 1:
905 next = 1 << 21;
906 break;
907 case 2:
908 next = 1 << 25;
909 break;
910 case 3:
911 next = 1 << 29;
912 break;
913 default:
914 /* Cannot occur, but makes gcc happy */
915 return;
916 }
917 next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
918 if (next == now)
919 next++;
920 #ifdef PPC_DEBUG_TB
921 if (loglevel != 0) {
922 fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
923 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
924 }
925 #endif
926 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
927 case 0x0:
928 case 0x1:
929 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
930 ppcemb_timer->wdt_next = next;
931 env->spr[SPR_40x_TSR] |= 1 << 31;
932 break;
933 case 0x2:
934 qemu_mod_timer(ppcemb_timer->wdt_timer, next);
935 ppcemb_timer->wdt_next = next;
936 env->spr[SPR_40x_TSR] |= 1 << 30;
937 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
938 ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
939 break;
940 case 0x3:
941 env->spr[SPR_40x_TSR] &= ~0x30000000;
942 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
943 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
944 case 0x0:
945 /* No reset */
946 break;
947 case 0x1: /* Core reset */
948 ppc40x_core_reset(env);
949 break;
950 case 0x2: /* Chip reset */
951 ppc40x_chip_reset(env);
952 break;
953 case 0x3: /* System reset */
954 ppc40x_system_reset(env);
955 break;
956 }
957 }
958 }
959
960 void store_40x_pit (CPUState *env, target_ulong val)
961 {
962 ppc_tb_t *tb_env;
963 ppcemb_timer_t *ppcemb_timer;
964
965 tb_env = env->tb_env;
966 ppcemb_timer = tb_env->opaque;
967 #ifdef PPC_DEBUG_TB
968 if (loglevel != 0) {
969 fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
970 }
971 #endif
972 ppcemb_timer->pit_reload = val;
973 start_stop_pit(env, tb_env, 0);
974 }
975
976 target_ulong load_40x_pit (CPUState *env)
977 {
978 return cpu_ppc_load_decr(env);
979 }
980
981 void store_booke_tsr (CPUState *env, target_ulong val)
982 {
983 #ifdef PPC_DEBUG_TB
984 if (loglevel != 0) {
985 fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
986 }
987 #endif
988 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
989 if (val & 0x80000000)
990 ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
991 }
992
993 void store_booke_tcr (CPUState *env, target_ulong val)
994 {
995 ppc_tb_t *tb_env;
996
997 tb_env = env->tb_env;
998 #ifdef PPC_DEBUG_TB
999 if (loglevel != 0) {
1000 fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
1001 }
1002 #endif
1003 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
1004 start_stop_pit(env, tb_env, 1);
1005 cpu_4xx_wdt_cb(env);
1006 }
1007
1008 static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
1009 {
1010 CPUState *env = opaque;
1011 ppc_tb_t *tb_env = env->tb_env;
1012
1013 #ifdef PPC_DEBUG_TB
1014 if (loglevel != 0) {
1015 fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
1016 }
1017 #endif
1018 tb_env->tb_freq = freq;
1019 /* XXX: we should also update all timers */
1020 }
1021
1022 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
1023 {
1024 ppc_tb_t *tb_env;
1025 ppcemb_timer_t *ppcemb_timer;
1026
1027 tb_env = qemu_mallocz(sizeof(ppc_tb_t));
1028 if (tb_env == NULL) {
1029 return NULL;
1030 }
1031 env->tb_env = tb_env;
1032 ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
1033 tb_env->tb_freq = freq;
1034 tb_env->opaque = ppcemb_timer;
1035 #ifdef PPC_DEBUG_TB
1036 if (loglevel != 0) {
1037 fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
1038 &ppc_emb_set_tb_clk);
1039 }
1040 #endif
1041 if (ppcemb_timer != NULL) {
1042 /* We use decr timer for PIT */
1043 tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
1044 ppcemb_timer->fit_timer =
1045 qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
1046 ppcemb_timer->wdt_timer =
1047 qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
1048 }
1049
1050 return &ppc_emb_set_tb_clk;
1051 }
1052
1053 /*****************************************************************************/
1054 /* Embedded PowerPC Device Control Registers */
1055 typedef struct ppc_dcrn_t ppc_dcrn_t;
1056 struct ppc_dcrn_t {
1057 dcr_read_cb dcr_read;
1058 dcr_write_cb dcr_write;
1059 void *opaque;
1060 };
1061
1062 /* XXX: on 460, DCR addresses are 32 bits wide,
1063 * using DCRIPR to get the 22 upper bits of the DCR address
1064 */
1065 #define DCRN_NB 1024
1066 struct ppc_dcr_t {
1067 ppc_dcrn_t dcrn[DCRN_NB];
1068 int (*read_error)(int dcrn);
1069 int (*write_error)(int dcrn);
1070 };
1071
1072 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1073 {
1074 ppc_dcrn_t *dcr;
1075
1076 if (dcrn < 0 || dcrn >= DCRN_NB)
1077 goto error;
1078 dcr = &dcr_env->dcrn[dcrn];
1079 if (dcr->dcr_read == NULL)
1080 goto error;
1081 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1082
1083 return 0;
1084
1085 error:
1086 if (dcr_env->read_error != NULL)
1087 return (*dcr_env->read_error)(dcrn);
1088
1089 return -1;
1090 }
1091
1092 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1093 {
1094 ppc_dcrn_t *dcr;
1095
1096 if (dcrn < 0 || dcrn >= DCRN_NB)
1097 goto error;
1098 dcr = &dcr_env->dcrn[dcrn];
1099 if (dcr->dcr_write == NULL)
1100 goto error;
1101 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1102
1103 return 0;
1104
1105 error:
1106 if (dcr_env->write_error != NULL)
1107 return (*dcr_env->write_error)(dcrn);
1108
1109 return -1;
1110 }
1111
1112 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1113 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1114 {
1115 ppc_dcr_t *dcr_env;
1116 ppc_dcrn_t *dcr;
1117
1118 dcr_env = env->dcr_env;
1119 if (dcr_env == NULL)
1120 return -1;
1121 if (dcrn < 0 || dcrn >= DCRN_NB)
1122 return -1;
1123 dcr = &dcr_env->dcrn[dcrn];
1124 if (dcr->opaque != NULL ||
1125 dcr->dcr_read != NULL ||
1126 dcr->dcr_write != NULL)
1127 return -1;
1128 dcr->opaque = opaque;
1129 dcr->dcr_read = dcr_read;
1130 dcr->dcr_write = dcr_write;
1131
1132 return 0;
1133 }
1134
1135 int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
1136 int (*write_error)(int dcrn))
1137 {
1138 ppc_dcr_t *dcr_env;
1139
1140 dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
1141 if (dcr_env == NULL)
1142 return -1;
1143 dcr_env->read_error = read_error;
1144 dcr_env->write_error = write_error;
1145 env->dcr_env = dcr_env;
1146
1147 return 0;
1148 }
1149
1150
1151 #if 0
1152 /*****************************************************************************/
1153 /* Handle system reset (for now, just stop emulation) */
1154 void cpu_ppc_reset (CPUState *env)
1155 {
1156 printf("Reset asked... Stop emulation\n");
1157 abort();
1158 }
1159 #endif
1160
1161 /*****************************************************************************/
1162 /* Debug port */
1163 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1164 {
1165 addr &= 0xF;
1166 switch (addr) {
1167 case 0:
1168 printf("%c", val);
1169 break;
1170 case 1:
1171 printf("\n");
1172 fflush(stdout);
1173 break;
1174 case 2:
1175 printf("Set loglevel to %04x\n", val);
1176 cpu_set_log(val | 0x100);
1177 break;
1178 }
1179 }
1180
1181 /*****************************************************************************/
1182 /* NVRAM helpers */
1183 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
1184 {
1185 m48t59_write(nvram, addr, value);
1186 }
1187
1188 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
1189 {
1190 return m48t59_read(nvram, addr);
1191 }
1192
1193 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
1194 {
1195 m48t59_write(nvram, addr, value >> 8);
1196 m48t59_write(nvram, addr + 1, value & 0xFF);
1197 }
1198
1199 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
1200 {
1201 uint16_t tmp;
1202
1203 tmp = m48t59_read(nvram, addr) << 8;
1204 tmp |= m48t59_read(nvram, addr + 1);
1205 return tmp;
1206 }
1207
1208 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
1209 {
1210 m48t59_write(nvram, addr, value >> 24);
1211 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
1212 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
1213 m48t59_write(nvram, addr + 3, value & 0xFF);
1214 }
1215
1216 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
1217 {
1218 uint32_t tmp;
1219
1220 tmp = m48t59_read(nvram, addr) << 24;
1221 tmp |= m48t59_read(nvram, addr + 1) << 16;
1222 tmp |= m48t59_read(nvram, addr + 2) << 8;
1223 tmp |= m48t59_read(nvram, addr + 3);
1224
1225 return tmp;
1226 }
1227
1228 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1229 const unsigned char *str, uint32_t max)
1230 {
1231 int i;
1232
1233 for (i = 0; i < max && str[i] != '\0'; i++) {
1234 m48t59_write(nvram, addr + i, str[i]);
1235 }
1236 m48t59_write(nvram, addr + max - 1, '\0');
1237 }
1238
1239 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
1240 {
1241 int i;
1242
1243 memset(dst, 0, max);
1244 for (i = 0; i < max; i++) {
1245 dst[i] = NVRAM_get_byte(nvram, addr + i);
1246 if (dst[i] == '\0')
1247 break;
1248 }
1249
1250 return i;
1251 }
1252
1253 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1254 {
1255 uint16_t tmp;
1256 uint16_t pd, pd1, pd2;
1257
1258 tmp = prev >> 8;
1259 pd = prev ^ value;
1260 pd1 = pd & 0x000F;
1261 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1262 tmp ^= (pd1 << 3) | (pd1 << 8);
1263 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1264
1265 return tmp;
1266 }
1267
1268 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
1269 {
1270 uint32_t i;
1271 uint16_t crc = 0xFFFF;
1272 int odd;
1273
1274 odd = count & 1;
1275 count &= ~1;
1276 for (i = 0; i != count; i++) {
1277 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1278 }
1279 if (odd) {
1280 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1281 }
1282
1283 return crc;
1284 }
1285
1286 #define CMDLINE_ADDR 0x017ff000
1287
1288 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1289 const unsigned char *arch,
1290 uint32_t RAM_size, int boot_device,
1291 uint32_t kernel_image, uint32_t kernel_size,
1292 const char *cmdline,
1293 uint32_t initrd_image, uint32_t initrd_size,
1294 uint32_t NVRAM_image,
1295 int width, int height, int depth)
1296 {
1297 uint16_t crc;
1298
1299 /* Set parameters for Open Hack'Ware BIOS */
1300 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1301 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1302 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1303 NVRAM_set_string(nvram, 0x20, arch, 16);
1304 NVRAM_set_lword(nvram, 0x30, RAM_size);
1305 NVRAM_set_byte(nvram, 0x34, boot_device);
1306 NVRAM_set_lword(nvram, 0x38, kernel_image);
1307 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1308 if (cmdline) {
1309 /* XXX: put the cmdline in NVRAM too ? */
1310 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
1311 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1312 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1313 } else {
1314 NVRAM_set_lword(nvram, 0x40, 0);
1315 NVRAM_set_lword(nvram, 0x44, 0);
1316 }
1317 NVRAM_set_lword(nvram, 0x48, initrd_image);
1318 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1319 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1320
1321 NVRAM_set_word(nvram, 0x54, width);
1322 NVRAM_set_word(nvram, 0x56, height);
1323 NVRAM_set_word(nvram, 0x58, depth);
1324 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1325 NVRAM_set_word(nvram, 0xFC, crc);
1326
1327 return 0;
1328 }
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