hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 #ifdef USE_KVM
  27 #include "qemu-kvm.h"
  28 #endif
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 //#define DEBUG_IRQ_LATENCY
  34 //#define DEBUG_IRQ_COUNT
  35
  36 typedef struct PicState {
  37     uint8_t last_irr; /* edge detection */
  38     uint8_t irr; /* interrupt request register */
  39     uint8_t imr; /* interrupt mask register */
  40     uint8_t isr; /* interrupt service register */
  41     uint8_t priority_add; /* highest irq priority */
  42     uint8_t irq_base;
  43     uint8_t read_reg_select;
  44     uint8_t poll;
  45     uint8_t special_mask;
  46     uint8_t init_state;
  47     uint8_t auto_eoi;
  48     uint8_t rotate_on_auto_eoi;
  49     uint8_t special_fully_nested_mode;
  50     uint8_t init4; /* true if 4 byte init */
  51     uint8_t single_mode; /* true if slave pic is not initialized */
  52     uint8_t elcr; /* PIIX edge/trigger selection*/
  53     uint8_t elcr_mask;
  54     PicState2 *pics_state;
  55 } PicState;
  56
  57 struct PicState2 {
  58     /* 0 is master pic, 1 is slave pic */
  59     /* XXX: better separation between the two pics */
  60     PicState pics[2];
  61     qemu_irq parent_irq;
  62     void *irq_request_opaque;
  63     /* IOAPIC callback support */
  64     SetIRQFunc *alt_irq_func;
  65     void *alt_irq_opaque;
  66 };
  67
  68 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  69 static int irq_level[16];
  70 #endif
  71 #ifdef DEBUG_IRQ_COUNT
  72 static uint64_t irq_count[16];
  73 #endif
  74
  75 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  76 static inline void pic_set_irq1(PicState *s, int irq, int level)
  77 {
  78     int mask;
  79     mask = 1 << irq;
  80     if (s->elcr & mask) {
  81         /* level triggered */
  82         if (level) {
  83             s->irr |= mask;
  84             s->last_irr |= mask;
  85         } else {
  86             s->irr &= ~mask;
  87             s->last_irr &= ~mask;
  88         }
  89     } else {
  90         /* edge triggered */
  91         if (level) {
  92             if ((s->last_irr & mask) == 0)
  93                 s->irr |= mask;
  94             s->last_irr |= mask;
  95         } else {
  96             s->last_irr &= ~mask;
  97         }
  98     }
  99 }
 100
 101 /* return the highest priority found in mask (highest = smallest
 102    number). Return 8 if no irq */
 103 static inline int get_priority(PicState *s, int mask)
 104 {
 105     int priority;
 106     if (mask == 0)
 107         return 8;
 108     priority = 0;
 109     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 110         priority++;
 111     return priority;
 112 }
 113
 114 /* return the pic wanted interrupt. return -1 if none */
 115 static int pic_get_irq(PicState *s)
 116 {
 117     int mask, cur_priority, priority;
 118
 119     mask = s->irr & ~s->imr;
 120     priority = get_priority(s, mask);
 121     if (priority == 8)
 122         return -1;
 123     /* compute current priority. If special fully nested mode on the
 124        master, the IRQ coming from the slave is not taken into account
 125        for the priority computation. */
 126     mask = s->isr;
 127     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 128         mask &= ~(1 << 2);
 129     cur_priority = get_priority(s, mask);
 130     if (priority < cur_priority) {
 131         /* higher priority found: an irq should be generated */
 132         return (priority + s->priority_add) & 7;
 133     } else {
 134         return -1;
 135     }
 136 }
 137
 138 /* raise irq to CPU if necessary. must be called every time the active
 139    irq may change */
 140 /* XXX: should not export it, but it is needed for an APIC kludge */
 141 void pic_update_irq(PicState2 *s)
 142 {
 143     int irq2, irq;
 144
 145     /* first look at slave pic */
 146     irq2 = pic_get_irq(&s->pics[1]);
 147     if (irq2 >= 0) {
 148         /* if irq request by slave pic, signal master PIC */
 149         pic_set_irq1(&s->pics[0], 2, 1);
 150         pic_set_irq1(&s->pics[0], 2, 0);
 151     }
 152     /* look at requested irq */
 153     irq = pic_get_irq(&s->pics[0]);
 154     if (irq >= 0) {
 155 #if defined(DEBUG_PIC)
 156         {
 157             int i;
 158             for(i = 0; i < 2; i++) {
 159                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 160                        i, s->pics[i].imr, s->pics[i].irr,
 161                        s->pics[i].priority_add);
 162
 163             }
 164         }
 165         printf("pic: cpu_interrupt\n");
 166 #endif
 167         qemu_irq_raise(s->parent_irq);
 168     }
 169
 170 /* all targets should do this rather than acking the IRQ in the cpu */
 171 #if defined(TARGET_MIPS)
 172     else {
 173         qemu_irq_lower(s->parent_irq);
 174     }
 175 #endif
 176 }
 177
 178 #ifdef DEBUG_IRQ_LATENCY
 179 int64_t irq_time[16];
 180 #endif
 181
 182 void i8259_set_irq(void *opaque, int irq, int level)
 183 {
 184     PicState2 *s = opaque;
 185 #ifdef USE_KVM
 186 #ifdef KVM_CAP_IRQCHIP
 187     extern int kvm_set_irq(int irq, int level);
 188
 189     if (kvm_allowed)
 190         if (kvm_set_irq(irq, level))
 191             return;
 192 #endif
 193 #endif
 194 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 195     if (level != irq_level[irq]) {
 196 #if defined(DEBUG_PIC)
 197         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 198 #endif
 199         irq_level[irq] = level;
 200 #ifdef DEBUG_IRQ_COUNT
 201         if (level == 1)
 202             irq_count[irq]++;
 203 #endif
 204     }
 205 #endif
 206 #ifdef DEBUG_IRQ_LATENCY
 207     if (level) {
 208         irq_time[irq] = qemu_get_clock(vm_clock);
 209     }
 210 #endif
 211     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 212     /* used for IOAPIC irqs */
 213     if (s->alt_irq_func)
 214         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 215     pic_update_irq(s);
 216 }
 217
 218 /* acknowledge interrupt 'irq' */
 219 static inline void pic_intack(PicState *s, int irq)
 220 {
 221     if (s->auto_eoi) {
 222         if (s->rotate_on_auto_eoi)
 223             s->priority_add = (irq + 1) & 7;
 224     } else {
 225         s->isr |= (1 << irq);
 226     }
 227
 228     /* We don't clear a level sensitive interrupt here */
 229     if (!(s->elcr & (1 << irq)))
 230         s->irr &= ~(1 << irq);
 231
 232 }
 233
 234 int pic_read_irq(PicState2 *s)
 235 {
 236     int irq, irq2, intno;
 237
 238     irq = pic_get_irq(&s->pics[0]);
 239     if (irq >= 0) {
 240
 241         if (time_drift_fix && irq == 0) {
 242             extern int64_t timer_acks, timer_ints_to_push;
 243             timer_acks++;
 244             if (timer_ints_to_push > 0) {
 245                 timer_ints_to_push--;
 246                 qemu_irq_lower(s->parent_irq);
 247                 qemu_irq_raise(s->parent_irq);
 248             }
 249         }
 250
 251         pic_intack(&s->pics[0], irq);
 252         if (irq == 2) {
 253             irq2 = pic_get_irq(&s->pics[1]);
 254             if (irq2 >= 0) {
 255                 pic_intack(&s->pics[1], irq2);
 256             } else {
 257                 /* spurious IRQ on slave controller */
 258                 irq2 = 7;
 259             }
 260             intno = s->pics[1].irq_base + irq2;
 261             irq = irq2 + 8;
 262         } else {
 263             intno = s->pics[0].irq_base + irq;
 264         }
 265     } else {
 266         /* spurious IRQ on host controller */
 267         irq = 7;
 268         intno = s->pics[0].irq_base + irq;
 269     }
 270     pic_update_irq(s);
 271
 272 #ifdef DEBUG_IRQ_LATENCY
 273     printf("IRQ%d latency=%0.3fus\n",
 274            irq,
 275            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 276 #endif
 277 #if defined(DEBUG_PIC)
 278     printf("pic_interrupt: irq=%d\n", irq);
 279 #endif
 280     return intno;
 281 }
 282
 283 static void pic_reset(void *opaque)
 284 {
 285     PicState *s = opaque;
 286
 287     s->last_irr = 0;
 288     s->irr = 0;
 289     s->imr = 0;
 290     s->isr = 0;
 291     s->priority_add = 0;
 292     s->irq_base = 0;
 293     s->read_reg_select = 0;
 294     s->poll = 0;
 295     s->special_mask = 0;
 296     s->init_state = 0;
 297     s->auto_eoi = 0;
 298     s->rotate_on_auto_eoi = 0;
 299     s->special_fully_nested_mode = 0;
 300     s->init4 = 0;
 301     s->single_mode = 0;
 302     /* Note: ELCR is not reset */
 303 }
 304
 305 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 306 {
 307     PicState *s = opaque;
 308     int priority, cmd, irq;
 309
 310 #ifdef DEBUG_PIC
 311     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 312 #endif
 313     addr &= 1;
 314     if (addr == 0) {
 315         if (val & 0x10) {
 316             /* init */
 317             pic_reset(s);
 318             /* deassert a pending interrupt */
 319             qemu_irq_lower(s->pics_state->parent_irq);
 320             s->init_state = 1;
 321             s->init4 = val & 1;
 322             s->single_mode = val & 2;
 323             if (val & 0x08)
 324                 hw_error("level sensitive irq not supported");
 325         } else if (val & 0x08) {
 326             if (val & 0x04)
 327                 s->poll = 1;
 328             if (val & 0x02)
 329                 s->read_reg_select = val & 1;
 330             if (val & 0x40)
 331                 s->special_mask = (val >> 5) & 1;
 332         } else {
 333             cmd = val >> 5;
 334             switch(cmd) {
 335             case 0:
 336             case 4:
 337                 s->rotate_on_auto_eoi = cmd >> 2;
 338                 break;
 339             case 1: /* end of interrupt */
 340             case 5:
 341                 priority = get_priority(s, s->isr);
 342                 if (priority != 8) {
 343                     irq = (priority + s->priority_add) & 7;
 344                     s->isr &= ~(1 << irq);
 345                     if (cmd == 5)
 346                         s->priority_add = (irq + 1) & 7;
 347                     pic_update_irq(s->pics_state);
 348                 }
 349                 break;
 350             case 3:
 351                 irq = val & 7;
 352                 s->isr &= ~(1 << irq);
 353                 pic_update_irq(s->pics_state);
 354                 break;
 355             case 6:
 356                 s->priority_add = (val + 1) & 7;
 357                 pic_update_irq(s->pics_state);
 358                 break;
 359             case 7:
 360                 irq = val & 7;
 361                 s->isr &= ~(1 << irq);
 362                 s->priority_add = (irq + 1) & 7;
 363                 pic_update_irq(s->pics_state);
 364                 break;
 365             default:
 366                 /* no operation */
 367                 break;
 368             }
 369         }
 370     } else {
 371         switch(s->init_state) {
 372         case 0:
 373             /* normal mode */
 374             s->imr = val;
 375             pic_update_irq(s->pics_state);
 376             break;
 377         case 1:
 378             s->irq_base = val & 0xf8;
 379             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 380             break;
 381         case 2:
 382             if (s->init4) {
 383                 s->init_state = 3;
 384             } else {
 385                 s->init_state = 0;
 386             }
 387             break;
 388         case 3:
 389             s->special_fully_nested_mode = (val >> 4) & 1;
 390             s->auto_eoi = (val >> 1) & 1;
 391             s->init_state = 0;
 392             break;
 393         }
 394     }
 395 }
 396
 397 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 398 {
 399     int ret;
 400
 401     ret = pic_get_irq(s);
 402     if (ret >= 0) {
 403         if (addr1 >> 7) {
 404             s->pics_state->pics[0].isr &= ~(1 << 2);
 405             s->pics_state->pics[0].irr &= ~(1 << 2);
 406         }
 407         s->irr &= ~(1 << ret);
 408         s->isr &= ~(1 << ret);
 409         if (addr1 >> 7 || ret != 2)
 410             pic_update_irq(s->pics_state);
 411     } else {
 412         ret = 0x07;
 413         pic_update_irq(s->pics_state);
 414     }
 415
 416     return ret;
 417 }
 418
 419 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 420 {
 421     PicState *s = opaque;
 422     unsigned int addr;
 423     int ret;
 424
 425     addr = addr1;
 426     addr &= 1;
 427     if (s->poll) {
 428         ret = pic_poll_read(s, addr1);
 429         s->poll = 0;
 430     } else {
 431         if (addr == 0) {
 432             if (s->read_reg_select)
 433                 ret = s->isr;
 434             else
 435                 ret = s->irr;
 436         } else {
 437             ret = s->imr;
 438         }
 439     }
 440 #ifdef DEBUG_PIC
 441     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 442 #endif
 443     return ret;
 444 }
 445
 446 /* memory mapped interrupt status */
 447 /* XXX: may be the same than pic_read_irq() */
 448 uint32_t pic_intack_read(PicState2 *s)
 449 {
 450     int ret;
 451
 452     ret = pic_poll_read(&s->pics[0], 0x00);
 453     if (ret == 2)
 454         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 455     /* Prepare for ISR read */
 456     s->pics[0].read_reg_select = 1;
 457
 458     return ret;
 459 }
 460
 461 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 462 {
 463     PicState *s = opaque;
 464     s->elcr = val & s->elcr_mask;
 465 }
 466
 467 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 468 {
 469     PicState *s = opaque;
 470     return s->elcr;
 471 }
 472
 473 #ifdef USE_KVM
 474 #include "qemu-kvm.h"
 475 extern int kvm_allowed;
 476 extern kvm_context_t kvm_context;
 477
 478 static void kvm_kernel_pic_save_to_user(PicState *s)
 479 {
 480 #ifdef KVM_CAP_IRQCHIP
 481     struct kvm_irqchip chip;
 482     struct kvm_pic_state *kpic;
 483
 484     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 485                    KVM_IRQCHIP_PIC_MASTER :
 486                    KVM_IRQCHIP_PIC_SLAVE;
 487     kvm_get_irqchip(kvm_context, &chip);
 488     kpic = &chip.chip.pic;
 489
 490     s->last_irr = kpic->last_irr;
 491     s->irr = kpic->irr;
 492     s->imr = kpic->imr;
 493     s->isr = kpic->isr;
 494     s->priority_add = kpic->priority_add;
 495     s->irq_base = kpic->irq_base;
 496     s->read_reg_select = kpic->read_reg_select;
 497     s->poll = kpic->poll;
 498     s->special_mask = kpic->special_mask;
 499     s->init_state = kpic->init_state;
 500     s->auto_eoi = kpic->auto_eoi;
 501     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 502     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 503     s->init4 = kpic->init4;
 504     s->elcr = kpic->elcr;
 505     s->elcr_mask = kpic->elcr_mask;
 506 #endif
 507 }
 508
 509 static void kvm_kernel_pic_load_from_user(PicState *s)
 510 {
 511 #ifdef KVM_CAP_IRQCHIP
 512     struct kvm_irqchip chip;
 513     struct kvm_pic_state *kpic;
 514
 515     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 516                    KVM_IRQCHIP_PIC_MASTER :
 517                    KVM_IRQCHIP_PIC_SLAVE;
 518     kpic = &chip.chip.pic;
 519
 520     kpic->last_irr = s->last_irr;
 521     kpic->irr = s->irr;
 522     kpic->imr = s->imr;
 523     kpic->isr = s->isr;
 524     kpic->priority_add = s->priority_add;
 525     kpic->irq_base = s->irq_base;
 526     kpic->read_reg_select = s->read_reg_select;
 527     kpic->poll = s->poll;
 528     kpic->special_mask = s->special_mask;
 529     kpic->init_state = s->init_state;
 530     kpic->auto_eoi = s->auto_eoi;
 531     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 532     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 533     kpic->init4 = s->init4;
 534     kpic->elcr = s->elcr;
 535     kpic->elcr_mask = s->elcr_mask;
 536
 537     kvm_set_irqchip(kvm_context, &chip);
 538 #endif
 539 }
 540 #endif
 541
 542 static void pic_save(QEMUFile *f, void *opaque)
 543 {
 544     PicState *s = opaque;
 545
 546 #ifdef USE_KVM
 547     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 548         kvm_kernel_pic_save_to_user(s);
 549     }
 550 #endif
 551
 552     qemu_put_8s(f, &s->last_irr);
 553     qemu_put_8s(f, &s->irr);
 554     qemu_put_8s(f, &s->imr);
 555     qemu_put_8s(f, &s->isr);
 556     qemu_put_8s(f, &s->priority_add);
 557     qemu_put_8s(f, &s->irq_base);
 558     qemu_put_8s(f, &s->read_reg_select);
 559     qemu_put_8s(f, &s->poll);
 560     qemu_put_8s(f, &s->special_mask);
 561     qemu_put_8s(f, &s->init_state);
 562     qemu_put_8s(f, &s->auto_eoi);
 563     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 564     qemu_put_8s(f, &s->special_fully_nested_mode);
 565     qemu_put_8s(f, &s->init4);
 566     qemu_put_8s(f, &s->single_mode);
 567     qemu_put_8s(f, &s->elcr);
 568 }
 569
 570 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 571 {
 572     PicState *s = opaque;
 573
 574     if (version_id != 1)
 575         return -EINVAL;
 576
 577     qemu_get_8s(f, &s->last_irr);
 578     qemu_get_8s(f, &s->irr);
 579     qemu_get_8s(f, &s->imr);
 580     qemu_get_8s(f, &s->isr);
 581     qemu_get_8s(f, &s->priority_add);
 582     qemu_get_8s(f, &s->irq_base);
 583     qemu_get_8s(f, &s->read_reg_select);
 584     qemu_get_8s(f, &s->poll);
 585     qemu_get_8s(f, &s->special_mask);
 586     qemu_get_8s(f, &s->init_state);
 587     qemu_get_8s(f, &s->auto_eoi);
 588     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 589     qemu_get_8s(f, &s->special_fully_nested_mode);
 590     qemu_get_8s(f, &s->init4);
 591     qemu_get_8s(f, &s->single_mode);
 592     qemu_get_8s(f, &s->elcr);
 593
 594 #ifdef USE_KVM
 595     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 596         kvm_kernel_pic_load_from_user(s);
 597     }
 598 #endif
 599
 600     return 0;
 601 }
 602
 603 /* XXX: add generic master/slave system */
 604 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 605 {
 606     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 607     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 608     if (elcr_addr >= 0) {
 609         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 610         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 611     }
 612     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 613     qemu_register_reset(pic_reset, s);
 614 }
 615
 616 void pic_info(void)
 617 {
 618     int i;
 619     PicState *s;
 620
 621     if (!isa_pic)
 622         return;
 623
 624     for(i=0;i<2;i++) {
 625         s = &isa_pic->pics[i];
 626         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 627                     i, s->irr, s->imr, s->isr, s->priority_add,
 628                     s->irq_base, s->read_reg_select, s->elcr,
 629                     s->special_fully_nested_mode);
 630     }
 631 }
 632
 633 void irq_info(void)
 634 {
 635 #ifndef DEBUG_IRQ_COUNT
 636     term_printf("irq statistic code not compiled.\n");
 637 #else
 638     int i;
 639     int64_t count;
 640
 641     term_printf("IRQ statistics:\n");
 642     for (i = 0; i < 16; i++) {
 643         count = irq_count[i];
 644         if (count > 0)
 645             term_printf("%2d: %" PRId64 "\n", i, count);
 646     }
 647 #endif
 648 }
 649
 650 qemu_irq *i8259_init(qemu_irq parent_irq)
 651 {
 652     PicState2 *s;
 653
 654     s = qemu_mallocz(sizeof(PicState2));
 655     if (!s)
 656         return NULL;
 657     pic_init1(0x20, 0x4d0, &s->pics[0]);
 658     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 659     s->pics[0].elcr_mask = 0xf8;
 660     s->pics[1].elcr_mask = 0xde;
 661     s->parent_irq = parent_irq;
 662     s->pics[0].pics_state = s;
 663     s->pics[1].pics_state = s;
 664     isa_pic = s;
 665     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 666 }
 667
 668 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 669                           void *alt_irq_opaque)
 670 {
 671     s->alt_irq_func = alt_irq_func;
 672     s->alt_irq_opaque = alt_irq_opaque;
 673 }