2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
37 * - destination write mask support not complete (bits 5..7)
38 * - optimize linear mappings
39 * - optimize bitblt functions
42 //#define DEBUG_CIRRUS
43 //#define DEBUG_BITBLT
45 /***************************************
49 ***************************************/
51 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
54 #define CIRRUS_ID_CLGD5422 (0x23<<2)
55 #define CIRRUS_ID_CLGD5426 (0x24<<2)
56 #define CIRRUS_ID_CLGD5424 (0x25<<2)
57 #define CIRRUS_ID_CLGD5428 (0x26<<2)
58 #define CIRRUS_ID_CLGD5430 (0x28<<2)
59 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
60 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
61 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64 #define CIRRUS_SR7_BPP_VGA 0x00
65 #define CIRRUS_SR7_BPP_SVGA 0x01
66 #define CIRRUS_SR7_BPP_MASK 0x0e
67 #define CIRRUS_SR7_BPP_8 0x00
68 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69 #define CIRRUS_SR7_BPP_24 0x04
70 #define CIRRUS_SR7_BPP_16 0x06
71 #define CIRRUS_SR7_BPP_32 0x08
72 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75 #define CIRRUS_MEMSIZE_512k 0x08
76 #define CIRRUS_MEMSIZE_1M 0x10
77 #define CIRRUS_MEMSIZE_2M 0x18
78 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81 #define CIRRUS_CURSOR_SHOW 0x01
82 #define CIRRUS_CURSOR_HIDDENPEL 0x02
83 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86 #define CIRRUS_BUSTYPE_VLBFAST 0x10
87 #define CIRRUS_BUSTYPE_PCI 0x20
88 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
89 #define CIRRUS_BUSTYPE_ISA 0x38
90 #define CIRRUS_MMIO_ENABLE 0x04
91 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95 #define CIRRUS_BANKING_DUAL 0x01
96 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99 #define CIRRUS_BLTMODE_BACKWARDS 0x01
100 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
105 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112 #define CIRRUS_BLT_BUSY 0x01
113 #define CIRRUS_BLT_START 0x02
114 #define CIRRUS_BLT_RESET 0x04
115 #define CIRRUS_BLT_FIFOUSED 0x10
116 #define CIRRUS_BLT_AUTOSTART 0x80
119 #define CIRRUS_ROP_0 0x00
120 #define CIRRUS_ROP_SRC_AND_DST 0x05
121 #define CIRRUS_ROP_NOP 0x06
122 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123 #define CIRRUS_ROP_NOTDST 0x0b
124 #define CIRRUS_ROP_SRC 0x0d
125 #define CIRRUS_ROP_1 0x0e
126 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127 #define CIRRUS_ROP_SRC_XOR_DST 0x59
128 #define CIRRUS_ROP_SRC_OR_DST 0x6d
129 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132 #define CIRRUS_ROP_NOTSRC 0xd0
133 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136 #define CIRRUS_ROP_NOP_INDEX 2
137 #define CIRRUS_ROP_SRC_INDEX 5
140 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
141 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
142 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
155 #define CIRRUS_MMIO_BLTROP 0x1a // byte
156 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175 // PCI 0x00: vendor, 0x02: device
176 #define PCI_VENDOR_CIRRUS 0x1013
177 #define PCI_DEVICE_CLGD5462 0x00d0
178 #define PCI_DEVICE_CLGD5465 0x00d6
180 // PCI 0x04: command(word), 0x06(word): status
181 #define PCI_COMMAND_IOACCESS 0x0001
182 #define PCI_COMMAND_MEMACCESS 0x0002
183 #define PCI_COMMAND_BUSMASTER 0x0004
184 #define PCI_COMMAND_SPECIALCYCLE 0x0008
185 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
186 #define PCI_COMMAND_PALETTESNOOPING 0x0020
187 #define PCI_COMMAND_PARITYDETECTION 0x0040
188 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
189 #define PCI_COMMAND_SERR 0x0100
190 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
191 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
192 #define PCI_CLASS_BASE_DISPLAY 0x03
193 // PCI 0x08, 0x00ff0000
194 #define PCI_CLASS_SUB_VGA 0x00
195 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
196 #define PCI_CLASS_HEADERTYPE_00h 0x00
197 // 0x10-0x3f (headertype 00h)
198 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
199 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
200 #define PCI_MAP_MEM 0x0
201 #define PCI_MAP_IO 0x1
202 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
203 #define PCI_MAP_IO_ADDR_MASK (~0x3)
204 #define PCI_MAP_MEMFLAGS_32BIT 0x0
205 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
206 #define PCI_MAP_MEMFLAGS_64BIT 0x4
207 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
208 // PCI 0x28: cardbus CIS pointer
209 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
210 // PCI 0x30: expansion ROM base address
211 #define PCI_ROMBIOS_ENABLED 0x1
212 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
213 // PCI 0x38: reserved
214 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
216 #define CIRRUS_PNPMMIO_SIZE 0x1000
219 /* I/O and memory hook */
220 #define CIRRUS_HOOK_NOT_HANDLED 0
221 #define CIRRUS_HOOK_HANDLED 1
223 struct CirrusVGAState
;
224 typedef void (*cirrus_bitblt_rop_t
) (struct CirrusVGAState
*s
,
225 uint8_t * dst
, const uint8_t * src
,
226 int dstpitch
, int srcpitch
,
227 int bltwidth
, int bltheight
);
228 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
229 uint8_t *dst
, int dst_pitch
, int width
, int height
);
231 typedef struct CirrusVGAState
{
234 int cirrus_linear_io_addr
;
235 int cirrus_linear_bitblt_io_addr
;
236 int cirrus_mmio_io_addr
;
238 unsigned long cirrus_lfb_addr
;
239 unsigned long cirrus_lfb_end
;
241 uint32_t cirrus_addr_mask
;
242 uint32_t linear_mmio_mask
;
243 uint8_t cirrus_shadow_gr0
;
244 uint8_t cirrus_shadow_gr1
;
245 uint8_t cirrus_hidden_dac_lockindex
;
246 uint8_t cirrus_hidden_dac_data
;
247 uint32_t cirrus_bank_base
[2];
248 uint32_t cirrus_bank_limit
[2];
249 uint8_t cirrus_hidden_palette
[48];
250 uint32_t hw_cursor_x
;
251 uint32_t hw_cursor_y
;
252 int cirrus_blt_pixelwidth
;
253 int cirrus_blt_width
;
254 int cirrus_blt_height
;
255 int cirrus_blt_dstpitch
;
256 int cirrus_blt_srcpitch
;
257 uint32_t cirrus_blt_fgcol
;
258 uint32_t cirrus_blt_bgcol
;
259 uint32_t cirrus_blt_dstaddr
;
260 uint32_t cirrus_blt_srcaddr
;
261 uint8_t cirrus_blt_mode
;
262 uint8_t cirrus_blt_modeext
;
263 cirrus_bitblt_rop_t cirrus_rop
;
264 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
265 uint8_t cirrus_bltbuf
[CIRRUS_BLTBUFSIZE
];
266 uint8_t *cirrus_srcptr
;
267 uint8_t *cirrus_srcptr_end
;
268 uint32_t cirrus_srccounter
;
269 /* hwcursor display state */
270 int last_hw_cursor_size
;
271 int last_hw_cursor_x
;
272 int last_hw_cursor_y
;
273 int last_hw_cursor_y_start
;
274 int last_hw_cursor_y_end
;
275 int real_vram_size
; /* XXX: suppress that */
276 CPUWriteMemoryFunc
**cirrus_linear_write
;
278 unsigned long map_addr
;
279 unsigned long map_end
;
283 typedef struct PCICirrusVGAState
{
285 CirrusVGAState cirrus_vga
;
288 static uint8_t rop_to_index
[256];
290 /***************************************
294 ***************************************/
297 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
298 static void cirrus_update_memory_access(CirrusVGAState
*s
);
300 /***************************************
304 ***************************************/
306 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
307 uint8_t *dst
,const uint8_t *src
,
308 int dstpitch
,int srcpitch
,
309 int bltwidth
,int bltheight
)
313 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
315 int dstpitch
, int bltwidth
,int bltheight
)
320 #define ROP_OP(d, s) d = 0
321 #include "cirrus_vga_rop.h"
323 #define ROP_NAME src_and_dst
324 #define ROP_OP(d, s) d = (s) & (d)
325 #include "cirrus_vga_rop.h"
327 #define ROP_NAME src_and_notdst
328 #define ROP_OP(d, s) d = (s) & (~(d))
329 #include "cirrus_vga_rop.h"
331 #define ROP_NAME notdst
332 #define ROP_OP(d, s) d = ~(d)
333 #include "cirrus_vga_rop.h"
336 #define ROP_OP(d, s) d = s
337 #include "cirrus_vga_rop.h"
340 #define ROP_OP(d, s) d = ~0
341 #include "cirrus_vga_rop.h"
343 #define ROP_NAME notsrc_and_dst
344 #define ROP_OP(d, s) d = (~(s)) & (d)
345 #include "cirrus_vga_rop.h"
347 #define ROP_NAME src_xor_dst
348 #define ROP_OP(d, s) d = (s) ^ (d)
349 #include "cirrus_vga_rop.h"
351 #define ROP_NAME src_or_dst
352 #define ROP_OP(d, s) d = (s) | (d)
353 #include "cirrus_vga_rop.h"
355 #define ROP_NAME notsrc_or_notdst
356 #define ROP_OP(d, s) d = (~(s)) | (~(d))
357 #include "cirrus_vga_rop.h"
359 #define ROP_NAME src_notxor_dst
360 #define ROP_OP(d, s) d = ~((s) ^ (d))
361 #include "cirrus_vga_rop.h"
363 #define ROP_NAME src_or_notdst
364 #define ROP_OP(d, s) d = (s) | (~(d))
365 #include "cirrus_vga_rop.h"
367 #define ROP_NAME notsrc
368 #define ROP_OP(d, s) d = (~(s))
369 #include "cirrus_vga_rop.h"
371 #define ROP_NAME notsrc_or_dst
372 #define ROP_OP(d, s) d = (~(s)) | (d)
373 #include "cirrus_vga_rop.h"
375 #define ROP_NAME notsrc_and_notdst
376 #define ROP_OP(d, s) d = (~(s)) & (~(d))
377 #include "cirrus_vga_rop.h"
379 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
380 cirrus_bitblt_rop_fwd_0
,
381 cirrus_bitblt_rop_fwd_src_and_dst
,
382 cirrus_bitblt_rop_nop
,
383 cirrus_bitblt_rop_fwd_src_and_notdst
,
384 cirrus_bitblt_rop_fwd_notdst
,
385 cirrus_bitblt_rop_fwd_src
,
386 cirrus_bitblt_rop_fwd_1
,
387 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
388 cirrus_bitblt_rop_fwd_src_xor_dst
,
389 cirrus_bitblt_rop_fwd_src_or_dst
,
390 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
391 cirrus_bitblt_rop_fwd_src_notxor_dst
,
392 cirrus_bitblt_rop_fwd_src_or_notdst
,
393 cirrus_bitblt_rop_fwd_notsrc
,
394 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
395 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
398 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
399 cirrus_bitblt_rop_bkwd_0
,
400 cirrus_bitblt_rop_bkwd_src_and_dst
,
401 cirrus_bitblt_rop_nop
,
402 cirrus_bitblt_rop_bkwd_src_and_notdst
,
403 cirrus_bitblt_rop_bkwd_notdst
,
404 cirrus_bitblt_rop_bkwd_src
,
405 cirrus_bitblt_rop_bkwd_1
,
406 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
407 cirrus_bitblt_rop_bkwd_src_xor_dst
,
408 cirrus_bitblt_rop_bkwd_src_or_dst
,
409 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
410 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
411 cirrus_bitblt_rop_bkwd_src_or_notdst
,
412 cirrus_bitblt_rop_bkwd_notsrc
,
413 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
414 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
417 #define ROP2(name) {\
424 #define ROP_NOP2(func) {\
431 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
432 ROP2(cirrus_patternfill_0
),
433 ROP2(cirrus_patternfill_src_and_dst
),
434 ROP_NOP2(cirrus_bitblt_rop_nop
),
435 ROP2(cirrus_patternfill_src_and_notdst
),
436 ROP2(cirrus_patternfill_notdst
),
437 ROP2(cirrus_patternfill_src
),
438 ROP2(cirrus_patternfill_1
),
439 ROP2(cirrus_patternfill_notsrc_and_dst
),
440 ROP2(cirrus_patternfill_src_xor_dst
),
441 ROP2(cirrus_patternfill_src_or_dst
),
442 ROP2(cirrus_patternfill_notsrc_or_notdst
),
443 ROP2(cirrus_patternfill_src_notxor_dst
),
444 ROP2(cirrus_patternfill_src_or_notdst
),
445 ROP2(cirrus_patternfill_notsrc
),
446 ROP2(cirrus_patternfill_notsrc_or_dst
),
447 ROP2(cirrus_patternfill_notsrc_and_notdst
),
450 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
451 ROP2(cirrus_colorexpand_transp_0
),
452 ROP2(cirrus_colorexpand_transp_src_and_dst
),
453 ROP_NOP2(cirrus_bitblt_rop_nop
),
454 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
455 ROP2(cirrus_colorexpand_transp_notdst
),
456 ROP2(cirrus_colorexpand_transp_src
),
457 ROP2(cirrus_colorexpand_transp_1
),
458 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
459 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
460 ROP2(cirrus_colorexpand_transp_src_or_dst
),
461 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
462 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
463 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
464 ROP2(cirrus_colorexpand_transp_notsrc
),
465 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
466 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
469 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
470 ROP2(cirrus_colorexpand_0
),
471 ROP2(cirrus_colorexpand_src_and_dst
),
472 ROP_NOP2(cirrus_bitblt_rop_nop
),
473 ROP2(cirrus_colorexpand_src_and_notdst
),
474 ROP2(cirrus_colorexpand_notdst
),
475 ROP2(cirrus_colorexpand_src
),
476 ROP2(cirrus_colorexpand_1
),
477 ROP2(cirrus_colorexpand_notsrc_and_dst
),
478 ROP2(cirrus_colorexpand_src_xor_dst
),
479 ROP2(cirrus_colorexpand_src_or_dst
),
480 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
481 ROP2(cirrus_colorexpand_src_notxor_dst
),
482 ROP2(cirrus_colorexpand_src_or_notdst
),
483 ROP2(cirrus_colorexpand_notsrc
),
484 ROP2(cirrus_colorexpand_notsrc_or_dst
),
485 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
488 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
489 ROP2(cirrus_colorexpand_pattern_transp_0
),
490 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
491 ROP_NOP2(cirrus_bitblt_rop_nop
),
492 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
493 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
494 ROP2(cirrus_colorexpand_pattern_transp_src
),
495 ROP2(cirrus_colorexpand_pattern_transp_1
),
496 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
497 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
498 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
499 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
500 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
501 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
502 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
503 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
504 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
507 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
508 ROP2(cirrus_colorexpand_pattern_0
),
509 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
510 ROP_NOP2(cirrus_bitblt_rop_nop
),
511 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
512 ROP2(cirrus_colorexpand_pattern_notdst
),
513 ROP2(cirrus_colorexpand_pattern_src
),
514 ROP2(cirrus_colorexpand_pattern_1
),
515 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
516 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
517 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
518 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
519 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
520 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
521 ROP2(cirrus_colorexpand_pattern_notsrc
),
522 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
523 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
526 static const cirrus_fill_t cirrus_fill
[16][4] = {
528 ROP2(cirrus_fill_src_and_dst
),
529 ROP_NOP2(cirrus_bitblt_fill_nop
),
530 ROP2(cirrus_fill_src_and_notdst
),
531 ROP2(cirrus_fill_notdst
),
532 ROP2(cirrus_fill_src
),
534 ROP2(cirrus_fill_notsrc_and_dst
),
535 ROP2(cirrus_fill_src_xor_dst
),
536 ROP2(cirrus_fill_src_or_dst
),
537 ROP2(cirrus_fill_notsrc_or_notdst
),
538 ROP2(cirrus_fill_src_notxor_dst
),
539 ROP2(cirrus_fill_src_or_notdst
),
540 ROP2(cirrus_fill_notsrc
),
541 ROP2(cirrus_fill_notsrc_or_dst
),
542 ROP2(cirrus_fill_notsrc_and_notdst
),
545 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
548 switch (s
->cirrus_blt_pixelwidth
) {
550 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
553 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8);
554 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
557 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
558 (s
->gr
[0x11] << 8) | (s
->gr
[0x13] << 16);
562 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8) |
563 (s
->gr
[0x13] << 16) | (s
->gr
[0x15] << 24);
564 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
569 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
572 switch (s
->cirrus_blt_pixelwidth
) {
574 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
577 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8);
578 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
581 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
582 (s
->gr
[0x10] << 8) | (s
->gr
[0x12] << 16);
586 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8) |
587 (s
->gr
[0x12] << 16) | (s
->gr
[0x14] << 24);
588 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
593 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
594 int off_pitch
, int bytesperline
,
601 for (y
= 0; y
< lines
; y
++) {
603 off_cur_end
= off_cur
+ bytesperline
;
604 off_cur
&= TARGET_PAGE_MASK
;
605 while (off_cur
< off_cur_end
) {
606 cpu_physical_memory_set_dirty(s
->vram_offset
+ off_cur
);
607 off_cur
+= TARGET_PAGE_SIZE
;
609 off_begin
+= off_pitch
;
613 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
* s
,
618 dst
= s
->vram_ptr
+ s
->cirrus_blt_dstaddr
;
619 (*s
->cirrus_rop
) (s
, dst
, src
,
620 s
->cirrus_blt_dstpitch
, 0,
621 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
622 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
623 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
624 s
->cirrus_blt_height
);
630 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
632 cirrus_fill_t rop_func
;
634 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
635 rop_func(s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
636 s
->cirrus_blt_dstpitch
,
637 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
638 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
639 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
640 s
->cirrus_blt_height
);
641 cirrus_bitblt_reset(s
);
645 /***************************************
647 * bitblt (video-to-video)
649 ***************************************/
651 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
653 return cirrus_bitblt_common_patterncopy(s
,
655 (s
->cirrus_blt_srcaddr
& ~7));
658 static void cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
666 depth
= s
->get_bpp((VGAState
*)s
) / 8;
667 s
->get_resolution((VGAState
*)s
, &width
, &height
);
670 sx
= (src
% (width
* depth
)) / depth
;
671 sy
= (src
/ (width
* depth
));
672 dx
= (dst
% (width
*depth
)) / depth
;
673 dy
= (dst
/ (width
* depth
));
675 /* normalize width */
678 /* if we're doing a backward copy, we have to adjust
679 our x/y to be the upper left corner (instead of the lower
681 if (s
->cirrus_blt_dstpitch
< 0) {
682 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
683 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
684 sy
-= s
->cirrus_blt_height
- 1;
685 dy
-= s
->cirrus_blt_height
- 1;
688 /* are we in the visible portion of memory? */
689 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
690 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
691 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
695 /* make to sure only copy if it's a plain copy ROP */
696 if (*s
->cirrus_rop
!= cirrus_bitblt_rop_fwd_src
&&
697 *s
->cirrus_rop
!= cirrus_bitblt_rop_bkwd_src
)
700 /* we have to flush all pending changes so that the copy
701 is generated at the appropriate moment in time */
705 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
706 s
->vram_ptr
+ s
->cirrus_blt_srcaddr
,
707 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
708 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
711 s
->ds
->dpy_copy(s
->ds
,
713 s
->cirrus_blt_width
/ depth
,
714 s
->cirrus_blt_height
);
716 /* we don't have to notify the display that this portion has
717 changed since dpy_copy implies this */
720 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
721 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
722 s
->cirrus_blt_height
);
725 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
727 if (s
->ds
->dpy_copy
) {
728 cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->start_addr
,
729 s
->cirrus_blt_srcaddr
- s
->start_addr
,
730 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
732 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
733 s
->vram_ptr
+ s
->cirrus_blt_srcaddr
,
734 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
735 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
737 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
738 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
739 s
->cirrus_blt_height
);
745 /***************************************
747 * bitblt (cpu-to-video)
749 ***************************************/
751 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
756 if (s
->cirrus_srccounter
> 0) {
757 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
758 cirrus_bitblt_common_patterncopy(s
, s
->cirrus_bltbuf
);
760 s
->cirrus_srccounter
= 0;
761 cirrus_bitblt_reset(s
);
763 /* at least one scan line */
765 (*s
->cirrus_rop
)(s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
766 s
->cirrus_bltbuf
, 0, 0, s
->cirrus_blt_width
, 1);
767 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
768 s
->cirrus_blt_width
, 1);
769 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
770 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
771 if (s
->cirrus_srccounter
<= 0)
773 /* more bytes than needed can be transfered because of
774 word alignment, so we keep them for the next line */
775 /* XXX: keep alignment to speed up transfer */
776 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
777 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
778 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
779 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
780 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
781 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
786 /***************************************
790 ***************************************/
792 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
795 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
796 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
797 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
798 s
->cirrus_srccounter
= 0;
799 cirrus_update_memory_access(s
);
802 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
806 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
807 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
808 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
810 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
811 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
812 s
->cirrus_blt_srcpitch
= 8;
814 /* XXX: check for 24 bpp */
815 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
817 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
819 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
820 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
821 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
822 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
824 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
826 /* always align input size to 32 bits */
827 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
829 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
831 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
832 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
833 cirrus_update_memory_access(s
);
837 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
841 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
846 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
850 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
851 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
853 ret
= cirrus_bitblt_videotovideo_copy(s
);
856 cirrus_bitblt_reset(s
);
860 static void cirrus_bitblt_start(CirrusVGAState
* s
)
864 s
->gr
[0x31] |= CIRRUS_BLT_BUSY
;
866 s
->cirrus_blt_width
= (s
->gr
[0x20] | (s
->gr
[0x21] << 8)) + 1;
867 s
->cirrus_blt_height
= (s
->gr
[0x22] | (s
->gr
[0x23] << 8)) + 1;
868 s
->cirrus_blt_dstpitch
= (s
->gr
[0x24] | (s
->gr
[0x25] << 8));
869 s
->cirrus_blt_srcpitch
= (s
->gr
[0x26] | (s
->gr
[0x27] << 8));
870 s
->cirrus_blt_dstaddr
=
871 (s
->gr
[0x28] | (s
->gr
[0x29] << 8) | (s
->gr
[0x2a] << 16));
872 s
->cirrus_blt_srcaddr
=
873 (s
->gr
[0x2c] | (s
->gr
[0x2d] << 8) | (s
->gr
[0x2e] << 16));
874 s
->cirrus_blt_mode
= s
->gr
[0x30];
875 s
->cirrus_blt_modeext
= s
->gr
[0x33];
876 blt_rop
= s
->gr
[0x32];
879 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
882 s
->cirrus_blt_modeext
,
884 s
->cirrus_blt_height
,
885 s
->cirrus_blt_dstpitch
,
886 s
->cirrus_blt_srcpitch
,
887 s
->cirrus_blt_dstaddr
,
888 s
->cirrus_blt_srcaddr
,
892 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
893 case CIRRUS_BLTMODE_PIXELWIDTH8
:
894 s
->cirrus_blt_pixelwidth
= 1;
896 case CIRRUS_BLTMODE_PIXELWIDTH16
:
897 s
->cirrus_blt_pixelwidth
= 2;
899 case CIRRUS_BLTMODE_PIXELWIDTH24
:
900 s
->cirrus_blt_pixelwidth
= 3;
902 case CIRRUS_BLTMODE_PIXELWIDTH32
:
903 s
->cirrus_blt_pixelwidth
= 4;
907 printf("cirrus: bitblt - pixel width is unknown\n");
911 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
914 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
915 CIRRUS_BLTMODE_MEMSYSDEST
))
916 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
918 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
923 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
924 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
925 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
926 CIRRUS_BLTMODE_PATTERNCOPY
|
927 CIRRUS_BLTMODE_COLOREXPAND
)) ==
928 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
929 cirrus_bitblt_fgcol(s
);
930 cirrus_bitblt_solidfill(s
, blt_rop
);
932 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
933 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
934 CIRRUS_BLTMODE_COLOREXPAND
) {
936 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
937 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
938 cirrus_bitblt_bgcol(s
);
940 cirrus_bitblt_fgcol(s
);
941 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
943 cirrus_bitblt_fgcol(s
);
944 cirrus_bitblt_bgcol(s
);
945 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
947 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
948 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
949 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
950 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
951 cirrus_bitblt_bgcol(s
);
953 cirrus_bitblt_fgcol(s
);
954 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
956 cirrus_bitblt_fgcol(s
);
957 cirrus_bitblt_bgcol(s
);
958 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
961 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
964 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
965 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
966 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
967 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
969 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
973 // setup bitblt engine.
974 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
975 if (!cirrus_bitblt_cputovideo(s
))
977 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
978 if (!cirrus_bitblt_videotocpu(s
))
981 if (!cirrus_bitblt_videotovideo(s
))
987 cirrus_bitblt_reset(s
);
990 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
994 old_value
= s
->gr
[0x31];
995 s
->gr
[0x31] = reg_value
;
997 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
998 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
999 cirrus_bitblt_reset(s
);
1000 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
1001 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
1002 cirrus_bitblt_start(s
);
1007 /***************************************
1011 ***************************************/
1013 static void cirrus_get_offsets(VGAState
*s1
,
1014 uint32_t *pline_offset
,
1015 uint32_t *pstart_addr
,
1016 uint32_t *pline_compare
)
1018 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1019 uint32_t start_addr
, line_offset
, line_compare
;
1021 line_offset
= s
->cr
[0x13]
1022 | ((s
->cr
[0x1b] & 0x10) << 4);
1024 *pline_offset
= line_offset
;
1026 start_addr
= (s
->cr
[0x0c] << 8)
1028 | ((s
->cr
[0x1b] & 0x01) << 16)
1029 | ((s
->cr
[0x1b] & 0x0c) << 15)
1030 | ((s
->cr
[0x1d] & 0x80) << 12);
1031 *pstart_addr
= start_addr
;
1033 line_compare
= s
->cr
[0x18] |
1034 ((s
->cr
[0x07] & 0x10) << 4) |
1035 ((s
->cr
[0x09] & 0x40) << 3);
1036 *pline_compare
= line_compare
;
1039 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1043 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1046 break; /* Sierra HiColor */
1049 break; /* XGA HiColor */
1052 printf("cirrus: invalid DAC value %x in 16bpp\n",
1053 (s
->cirrus_hidden_dac_data
& 0xf));
1061 static int cirrus_get_bpp(VGAState
*s1
)
1063 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1066 if ((s
->sr
[0x07] & 0x01) != 0) {
1068 switch (s
->sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1069 case CIRRUS_SR7_BPP_8
:
1072 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1073 ret
= cirrus_get_bpp16_depth(s
);
1075 case CIRRUS_SR7_BPP_24
:
1078 case CIRRUS_SR7_BPP_16
:
1079 ret
= cirrus_get_bpp16_depth(s
);
1081 case CIRRUS_SR7_BPP_32
:
1086 printf("cirrus: unknown bpp - sr7=%x\n", s
->sr
[0x7]);
1099 static void cirrus_get_resolution(VGAState
*s
, int *pwidth
, int *pheight
)
1103 width
= (s
->cr
[0x01] + 1) * 8;
1104 height
= s
->cr
[0x12] |
1105 ((s
->cr
[0x07] & 0x02) << 7) |
1106 ((s
->cr
[0x07] & 0x40) << 3);
1107 height
= (height
+ 1);
1108 /* interlace support */
1109 if (s
->cr
[0x1a] & 0x01)
1110 height
= height
* 2;
1115 /***************************************
1119 ***************************************/
1121 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1126 if ((s
->gr
[0x0b] & 0x01) != 0) /* dual bank */
1127 offset
= s
->gr
[0x09 + bank_index
];
1128 else /* single bank */
1129 offset
= s
->gr
[0x09];
1131 if ((s
->gr
[0x0b] & 0x20) != 0)
1136 if (s
->real_vram_size
<= offset
)
1139 limit
= s
->real_vram_size
- offset
;
1141 if (((s
->gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1142 if (limit
> 0x8000) {
1151 s
->cirrus_bank_base
[bank_index
] = offset
;
1152 s
->cirrus_bank_limit
[bank_index
] = limit
;
1154 s
->cirrus_bank_base
[bank_index
] = 0;
1155 s
->cirrus_bank_limit
[bank_index
] = 0;
1159 /***************************************
1161 * I/O access between 0x3c4-0x3c5
1163 ***************************************/
1166 cirrus_hook_read_sr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1168 switch (reg_index
) {
1169 case 0x00: // Standard VGA
1170 case 0x01: // Standard VGA
1171 case 0x02: // Standard VGA
1172 case 0x03: // Standard VGA
1173 case 0x04: // Standard VGA
1174 return CIRRUS_HOOK_NOT_HANDLED
;
1175 case 0x06: // Unlock Cirrus extensions
1176 *reg_value
= s
->sr
[reg_index
];
1181 case 0x70: // Graphics Cursor X
1185 case 0xf0: // Graphics Cursor X
1186 *reg_value
= s
->sr
[0x10];
1191 case 0x71: // Graphics Cursor Y
1195 case 0xf1: // Graphics Cursor Y
1196 *reg_value
= s
->sr
[0x11];
1199 case 0x07: // Extended Sequencer Mode
1200 case 0x08: // EEPROM Control
1201 case 0x09: // Scratch Register 0
1202 case 0x0a: // Scratch Register 1
1203 case 0x0b: // VCLK 0
1204 case 0x0c: // VCLK 1
1205 case 0x0d: // VCLK 2
1206 case 0x0e: // VCLK 3
1207 case 0x0f: // DRAM Control
1208 case 0x12: // Graphics Cursor Attribute
1209 case 0x13: // Graphics Cursor Pattern Address
1210 case 0x14: // Scratch Register 2
1211 case 0x15: // Scratch Register 3
1212 case 0x16: // Performance Tuning Register
1213 case 0x17: // Configuration Readback and Extended Control
1214 case 0x18: // Signature Generator Control
1215 case 0x19: // Signal Generator Result
1216 case 0x1a: // Signal Generator Result
1217 case 0x1b: // VCLK 0 Denominator & Post
1218 case 0x1c: // VCLK 1 Denominator & Post
1219 case 0x1d: // VCLK 2 Denominator & Post
1220 case 0x1e: // VCLK 3 Denominator & Post
1221 case 0x1f: // BIOS Write Enable and MCLK select
1223 printf("cirrus: handled inport sr_index %02x\n", reg_index
);
1225 *reg_value
= s
->sr
[reg_index
];
1229 printf("cirrus: inport sr_index %02x\n", reg_index
);
1235 return CIRRUS_HOOK_HANDLED
;
1239 cirrus_hook_write_sr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1241 switch (reg_index
) {
1242 case 0x00: // Standard VGA
1243 case 0x01: // Standard VGA
1244 case 0x02: // Standard VGA
1245 case 0x03: // Standard VGA
1246 case 0x04: // Standard VGA
1247 return CIRRUS_HOOK_NOT_HANDLED
;
1248 case 0x06: // Unlock Cirrus extensions
1250 if (reg_value
== 0x12) {
1251 s
->sr
[reg_index
] = 0x12;
1253 s
->sr
[reg_index
] = 0x0f;
1259 case 0x70: // Graphics Cursor X
1263 case 0xf0: // Graphics Cursor X
1264 s
->sr
[0x10] = reg_value
;
1265 s
->hw_cursor_x
= (reg_value
<< 3) | (reg_index
>> 5);
1270 case 0x71: // Graphics Cursor Y
1274 case 0xf1: // Graphics Cursor Y
1275 s
->sr
[0x11] = reg_value
;
1276 s
->hw_cursor_y
= (reg_value
<< 3) | (reg_index
>> 5);
1278 case 0x07: // Extended Sequencer Mode
1279 case 0x08: // EEPROM Control
1280 case 0x09: // Scratch Register 0
1281 case 0x0a: // Scratch Register 1
1282 case 0x0b: // VCLK 0
1283 case 0x0c: // VCLK 1
1284 case 0x0d: // VCLK 2
1285 case 0x0e: // VCLK 3
1286 case 0x0f: // DRAM Control
1287 case 0x12: // Graphics Cursor Attribute
1288 case 0x13: // Graphics Cursor Pattern Address
1289 case 0x14: // Scratch Register 2
1290 case 0x15: // Scratch Register 3
1291 case 0x16: // Performance Tuning Register
1292 case 0x18: // Signature Generator Control
1293 case 0x19: // Signature Generator Result
1294 case 0x1a: // Signature Generator Result
1295 case 0x1b: // VCLK 0 Denominator & Post
1296 case 0x1c: // VCLK 1 Denominator & Post
1297 case 0x1d: // VCLK 2 Denominator & Post
1298 case 0x1e: // VCLK 3 Denominator & Post
1299 case 0x1f: // BIOS Write Enable and MCLK select
1300 s
->sr
[reg_index
] = reg_value
;
1302 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1303 reg_index
, reg_value
);
1306 case 0x17: // Configuration Readback and Extended Control
1307 s
->sr
[reg_index
] = (s
->sr
[reg_index
] & 0x38) | (reg_value
& 0xc7);
1308 cirrus_update_memory_access(s
);
1312 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index
,
1318 return CIRRUS_HOOK_HANDLED
;
1321 /***************************************
1323 * I/O access at 0x3c6
1325 ***************************************/
1327 static void cirrus_read_hidden_dac(CirrusVGAState
* s
, int *reg_value
)
1330 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1331 *reg_value
= s
->cirrus_hidden_dac_data
;
1332 s
->cirrus_hidden_dac_lockindex
= 0;
1336 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1338 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1339 s
->cirrus_hidden_dac_data
= reg_value
;
1340 #if defined(DEBUG_CIRRUS)
1341 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1344 s
->cirrus_hidden_dac_lockindex
= 0;
1347 /***************************************
1349 * I/O access at 0x3c9
1351 ***************************************/
1353 static int cirrus_hook_read_palette(CirrusVGAState
* s
, int *reg_value
)
1355 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1356 return CIRRUS_HOOK_NOT_HANDLED
;
1358 s
->cirrus_hidden_palette
[(s
->dac_read_index
& 0x0f) * 3 +
1360 if (++s
->dac_sub_index
== 3) {
1361 s
->dac_sub_index
= 0;
1362 s
->dac_read_index
++;
1364 return CIRRUS_HOOK_HANDLED
;
1367 static int cirrus_hook_write_palette(CirrusVGAState
* s
, int reg_value
)
1369 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1370 return CIRRUS_HOOK_NOT_HANDLED
;
1371 s
->dac_cache
[s
->dac_sub_index
] = reg_value
;
1372 if (++s
->dac_sub_index
== 3) {
1373 memcpy(&s
->cirrus_hidden_palette
[(s
->dac_write_index
& 0x0f) * 3],
1375 /* XXX update cursor */
1376 s
->dac_sub_index
= 0;
1377 s
->dac_write_index
++;
1379 return CIRRUS_HOOK_HANDLED
;
1382 /***************************************
1384 * I/O access between 0x3ce-0x3cf
1386 ***************************************/
1389 cirrus_hook_read_gr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1391 switch (reg_index
) {
1392 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1393 *reg_value
= s
->cirrus_shadow_gr0
;
1394 return CIRRUS_HOOK_HANDLED
;
1395 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1396 *reg_value
= s
->cirrus_shadow_gr1
;
1397 return CIRRUS_HOOK_HANDLED
;
1398 case 0x02: // Standard VGA
1399 case 0x03: // Standard VGA
1400 case 0x04: // Standard VGA
1401 case 0x06: // Standard VGA
1402 case 0x07: // Standard VGA
1403 case 0x08: // Standard VGA
1404 return CIRRUS_HOOK_NOT_HANDLED
;
1405 case 0x05: // Standard VGA, Cirrus extended mode
1410 if (reg_index
< 0x3a) {
1411 *reg_value
= s
->gr
[reg_index
];
1414 printf("cirrus: inport gr_index %02x\n", reg_index
);
1419 return CIRRUS_HOOK_HANDLED
;
1423 cirrus_hook_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1425 #if defined(DEBUG_BITBLT) && 0
1426 printf("gr%02x: %02x\n", reg_index
, reg_value
);
1428 switch (reg_index
) {
1429 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1430 s
->cirrus_shadow_gr0
= reg_value
;
1431 return CIRRUS_HOOK_NOT_HANDLED
;
1432 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1433 s
->cirrus_shadow_gr1
= reg_value
;
1434 return CIRRUS_HOOK_NOT_HANDLED
;
1435 case 0x02: // Standard VGA
1436 case 0x03: // Standard VGA
1437 case 0x04: // Standard VGA
1438 case 0x06: // Standard VGA
1439 case 0x07: // Standard VGA
1440 case 0x08: // Standard VGA
1441 return CIRRUS_HOOK_NOT_HANDLED
;
1442 case 0x05: // Standard VGA, Cirrus extended mode
1443 s
->gr
[reg_index
] = reg_value
& 0x7f;
1444 cirrus_update_memory_access(s
);
1446 case 0x09: // bank offset #0
1447 case 0x0A: // bank offset #1
1448 s
->gr
[reg_index
] = reg_value
;
1449 cirrus_update_bank_ptr(s
, 0);
1450 cirrus_update_bank_ptr(s
, 1);
1453 s
->gr
[reg_index
] = reg_value
;
1454 cirrus_update_bank_ptr(s
, 0);
1455 cirrus_update_bank_ptr(s
, 1);
1456 cirrus_update_memory_access(s
);
1458 case 0x10: // BGCOLOR 0x0000ff00
1459 case 0x11: // FGCOLOR 0x0000ff00
1460 case 0x12: // BGCOLOR 0x00ff0000
1461 case 0x13: // FGCOLOR 0x00ff0000
1462 case 0x14: // BGCOLOR 0xff000000
1463 case 0x15: // FGCOLOR 0xff000000
1464 case 0x20: // BLT WIDTH 0x0000ff
1465 case 0x22: // BLT HEIGHT 0x0000ff
1466 case 0x24: // BLT DEST PITCH 0x0000ff
1467 case 0x26: // BLT SRC PITCH 0x0000ff
1468 case 0x28: // BLT DEST ADDR 0x0000ff
1469 case 0x29: // BLT DEST ADDR 0x00ff00
1470 case 0x2c: // BLT SRC ADDR 0x0000ff
1471 case 0x2d: // BLT SRC ADDR 0x00ff00
1472 case 0x2f: // BLT WRITEMASK
1473 case 0x30: // BLT MODE
1474 case 0x32: // RASTER OP
1475 case 0x33: // BLT MODEEXT
1476 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1477 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1478 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1479 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1480 s
->gr
[reg_index
] = reg_value
;
1482 case 0x21: // BLT WIDTH 0x001f00
1483 case 0x23: // BLT HEIGHT 0x001f00
1484 case 0x25: // BLT DEST PITCH 0x001f00
1485 case 0x27: // BLT SRC PITCH 0x001f00
1486 s
->gr
[reg_index
] = reg_value
& 0x1f;
1488 case 0x2a: // BLT DEST ADDR 0x3f0000
1489 s
->gr
[reg_index
] = reg_value
& 0x3f;
1490 /* if auto start mode, starts bit blt now */
1491 if (s
->gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1492 cirrus_bitblt_start(s
);
1495 case 0x2e: // BLT SRC ADDR 0x3f0000
1496 s
->gr
[reg_index
] = reg_value
& 0x3f;
1498 case 0x31: // BLT STATUS/START
1499 cirrus_write_bitblt(s
, reg_value
);
1503 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index
,
1509 return CIRRUS_HOOK_HANDLED
;
1512 /***************************************
1514 * I/O access between 0x3d4-0x3d5
1516 ***************************************/
1519 cirrus_hook_read_cr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1521 switch (reg_index
) {
1522 case 0x00: // Standard VGA
1523 case 0x01: // Standard VGA
1524 case 0x02: // Standard VGA
1525 case 0x03: // Standard VGA
1526 case 0x04: // Standard VGA
1527 case 0x05: // Standard VGA
1528 case 0x06: // Standard VGA
1529 case 0x07: // Standard VGA
1530 case 0x08: // Standard VGA
1531 case 0x09: // Standard VGA
1532 case 0x0a: // Standard VGA
1533 case 0x0b: // Standard VGA
1534 case 0x0c: // Standard VGA
1535 case 0x0d: // Standard VGA
1536 case 0x0e: // Standard VGA
1537 case 0x0f: // Standard VGA
1538 case 0x10: // Standard VGA
1539 case 0x11: // Standard VGA
1540 case 0x12: // Standard VGA
1541 case 0x13: // Standard VGA
1542 case 0x14: // Standard VGA
1543 case 0x15: // Standard VGA
1544 case 0x16: // Standard VGA
1545 case 0x17: // Standard VGA
1546 case 0x18: // Standard VGA
1547 return CIRRUS_HOOK_NOT_HANDLED
;
1548 case 0x19: // Interlace End
1549 case 0x1a: // Miscellaneous Control
1550 case 0x1b: // Extended Display Control
1551 case 0x1c: // Sync Adjust and Genlock
1552 case 0x1d: // Overlay Extended Control
1553 case 0x22: // Graphics Data Latches Readback (R)
1554 case 0x24: // Attribute Controller Toggle Readback (R)
1555 case 0x25: // Part Status
1556 case 0x27: // Part ID (R)
1557 *reg_value
= s
->cr
[reg_index
];
1559 case 0x26: // Attribute Controller Index Readback (R)
1560 *reg_value
= s
->ar_index
& 0x3f;
1564 printf("cirrus: inport cr_index %02x\n", reg_index
);
1570 return CIRRUS_HOOK_HANDLED
;
1574 cirrus_hook_write_cr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1576 switch (reg_index
) {
1577 case 0x00: // Standard VGA
1578 case 0x01: // Standard VGA
1579 case 0x02: // Standard VGA
1580 case 0x03: // Standard VGA
1581 case 0x04: // Standard VGA
1582 case 0x05: // Standard VGA
1583 case 0x06: // Standard VGA
1584 case 0x07: // Standard VGA
1585 case 0x08: // Standard VGA
1586 case 0x09: // Standard VGA
1587 case 0x0a: // Standard VGA
1588 case 0x0b: // Standard VGA
1589 case 0x0c: // Standard VGA
1590 case 0x0d: // Standard VGA
1591 case 0x0e: // Standard VGA
1592 case 0x0f: // Standard VGA
1593 case 0x10: // Standard VGA
1594 case 0x11: // Standard VGA
1595 case 0x12: // Standard VGA
1596 case 0x13: // Standard VGA
1597 case 0x14: // Standard VGA
1598 case 0x15: // Standard VGA
1599 case 0x16: // Standard VGA
1600 case 0x17: // Standard VGA
1601 case 0x18: // Standard VGA
1602 return CIRRUS_HOOK_NOT_HANDLED
;
1603 case 0x19: // Interlace End
1604 case 0x1a: // Miscellaneous Control
1605 case 0x1b: // Extended Display Control
1606 case 0x1c: // Sync Adjust and Genlock
1607 case 0x1d: // Overlay Extended Control
1608 s
->cr
[reg_index
] = reg_value
;
1610 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1611 reg_index
, reg_value
);
1614 case 0x22: // Graphics Data Latches Readback (R)
1615 case 0x24: // Attribute Controller Toggle Readback (R)
1616 case 0x26: // Attribute Controller Index Readback (R)
1617 case 0x27: // Part ID (R)
1619 case 0x25: // Part Status
1622 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index
,
1628 return CIRRUS_HOOK_HANDLED
;
1631 /***************************************
1633 * memory-mapped I/O (bitblt)
1635 ***************************************/
1637 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1642 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1643 cirrus_hook_read_gr(s
, 0x00, &value
);
1645 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1646 cirrus_hook_read_gr(s
, 0x10, &value
);
1648 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1649 cirrus_hook_read_gr(s
, 0x12, &value
);
1651 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1652 cirrus_hook_read_gr(s
, 0x14, &value
);
1654 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1655 cirrus_hook_read_gr(s
, 0x01, &value
);
1657 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1658 cirrus_hook_read_gr(s
, 0x11, &value
);
1660 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1661 cirrus_hook_read_gr(s
, 0x13, &value
);
1663 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1664 cirrus_hook_read_gr(s
, 0x15, &value
);
1666 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1667 cirrus_hook_read_gr(s
, 0x20, &value
);
1669 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1670 cirrus_hook_read_gr(s
, 0x21, &value
);
1672 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1673 cirrus_hook_read_gr(s
, 0x22, &value
);
1675 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1676 cirrus_hook_read_gr(s
, 0x23, &value
);
1678 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1679 cirrus_hook_read_gr(s
, 0x24, &value
);
1681 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1682 cirrus_hook_read_gr(s
, 0x25, &value
);
1684 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1685 cirrus_hook_read_gr(s
, 0x26, &value
);
1687 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1688 cirrus_hook_read_gr(s
, 0x27, &value
);
1690 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1691 cirrus_hook_read_gr(s
, 0x28, &value
);
1693 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1694 cirrus_hook_read_gr(s
, 0x29, &value
);
1696 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1697 cirrus_hook_read_gr(s
, 0x2a, &value
);
1699 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1700 cirrus_hook_read_gr(s
, 0x2c, &value
);
1702 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1703 cirrus_hook_read_gr(s
, 0x2d, &value
);
1705 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1706 cirrus_hook_read_gr(s
, 0x2e, &value
);
1708 case CIRRUS_MMIO_BLTWRITEMASK
:
1709 cirrus_hook_read_gr(s
, 0x2f, &value
);
1711 case CIRRUS_MMIO_BLTMODE
:
1712 cirrus_hook_read_gr(s
, 0x30, &value
);
1714 case CIRRUS_MMIO_BLTROP
:
1715 cirrus_hook_read_gr(s
, 0x32, &value
);
1717 case CIRRUS_MMIO_BLTMODEEXT
:
1718 cirrus_hook_read_gr(s
, 0x33, &value
);
1720 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1721 cirrus_hook_read_gr(s
, 0x34, &value
);
1723 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1724 cirrus_hook_read_gr(s
, 0x35, &value
);
1726 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1727 cirrus_hook_read_gr(s
, 0x38, &value
);
1729 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1730 cirrus_hook_read_gr(s
, 0x39, &value
);
1732 case CIRRUS_MMIO_BLTSTATUS
:
1733 cirrus_hook_read_gr(s
, 0x31, &value
);
1737 printf("cirrus: mmio read - address 0x%04x\n", address
);
1742 return (uint8_t) value
;
1745 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1749 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1750 cirrus_hook_write_gr(s
, 0x00, value
);
1752 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1753 cirrus_hook_write_gr(s
, 0x10, value
);
1755 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1756 cirrus_hook_write_gr(s
, 0x12, value
);
1758 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1759 cirrus_hook_write_gr(s
, 0x14, value
);
1761 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1762 cirrus_hook_write_gr(s
, 0x01, value
);
1764 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1765 cirrus_hook_write_gr(s
, 0x11, value
);
1767 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1768 cirrus_hook_write_gr(s
, 0x13, value
);
1770 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1771 cirrus_hook_write_gr(s
, 0x15, value
);
1773 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1774 cirrus_hook_write_gr(s
, 0x20, value
);
1776 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1777 cirrus_hook_write_gr(s
, 0x21, value
);
1779 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1780 cirrus_hook_write_gr(s
, 0x22, value
);
1782 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1783 cirrus_hook_write_gr(s
, 0x23, value
);
1785 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1786 cirrus_hook_write_gr(s
, 0x24, value
);
1788 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1789 cirrus_hook_write_gr(s
, 0x25, value
);
1791 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1792 cirrus_hook_write_gr(s
, 0x26, value
);
1794 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1795 cirrus_hook_write_gr(s
, 0x27, value
);
1797 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1798 cirrus_hook_write_gr(s
, 0x28, value
);
1800 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1801 cirrus_hook_write_gr(s
, 0x29, value
);
1803 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1804 cirrus_hook_write_gr(s
, 0x2a, value
);
1806 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1809 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1810 cirrus_hook_write_gr(s
, 0x2c, value
);
1812 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1813 cirrus_hook_write_gr(s
, 0x2d, value
);
1815 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1816 cirrus_hook_write_gr(s
, 0x2e, value
);
1818 case CIRRUS_MMIO_BLTWRITEMASK
:
1819 cirrus_hook_write_gr(s
, 0x2f, value
);
1821 case CIRRUS_MMIO_BLTMODE
:
1822 cirrus_hook_write_gr(s
, 0x30, value
);
1824 case CIRRUS_MMIO_BLTROP
:
1825 cirrus_hook_write_gr(s
, 0x32, value
);
1827 case CIRRUS_MMIO_BLTMODEEXT
:
1828 cirrus_hook_write_gr(s
, 0x33, value
);
1830 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1831 cirrus_hook_write_gr(s
, 0x34, value
);
1833 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1834 cirrus_hook_write_gr(s
, 0x35, value
);
1836 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1837 cirrus_hook_write_gr(s
, 0x38, value
);
1839 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1840 cirrus_hook_write_gr(s
, 0x39, value
);
1842 case CIRRUS_MMIO_BLTSTATUS
:
1843 cirrus_hook_write_gr(s
, 0x31, value
);
1847 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1854 /***************************************
1858 * assume TARGET_PAGE_SIZE >= 16
1860 ***************************************/
1862 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
1868 unsigned val
= mem_value
;
1871 dst
= s
->vram_ptr
+ offset
;
1872 for (x
= 0; x
< 8; x
++) {
1874 *dst
= s
->cirrus_shadow_gr1
;
1875 } else if (mode
== 5) {
1876 *dst
= s
->cirrus_shadow_gr0
;
1881 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1882 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 7);
1885 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
1891 unsigned val
= mem_value
;
1894 dst
= s
->vram_ptr
+ offset
;
1895 for (x
= 0; x
< 8; x
++) {
1897 *dst
= s
->cirrus_shadow_gr1
;
1898 *(dst
+ 1) = s
->gr
[0x11];
1899 } else if (mode
== 5) {
1900 *dst
= s
->cirrus_shadow_gr0
;
1901 *(dst
+ 1) = s
->gr
[0x10];
1906 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1907 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 15);
1910 /***************************************
1912 * memory access between 0xa0000-0xbffff
1914 ***************************************/
1916 static uint32_t cirrus_vga_mem_readb(void *opaque
, target_phys_addr_t addr
)
1918 CirrusVGAState
*s
= opaque
;
1919 unsigned bank_index
;
1920 unsigned bank_offset
;
1923 if ((s
->sr
[0x07] & 0x01) == 0) {
1924 return vga_mem_readb(s
, addr
);
1929 if (addr
< 0x10000) {
1930 /* XXX handle bitblt */
1932 bank_index
= addr
>> 15;
1933 bank_offset
= addr
& 0x7fff;
1934 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
1935 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
1936 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
1938 } else if (s
->gr
[0x0B] & 0x02) {
1941 bank_offset
&= s
->cirrus_addr_mask
;
1942 val
= *(s
->vram_ptr
+ bank_offset
);
1945 } else if (addr
>= 0x18000 && addr
< 0x18100) {
1946 /* memory-mapped I/O */
1948 if ((s
->sr
[0x17] & 0x44) == 0x04) {
1949 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
1954 printf("cirrus: mem_readb %06x\n", addr
);
1960 static uint32_t cirrus_vga_mem_readw(void *opaque
, target_phys_addr_t addr
)
1963 #ifdef TARGET_WORDS_BIGENDIAN
1964 v
= cirrus_vga_mem_readb(opaque
, addr
) << 8;
1965 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1);
1967 v
= cirrus_vga_mem_readb(opaque
, addr
);
1968 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
1973 static uint32_t cirrus_vga_mem_readl(void *opaque
, target_phys_addr_t addr
)
1976 #ifdef TARGET_WORDS_BIGENDIAN
1977 v
= cirrus_vga_mem_readb(opaque
, addr
) << 24;
1978 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 16;
1979 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 8;
1980 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3);
1982 v
= cirrus_vga_mem_readb(opaque
, addr
);
1983 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
1984 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 16;
1985 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3) << 24;
1990 static void cirrus_vga_mem_writeb(void *opaque
, target_phys_addr_t addr
,
1993 CirrusVGAState
*s
= opaque
;
1994 unsigned bank_index
;
1995 unsigned bank_offset
;
1998 if ((s
->sr
[0x07] & 0x01) == 0) {
1999 vga_mem_writeb(s
, addr
, mem_value
);
2005 if (addr
< 0x10000) {
2006 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2008 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
2009 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2010 cirrus_bitblt_cputovideo_next(s
);
2014 bank_index
= addr
>> 15;
2015 bank_offset
= addr
& 0x7fff;
2016 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2017 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2018 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2020 } else if (s
->gr
[0x0B] & 0x02) {
2023 bank_offset
&= s
->cirrus_addr_mask
;
2024 mode
= s
->gr
[0x05] & 0x7;
2025 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2026 *(s
->vram_ptr
+ bank_offset
) = mem_value
;
2027 cpu_physical_memory_set_dirty(s
->vram_offset
+
2030 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2031 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2035 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2042 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2043 /* memory-mapped I/O */
2044 if ((s
->sr
[0x17] & 0x44) == 0x04) {
2045 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2049 printf("cirrus: mem_writeb %06x value %02x\n", addr
, mem_value
);
2054 static void cirrus_vga_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2056 #ifdef TARGET_WORDS_BIGENDIAN
2057 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2058 cirrus_vga_mem_writeb(opaque
, addr
+ 1, val
& 0xff);
2060 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2061 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2065 static void cirrus_vga_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2067 #ifdef TARGET_WORDS_BIGENDIAN
2068 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2069 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2070 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2071 cirrus_vga_mem_writeb(opaque
, addr
+ 3, val
& 0xff);
2073 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2074 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2075 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2076 cirrus_vga_mem_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2080 static CPUReadMemoryFunc
*cirrus_vga_mem_read
[3] = {
2081 cirrus_vga_mem_readb
,
2082 cirrus_vga_mem_readw
,
2083 cirrus_vga_mem_readl
,
2086 static CPUWriteMemoryFunc
*cirrus_vga_mem_write
[3] = {
2087 cirrus_vga_mem_writeb
,
2088 cirrus_vga_mem_writew
,
2089 cirrus_vga_mem_writel
,
2092 /***************************************
2096 ***************************************/
2098 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2100 if (s
->last_hw_cursor_size
) {
2101 vga_invalidate_scanlines((VGAState
*)s
,
2102 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2103 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2107 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2111 int y
, y_min
, y_max
;
2113 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2114 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2115 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2118 for(y
= 0; y
< 64; y
++) {
2119 content
= ((uint32_t *)src
)[0] |
2120 ((uint32_t *)src
)[1] |
2121 ((uint32_t *)src
)[2] |
2122 ((uint32_t *)src
)[3];
2132 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2135 for(y
= 0; y
< 32; y
++) {
2136 content
= ((uint32_t *)src
)[0] |
2137 ((uint32_t *)(src
+ 128))[0];
2147 if (y_min
> y_max
) {
2148 s
->last_hw_cursor_y_start
= 0;
2149 s
->last_hw_cursor_y_end
= 0;
2151 s
->last_hw_cursor_y_start
= y_min
;
2152 s
->last_hw_cursor_y_end
= y_max
+ 1;
2156 /* NOTE: we do not currently handle the cursor bitmap change, so we
2157 update the cursor only if it moves. */
2158 static void cirrus_cursor_invalidate(VGAState
*s1
)
2160 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2163 if (!s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
) {
2166 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2171 /* invalidate last cursor and new cursor if any change */
2172 if (s
->last_hw_cursor_size
!= size
||
2173 s
->last_hw_cursor_x
!= s
->hw_cursor_x
||
2174 s
->last_hw_cursor_y
!= s
->hw_cursor_y
) {
2176 invalidate_cursor1(s
);
2178 s
->last_hw_cursor_size
= size
;
2179 s
->last_hw_cursor_x
= s
->hw_cursor_x
;
2180 s
->last_hw_cursor_y
= s
->hw_cursor_y
;
2181 /* compute the real cursor min and max y */
2182 cirrus_cursor_compute_yrange(s
);
2183 invalidate_cursor1(s
);
2187 static void cirrus_cursor_draw_line(VGAState
*s1
, uint8_t *d1
, int scr_y
)
2189 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2190 int w
, h
, bpp
, x1
, x2
, poffset
;
2191 unsigned int color0
, color1
;
2192 const uint8_t *palette
, *src
;
2195 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2197 /* fast test to see if the cursor intersects with the scan line */
2198 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2203 if (scr_y
< s
->hw_cursor_y
||
2204 scr_y
>= (s
->hw_cursor_y
+ h
))
2207 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2208 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2209 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2210 src
+= (scr_y
- s
->hw_cursor_y
) * 16;
2212 content
= ((uint32_t *)src
)[0] |
2213 ((uint32_t *)src
)[1] |
2214 ((uint32_t *)src
)[2] |
2215 ((uint32_t *)src
)[3];
2217 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2218 src
+= (scr_y
- s
->hw_cursor_y
) * 4;
2220 content
= ((uint32_t *)src
)[0] |
2221 ((uint32_t *)(src
+ 128))[0];
2223 /* if nothing to draw, no need to continue */
2228 x1
= s
->hw_cursor_x
;
2229 if (x1
>= s
->last_scr_width
)
2231 x2
= s
->hw_cursor_x
+ w
;
2232 if (x2
> s
->last_scr_width
)
2233 x2
= s
->last_scr_width
;
2235 palette
= s
->cirrus_hidden_palette
;
2236 color0
= s
->rgb_to_pixel(c6_to_8(palette
[0x0 * 3]),
2237 c6_to_8(palette
[0x0 * 3 + 1]),
2238 c6_to_8(palette
[0x0 * 3 + 2]));
2239 color1
= s
->rgb_to_pixel(c6_to_8(palette
[0xf * 3]),
2240 c6_to_8(palette
[0xf * 3 + 1]),
2241 c6_to_8(palette
[0xf * 3 + 2]));
2242 bpp
= ((s
->ds
->depth
+ 7) >> 3);
2244 switch(s
->ds
->depth
) {
2248 vga_draw_cursor_line_8(d1
, src
, poffset
, w
, color0
, color1
, 0xff);
2251 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0x7fff);
2254 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0xffff);
2257 vga_draw_cursor_line_32(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2262 /***************************************
2266 ***************************************/
2268 static uint32_t cirrus_linear_readb(void *opaque
, target_phys_addr_t addr
)
2270 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2273 addr
&= s
->cirrus_addr_mask
;
2275 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2276 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2277 /* memory-mapped I/O */
2278 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2280 /* XXX handle bitblt */
2284 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2286 } else if (s
->gr
[0x0B] & 0x02) {
2289 addr
&= s
->cirrus_addr_mask
;
2290 ret
= *(s
->vram_ptr
+ addr
);
2296 static uint32_t cirrus_linear_readw(void *opaque
, target_phys_addr_t addr
)
2299 #ifdef TARGET_WORDS_BIGENDIAN
2300 v
= cirrus_linear_readb(opaque
, addr
) << 8;
2301 v
|= cirrus_linear_readb(opaque
, addr
+ 1);
2303 v
= cirrus_linear_readb(opaque
, addr
);
2304 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2309 static uint32_t cirrus_linear_readl(void *opaque
, target_phys_addr_t addr
)
2312 #ifdef TARGET_WORDS_BIGENDIAN
2313 v
= cirrus_linear_readb(opaque
, addr
) << 24;
2314 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 16;
2315 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 8;
2316 v
|= cirrus_linear_readb(opaque
, addr
+ 3);
2318 v
= cirrus_linear_readb(opaque
, addr
);
2319 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2320 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 16;
2321 v
|= cirrus_linear_readb(opaque
, addr
+ 3) << 24;
2326 static void cirrus_linear_writeb(void *opaque
, target_phys_addr_t addr
,
2329 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2332 addr
&= s
->cirrus_addr_mask
;
2334 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2335 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2336 /* memory-mapped I/O */
2337 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2338 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2340 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2341 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2342 cirrus_bitblt_cputovideo_next(s
);
2346 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2348 } else if (s
->gr
[0x0B] & 0x02) {
2351 addr
&= s
->cirrus_addr_mask
;
2353 mode
= s
->gr
[0x05] & 0x7;
2354 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2355 *(s
->vram_ptr
+ addr
) = (uint8_t) val
;
2356 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2358 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2359 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2361 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2367 static void cirrus_linear_writew(void *opaque
, target_phys_addr_t addr
,
2370 #ifdef TARGET_WORDS_BIGENDIAN
2371 cirrus_linear_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2372 cirrus_linear_writeb(opaque
, addr
+ 1, val
& 0xff);
2374 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2375 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2379 static void cirrus_linear_writel(void *opaque
, target_phys_addr_t addr
,
2382 #ifdef TARGET_WORDS_BIGENDIAN
2383 cirrus_linear_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2384 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2385 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2386 cirrus_linear_writeb(opaque
, addr
+ 3, val
& 0xff);
2388 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2389 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2390 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2391 cirrus_linear_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2396 static CPUReadMemoryFunc
*cirrus_linear_read
[3] = {
2397 cirrus_linear_readb
,
2398 cirrus_linear_readw
,
2399 cirrus_linear_readl
,
2402 static CPUWriteMemoryFunc
*cirrus_linear_write
[3] = {
2403 cirrus_linear_writeb
,
2404 cirrus_linear_writew
,
2405 cirrus_linear_writel
,
2408 static void cirrus_linear_mem_writeb(void *opaque
, target_phys_addr_t addr
,
2411 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2413 addr
&= s
->cirrus_addr_mask
;
2414 *(s
->vram_ptr
+ addr
) = val
;
2415 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2418 static void cirrus_linear_mem_writew(void *opaque
, target_phys_addr_t addr
,
2421 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2423 addr
&= s
->cirrus_addr_mask
;
2424 cpu_to_le16w((uint16_t *)(s
->vram_ptr
+ addr
), val
);
2425 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2428 static void cirrus_linear_mem_writel(void *opaque
, target_phys_addr_t addr
,
2431 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2433 addr
&= s
->cirrus_addr_mask
;
2434 cpu_to_le32w((uint32_t *)(s
->vram_ptr
+ addr
), val
);
2435 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2438 /***************************************
2440 * system to screen memory access
2442 ***************************************/
2445 static uint32_t cirrus_linear_bitblt_readb(void *opaque
, target_phys_addr_t addr
)
2449 /* XXX handle bitblt */
2454 static uint32_t cirrus_linear_bitblt_readw(void *opaque
, target_phys_addr_t addr
)
2457 #ifdef TARGET_WORDS_BIGENDIAN
2458 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 8;
2459 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1);
2461 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2462 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2467 static uint32_t cirrus_linear_bitblt_readl(void *opaque
, target_phys_addr_t addr
)
2470 #ifdef TARGET_WORDS_BIGENDIAN
2471 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 24;
2472 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 16;
2473 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 8;
2474 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3);
2476 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2477 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2478 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 16;
2479 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3) << 24;
2484 static void cirrus_linear_bitblt_writeb(void *opaque
, target_phys_addr_t addr
,
2487 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2489 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2491 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2492 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2493 cirrus_bitblt_cputovideo_next(s
);
2498 static void cirrus_linear_bitblt_writew(void *opaque
, target_phys_addr_t addr
,
2501 #ifdef TARGET_WORDS_BIGENDIAN
2502 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2503 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, val
& 0xff);
2505 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2506 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2510 static void cirrus_linear_bitblt_writel(void *opaque
, target_phys_addr_t addr
,
2513 #ifdef TARGET_WORDS_BIGENDIAN
2514 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2515 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2516 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2517 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, val
& 0xff);
2519 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2520 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2521 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2522 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2527 static CPUReadMemoryFunc
*cirrus_linear_bitblt_read
[3] = {
2528 cirrus_linear_bitblt_readb
,
2529 cirrus_linear_bitblt_readw
,
2530 cirrus_linear_bitblt_readl
,
2533 static CPUWriteMemoryFunc
*cirrus_linear_bitblt_write
[3] = {
2534 cirrus_linear_bitblt_writeb
,
2535 cirrus_linear_bitblt_writew
,
2536 cirrus_linear_bitblt_writel
,
2541 #include "qemu-kvm.h"
2543 extern kvm_context_t kvm_context
;
2545 static void *set_vram_mapping(unsigned long begin
, unsigned long end
)
2547 void *vram_pointer
= NULL
;
2549 /* align begin and end address */
2550 begin
= begin
& TARGET_PAGE_MASK
;
2551 end
= begin
+ VGA_RAM_SIZE
;
2552 end
= (end
+ TARGET_PAGE_SIZE
-1 ) & TARGET_PAGE_MASK
;
2554 vram_pointer
= kvm_create_phys_mem(kvm_context
, begin
, end
- begin
, 1,
2557 if (vram_pointer
== NULL
) {
2558 printf("set_vram_mapping: cannot allocate memory: %m\n");
2562 memset(vram_pointer
, 0, end
- begin
);
2564 return vram_pointer
;
2567 static int unset_vram_mapping(unsigned long begin
, unsigned long end
)
2569 /* align begin and end address */
2570 end
= begin
+ VGA_RAM_SIZE
;
2571 begin
= begin
& TARGET_PAGE_MASK
;
2572 end
= (end
+ TARGET_PAGE_SIZE
-1 ) & TARGET_PAGE_MASK
;
2574 kvm_destroy_phys_mem(kvm_context
, begin
, end
- begin
);
2581 /* Compute the memory access functions */
2582 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2586 if ((s
->sr
[0x17] & 0x44) == 0x44) {
2588 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2591 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2593 } else if (s
->gr
[0x0B] & 0x02) {
2597 mode
= s
->gr
[0x05] & 0x7;
2598 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2600 if (kvm_allowed
&& s
->cirrus_lfb_addr
&& s
->cirrus_lfb_end
&&
2602 void *vram_pointer
, *old_vram
;
2604 vram_pointer
= set_vram_mapping(s
->cirrus_lfb_addr
,
2607 fprintf(stderr
, "NULL vram_pointer\n");
2609 old_vram
= vga_update_vram((VGAState
*)s
, vram_pointer
,
2611 qemu_free(old_vram
);
2613 s
->map_addr
= s
->cirrus_lfb_addr
;
2614 s
->map_end
= s
->cirrus_lfb_end
;
2617 s
->cirrus_linear_write
[0] = cirrus_linear_mem_writeb
;
2618 s
->cirrus_linear_write
[1] = cirrus_linear_mem_writew
;
2619 s
->cirrus_linear_write
[2] = cirrus_linear_mem_writel
;
2623 if (kvm_allowed
&& s
->cirrus_lfb_addr
&& s
->cirrus_lfb_end
&&
2626 void *old_vram
= NULL
;
2628 error
= unset_vram_mapping(s
->cirrus_lfb_addr
,
2631 old_vram
= vga_update_vram((VGAState
*)s
, NULL
,
2634 munmap(old_vram
, s
->map_addr
- s
->map_end
);
2635 s
->map_addr
= s
->map_end
= 0;
2638 s
->cirrus_linear_write
[0] = cirrus_linear_writeb
;
2639 s
->cirrus_linear_write
[1] = cirrus_linear_writew
;
2640 s
->cirrus_linear_write
[2] = cirrus_linear_writel
;
2648 static uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
2650 CirrusVGAState
*s
= opaque
;
2653 /* check port range access depending on color/monochrome mode */
2654 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2655 || (addr
>= 0x3d0 && addr
<= 0x3df
2656 && !(s
->msr
& MSR_COLOR_EMULATION
))) {
2661 if (s
->ar_flip_flop
== 0) {
2668 index
= s
->ar_index
& 0x1f;
2681 if (cirrus_hook_read_sr(s
, s
->sr_index
, &val
))
2683 val
= s
->sr
[s
->sr_index
];
2684 #ifdef DEBUG_VGA_REG
2685 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2689 cirrus_read_hidden_dac(s
, &val
);
2695 val
= s
->dac_write_index
;
2696 s
->cirrus_hidden_dac_lockindex
= 0;
2699 if (cirrus_hook_read_palette(s
, &val
))
2701 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
2702 if (++s
->dac_sub_index
== 3) {
2703 s
->dac_sub_index
= 0;
2704 s
->dac_read_index
++;
2717 if (cirrus_hook_read_gr(s
, s
->gr_index
, &val
))
2719 val
= s
->gr
[s
->gr_index
];
2720 #ifdef DEBUG_VGA_REG
2721 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2730 if (cirrus_hook_read_cr(s
, s
->cr_index
, &val
))
2732 val
= s
->cr
[s
->cr_index
];
2733 #ifdef DEBUG_VGA_REG
2734 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2739 /* just toggle to fool polling */
2740 s
->st01
^= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
2742 s
->ar_flip_flop
= 0;
2749 #if defined(DEBUG_VGA)
2750 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
2755 static void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
2757 CirrusVGAState
*s
= opaque
;
2760 /* check port range access depending on color/monochrome mode */
2761 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2762 || (addr
>= 0x3d0 && addr
<= 0x3df
2763 && !(s
->msr
& MSR_COLOR_EMULATION
)))
2767 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
2772 if (s
->ar_flip_flop
== 0) {
2776 index
= s
->ar_index
& 0x1f;
2779 s
->ar
[index
] = val
& 0x3f;
2782 s
->ar
[index
] = val
& ~0x10;
2788 s
->ar
[index
] = val
& ~0xc0;
2791 s
->ar
[index
] = val
& ~0xf0;
2794 s
->ar
[index
] = val
& ~0xf0;
2800 s
->ar_flip_flop
^= 1;
2803 s
->msr
= val
& ~0x10;
2809 if (cirrus_hook_write_sr(s
, s
->sr_index
, val
))
2811 #ifdef DEBUG_VGA_REG
2812 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
2814 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
2817 cirrus_write_hidden_dac(s
, val
);
2820 s
->dac_read_index
= val
;
2821 s
->dac_sub_index
= 0;
2825 s
->dac_write_index
= val
;
2826 s
->dac_sub_index
= 0;
2830 if (cirrus_hook_write_palette(s
, val
))
2832 s
->dac_cache
[s
->dac_sub_index
] = val
;
2833 if (++s
->dac_sub_index
== 3) {
2834 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
2835 s
->dac_sub_index
= 0;
2836 s
->dac_write_index
++;
2843 if (cirrus_hook_write_gr(s
, s
->gr_index
, val
))
2845 #ifdef DEBUG_VGA_REG
2846 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
2848 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
2856 if (cirrus_hook_write_cr(s
, s
->cr_index
, val
))
2858 #ifdef DEBUG_VGA_REG
2859 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
2861 /* handle CR0-7 protection */
2862 if ((s
->cr
[0x11] & 0x80) && s
->cr_index
<= 7) {
2863 /* can always write bit 4 of CR7 */
2864 if (s
->cr_index
== 7)
2865 s
->cr
[7] = (s
->cr
[7] & ~0x10) | (val
& 0x10);
2868 switch (s
->cr_index
) {
2869 case 0x01: /* horizontal display end */
2874 case 0x12: /* veritcal display end */
2875 s
->cr
[s
->cr_index
] = val
;
2879 s
->cr
[s
->cr_index
] = val
;
2885 s
->fcr
= val
& 0x10;
2890 /***************************************
2892 * memory-mapped I/O access
2894 ***************************************/
2896 static uint32_t cirrus_mmio_readb(void *opaque
, target_phys_addr_t addr
)
2898 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2900 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2902 if (addr
>= 0x100) {
2903 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2905 return vga_ioport_read(s
, addr
+ 0x3c0);
2909 static uint32_t cirrus_mmio_readw(void *opaque
, target_phys_addr_t addr
)
2912 #ifdef TARGET_WORDS_BIGENDIAN
2913 v
= cirrus_mmio_readb(opaque
, addr
) << 8;
2914 v
|= cirrus_mmio_readb(opaque
, addr
+ 1);
2916 v
= cirrus_mmio_readb(opaque
, addr
);
2917 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
2922 static uint32_t cirrus_mmio_readl(void *opaque
, target_phys_addr_t addr
)
2925 #ifdef TARGET_WORDS_BIGENDIAN
2926 v
= cirrus_mmio_readb(opaque
, addr
) << 24;
2927 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 16;
2928 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 8;
2929 v
|= cirrus_mmio_readb(opaque
, addr
+ 3);
2931 v
= cirrus_mmio_readb(opaque
, addr
);
2932 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
2933 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 16;
2934 v
|= cirrus_mmio_readb(opaque
, addr
+ 3) << 24;
2939 static void cirrus_mmio_writeb(void *opaque
, target_phys_addr_t addr
,
2942 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2944 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2946 if (addr
>= 0x100) {
2947 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
2949 vga_ioport_write(s
, addr
+ 0x3c0, val
);
2953 static void cirrus_mmio_writew(void *opaque
, target_phys_addr_t addr
,
2956 #ifdef TARGET_WORDS_BIGENDIAN
2957 cirrus_mmio_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2958 cirrus_mmio_writeb(opaque
, addr
+ 1, val
& 0xff);
2960 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
2961 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2965 static void cirrus_mmio_writel(void *opaque
, target_phys_addr_t addr
,
2968 #ifdef TARGET_WORDS_BIGENDIAN
2969 cirrus_mmio_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2970 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2971 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2972 cirrus_mmio_writeb(opaque
, addr
+ 3, val
& 0xff);
2974 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
2975 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2976 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2977 cirrus_mmio_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2982 static CPUReadMemoryFunc
*cirrus_mmio_read
[3] = {
2988 static CPUWriteMemoryFunc
*cirrus_mmio_write
[3] = {
2994 /* load/save state */
2996 static void cirrus_vga_save(QEMUFile
*f
, void *opaque
)
2998 CirrusVGAState
*s
= opaque
;
3001 pci_device_save(s
->pci_dev
, f
);
3003 qemu_put_be32s(f
, &s
->latch
);
3004 qemu_put_8s(f
, &s
->sr_index
);
3005 qemu_put_buffer(f
, s
->sr
, 256);
3006 qemu_put_8s(f
, &s
->gr_index
);
3007 qemu_put_8s(f
, &s
->cirrus_shadow_gr0
);
3008 qemu_put_8s(f
, &s
->cirrus_shadow_gr1
);
3009 qemu_put_buffer(f
, s
->gr
+ 2, 254);
3010 qemu_put_8s(f
, &s
->ar_index
);
3011 qemu_put_buffer(f
, s
->ar
, 21);
3012 qemu_put_be32s(f
, &s
->ar_flip_flop
);
3013 qemu_put_8s(f
, &s
->cr_index
);
3014 qemu_put_buffer(f
, s
->cr
, 256);
3015 qemu_put_8s(f
, &s
->msr
);
3016 qemu_put_8s(f
, &s
->fcr
);
3017 qemu_put_8s(f
, &s
->st00
);
3018 qemu_put_8s(f
, &s
->st01
);
3020 qemu_put_8s(f
, &s
->dac_state
);
3021 qemu_put_8s(f
, &s
->dac_sub_index
);
3022 qemu_put_8s(f
, &s
->dac_read_index
);
3023 qemu_put_8s(f
, &s
->dac_write_index
);
3024 qemu_put_buffer(f
, s
->dac_cache
, 3);
3025 qemu_put_buffer(f
, s
->palette
, 768);
3027 qemu_put_be32s(f
, &s
->bank_offset
);
3029 qemu_put_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
3030 qemu_put_8s(f
, &s
->cirrus_hidden_dac_data
);
3032 qemu_put_be32s(f
, &s
->hw_cursor_x
);
3033 qemu_put_be32s(f
, &s
->hw_cursor_y
);
3034 /* XXX: we do not save the bitblt state - we assume we do not save
3035 the state when the blitter is active */
3038 if (kvm_allowed
) { /* XXX: KVM images ought to be loadable in QEMU */
3039 qemu_put_be32s(f
, &s
->real_vram_size
);
3040 qemu_put_buffer(f
, s
->vram_ptr
, s
->real_vram_size
);
3045 static int cirrus_vga_load(QEMUFile
*f
, void *opaque
, int version_id
)
3047 CirrusVGAState
*s
= opaque
;
3053 if (s
->pci_dev
&& version_id
>= 2) {
3054 ret
= pci_device_load(s
->pci_dev
, f
);
3059 qemu_get_be32s(f
, &s
->latch
);
3060 qemu_get_8s(f
, &s
->sr_index
);
3061 qemu_get_buffer(f
, s
->sr
, 256);
3062 qemu_get_8s(f
, &s
->gr_index
);
3063 qemu_get_8s(f
, &s
->cirrus_shadow_gr0
);
3064 qemu_get_8s(f
, &s
->cirrus_shadow_gr1
);
3065 s
->gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
3066 s
->gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
3067 qemu_get_buffer(f
, s
->gr
+ 2, 254);
3068 qemu_get_8s(f
, &s
->ar_index
);
3069 qemu_get_buffer(f
, s
->ar
, 21);
3070 qemu_get_be32s(f
, &s
->ar_flip_flop
);
3071 qemu_get_8s(f
, &s
->cr_index
);
3072 qemu_get_buffer(f
, s
->cr
, 256);
3073 qemu_get_8s(f
, &s
->msr
);
3074 qemu_get_8s(f
, &s
->fcr
);
3075 qemu_get_8s(f
, &s
->st00
);
3076 qemu_get_8s(f
, &s
->st01
);
3078 qemu_get_8s(f
, &s
->dac_state
);
3079 qemu_get_8s(f
, &s
->dac_sub_index
);
3080 qemu_get_8s(f
, &s
->dac_read_index
);
3081 qemu_get_8s(f
, &s
->dac_write_index
);
3082 qemu_get_buffer(f
, s
->dac_cache
, 3);
3083 qemu_get_buffer(f
, s
->palette
, 768);
3085 qemu_get_be32s(f
, &s
->bank_offset
);
3087 qemu_get_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
3088 qemu_get_8s(f
, &s
->cirrus_hidden_dac_data
);
3090 qemu_get_be32s(f
, &s
->hw_cursor_x
);
3091 qemu_get_be32s(f
, &s
->hw_cursor_y
);
3096 qemu_get_be32s(f
, &real_vram_size
);
3097 if (real_vram_size
!= s
->real_vram_size
) {
3098 if (real_vram_size
> s
->real_vram_size
)
3099 real_vram_size
= s
->real_vram_size
;
3100 printf("%s: REAL_VRAM_SIZE MISMATCH !!!!!! SAVED=%d CURRENT=%d",
3101 __FUNCTION__
, real_vram_size
, s
->real_vram_size
);
3103 qemu_get_buffer(f
, s
->vram_ptr
, real_vram_size
);
3104 cirrus_update_memory_access(s
);
3110 s
->graphic_mode
= -1;
3111 cirrus_update_bank_ptr(s
, 0);
3112 cirrus_update_bank_ptr(s
, 1);
3116 /***************************************
3120 ***************************************/
3122 static void cirrus_init_common(CirrusVGAState
* s
, int device_id
, int is_pci
)
3124 int vga_io_memory
, i
;
3129 for(i
= 0;i
< 256; i
++)
3130 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
3131 rop_to_index
[CIRRUS_ROP_0
] = 0;
3132 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
3133 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
3134 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
3135 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
3136 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
3137 rop_to_index
[CIRRUS_ROP_1
] = 6;
3138 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
3139 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
3140 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
3141 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
3142 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
3143 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
3144 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
3145 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
3146 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
3149 register_ioport_write(0x3c0, 16, 1, vga_ioport_write
, s
);
3151 register_ioport_write(0x3b4, 2, 1, vga_ioport_write
, s
);
3152 register_ioport_write(0x3d4, 2, 1, vga_ioport_write
, s
);
3153 register_ioport_write(0x3ba, 1, 1, vga_ioport_write
, s
);
3154 register_ioport_write(0x3da, 1, 1, vga_ioport_write
, s
);
3156 register_ioport_read(0x3c0, 16, 1, vga_ioport_read
, s
);
3158 register_ioport_read(0x3b4, 2, 1, vga_ioport_read
, s
);
3159 register_ioport_read(0x3d4, 2, 1, vga_ioport_read
, s
);
3160 register_ioport_read(0x3ba, 1, 1, vga_ioport_read
, s
);
3161 register_ioport_read(0x3da, 1, 1, vga_ioport_read
, s
);
3163 vga_io_memory
= cpu_register_io_memory(0, cirrus_vga_mem_read
,
3164 cirrus_vga_mem_write
, s
);
3165 cpu_register_physical_memory(isa_mem_base
+ 0x000a0000, 0x20000,
3169 if (device_id
== CIRRUS_ID_CLGD5446
) {
3170 /* 4MB 64 bit memory config, always PCI */
3171 s
->sr
[0x1F] = 0x2d; // MemClock
3172 s
->gr
[0x18] = 0x0f; // fastest memory configuration
3176 s
->sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3177 s
->real_vram_size
= 4096 * 1024;
3181 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3182 s
->real_vram_size
= 2048 * 1024;
3185 s
->sr
[0x1F] = 0x22; // MemClock
3186 s
->sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
3188 s
->sr
[0x17] = CIRRUS_BUSTYPE_PCI
;
3190 s
->sr
[0x17] = CIRRUS_BUSTYPE_ISA
;
3191 s
->real_vram_size
= 2048 * 1024;
3192 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3194 s
->cr
[0x27] = device_id
;
3196 /* Win2K seems to assume that the pattern buffer is at 0xff
3198 memset(s
->vram_ptr
, 0xff, s
->real_vram_size
);
3200 s
->cirrus_hidden_dac_lockindex
= 5;
3201 s
->cirrus_hidden_dac_data
= 0;
3203 /* I/O handler for LFB */
3204 s
->cirrus_linear_io_addr
=
3205 cpu_register_io_memory(0, cirrus_linear_read
, cirrus_linear_write
,
3207 s
->cirrus_linear_write
= cpu_get_io_memory_write(s
->cirrus_linear_io_addr
);
3209 /* I/O handler for LFB */
3210 s
->cirrus_linear_bitblt_io_addr
=
3211 cpu_register_io_memory(0, cirrus_linear_bitblt_read
, cirrus_linear_bitblt_write
,
3214 /* I/O handler for memory-mapped I/O */
3215 s
->cirrus_mmio_io_addr
=
3216 cpu_register_io_memory(0, cirrus_mmio_read
, cirrus_mmio_write
, s
);
3218 /* XXX: s->vram_size must be a power of two */
3219 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
3220 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
3222 s
->get_bpp
= cirrus_get_bpp
;
3223 s
->get_offsets
= cirrus_get_offsets
;
3224 s
->get_resolution
= cirrus_get_resolution
;
3225 s
->cursor_invalidate
= cirrus_cursor_invalidate
;
3226 s
->cursor_draw_line
= cirrus_cursor_draw_line
;
3228 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save
, cirrus_vga_load
, s
);
3231 /***************************************
3235 ***************************************/
3237 void isa_cirrus_vga_init(DisplayState
*ds
, uint8_t *vga_ram_base
,
3238 unsigned long vga_ram_offset
, int vga_ram_size
)
3242 s
= qemu_mallocz(sizeof(CirrusVGAState
));
3244 vga_common_init((VGAState
*)s
,
3245 ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3246 cirrus_init_common(s
, CIRRUS_ID_CLGD5430
, 0);
3247 /* XXX ISA-LFB support */
3250 /***************************************
3254 ***************************************/
3256 static void cirrus_pci_lfb_map(PCIDevice
*d
, int region_num
,
3257 uint32_t addr
, uint32_t size
, int type
)
3259 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3261 /* XXX: add byte swapping apertures */
3262 cpu_register_physical_memory(addr
, s
->vram_size
,
3263 s
->cirrus_linear_io_addr
);
3266 s
->cirrus_lfb_addr
= addr
;
3267 s
->cirrus_lfb_end
= addr
+ VGA_RAM_SIZE
;
3269 if (s
->map_addr
&& (s
->cirrus_lfb_addr
!= s
->map_addr
) &&
3270 (s
->cirrus_lfb_end
!= s
->map_end
))
3271 printf("cirrus vga map change while on lfb mode\n");
3275 cpu_register_physical_memory(addr
+ 0x1000000, 0x400000,
3276 s
->cirrus_linear_bitblt_io_addr
);
3279 static void cirrus_pci_mmio_map(PCIDevice
*d
, int region_num
,
3280 uint32_t addr
, uint32_t size
, int type
)
3282 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3284 cpu_register_physical_memory(addr
, CIRRUS_PNPMMIO_SIZE
,
3285 s
->cirrus_mmio_io_addr
);
3288 void pci_cirrus_vga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
3289 unsigned long vga_ram_offset
, int vga_ram_size
)
3291 PCICirrusVGAState
*d
;
3296 device_id
= CIRRUS_ID_CLGD5446
;
3298 /* setup PCI configuration registers */
3299 d
= (PCICirrusVGAState
*)pci_register_device(bus
, "Cirrus VGA",
3300 sizeof(PCICirrusVGAState
),
3302 pci_conf
= d
->dev
.config
;
3303 pci_conf
[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS
& 0xff);
3304 pci_conf
[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS
>> 8);
3305 pci_conf
[0x02] = (uint8_t) (device_id
& 0xff);
3306 pci_conf
[0x03] = (uint8_t) (device_id
>> 8);
3307 pci_conf
[0x04] = PCI_COMMAND_IOACCESS
| PCI_COMMAND_MEMACCESS
;
3308 pci_conf
[0x0a] = PCI_CLASS_SUB_VGA
;
3309 pci_conf
[0x0b] = PCI_CLASS_BASE_DISPLAY
;
3310 pci_conf
[0x0e] = PCI_CLASS_HEADERTYPE_00h
;
3314 vga_common_init((VGAState
*)s
,
3315 ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3316 cirrus_init_common(s
, device_id
, 1);
3317 s
->pci_dev
= (PCIDevice
*)d
;
3319 /* setup memory space */
3321 /* memory #1 memory-mapped I/O */
3322 /* XXX: s->vram_size must be a power of two */
3323 pci_register_io_region((PCIDevice
*)d
, 0, 0x2000000,
3324 PCI_ADDRESS_SPACE_MEM_PREFETCH
, cirrus_pci_lfb_map
);
3325 if (device_id
== CIRRUS_ID_CLGD5446
) {
3326 pci_register_io_region((PCIDevice
*)d
, 1, CIRRUS_PNPMMIO_SIZE
,
3327 PCI_ADDRESS_SPACE_MEM
, cirrus_pci_mmio_map
);