6 #define CONFIG_X86_32 1
12 #define CONFIG_X86_64 1
16 #if defined(__i386__) || defined (__x86_64__)
41 #ifndef _ASM_X86_KVM_H
42 #define _ASM_X86_KVM_H
45 * KVM x86 specific structures and definitions
49 #include <asm/types.h>
50 #include <linux/ioctl.h>
52 /* Select x86 specific features in <linux/kvm.h> */
53 #define __KVM_HAVE_PIT
54 #define __KVM_HAVE_IOAPIC
55 #define __KVM_HAVE_DEVICE_ASSIGNMENT
56 #define __KVM_HAVE_MSI
57 #define __KVM_HAVE_USER_NMI
58 #define __KVM_HAVE_GUEST_DEBUG
59 #define __KVM_HAVE_MSIX
61 /* Architectural interrupt line count. */
62 #define KVM_NR_INTERRUPTS 256
64 struct kvm_memory_alias
{
65 __u32 slot
; /* this has a different namespace than memory slots */
67 __u64 guest_phys_addr
;
69 __u64 target_phys_addr
;
72 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
73 struct kvm_pic_state
{
74 __u8 last_irr
; /* edge detection */
75 __u8 irr
; /* interrupt request register */
76 __u8 imr
; /* interrupt mask register */
77 __u8 isr
; /* interrupt service register */
78 __u8 priority_add
; /* highest irq priority */
85 __u8 rotate_on_auto_eoi
;
86 __u8 special_fully_nested_mode
;
87 __u8 init4
; /* true if 4 byte init */
88 __u8 elcr
; /* PIIX edge/trigger selection */
92 #define KVM_IOAPIC_NUM_PINS 24
93 struct kvm_ioapic_state
{
103 __u8 delivery_mode
:3;
105 __u8 delivery_status
:1;
114 } redirtbl
[KVM_IOAPIC_NUM_PINS
];
117 #define KVM_IRQCHIP_PIC_MASTER 0
118 #define KVM_IRQCHIP_PIC_SLAVE 1
119 #define KVM_IRQCHIP_IOAPIC 2
121 /* for KVM_GET_REGS and KVM_SET_REGS */
123 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
124 __u64 rax
, rbx
, rcx
, rdx
;
125 __u64 rsi
, rdi
, rsp
, rbp
;
126 __u64 r8
, r9
, r10
, r11
;
127 __u64 r12
, r13
, r14
, r15
;
131 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
132 #define KVM_APIC_REG_SIZE 0x400
133 struct kvm_lapic_state
{
134 char regs
[KVM_APIC_REG_SIZE
];
142 __u8 present
, dpl
, db
, s
, l
, g
, avl
;
154 /* for KVM_GET_SREGS and KVM_SET_SREGS */
156 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
157 struct kvm_segment cs
, ds
, es
, fs
, gs
, ss
;
158 struct kvm_segment tr
, ldt
;
159 struct kvm_dtable gdt
, idt
;
160 __u64 cr0
, cr2
, cr3
, cr4
, cr8
;
163 __u64 interrupt_bitmap
[(KVM_NR_INTERRUPTS
+ 63) / 64];
166 /* for KVM_GET_FPU and KVM_SET_FPU */
171 __u8 ftwx
; /* in fxsave format */
181 struct kvm_msr_entry
{
187 /* for KVM_GET_MSRS and KVM_SET_MSRS */
189 __u32 nmsrs
; /* number of msrs in entries */
192 struct kvm_msr_entry entries
[0];
195 /* for KVM_GET_MSR_INDEX_LIST */
196 struct kvm_msr_list
{
197 __u32 nmsrs
; /* number of msrs in entries */
202 struct kvm_cpuid_entry
{
211 /* for KVM_SET_CPUID */
215 struct kvm_cpuid_entry entries
[0];
218 struct kvm_cpuid_entry2
{
229 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
230 #define KVM_CPUID_FLAG_STATEFUL_FUNC 2
231 #define KVM_CPUID_FLAG_STATE_READ_NEXT 4
233 /* for KVM_SET_CPUID2 */
237 struct kvm_cpuid_entry2 entries
[0];
240 /* for KVM_GET_PIT and KVM_SET_PIT */
241 struct kvm_pit_channel_state
{
242 __u32 count
; /* can be 65536 */
254 __s64 count_load_time
;
257 struct kvm_debug_exit_arch
{
265 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
266 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
267 #define KVM_GUESTDBG_INJECT_DB 0x00040000
268 #define KVM_GUESTDBG_INJECT_BP 0x00080000
270 /* for KVM_SET_GUEST_DEBUG */
271 struct kvm_guest_debug_arch
{
275 struct kvm_pit_state
{
276 struct kvm_pit_channel_state channels
[3];
279 struct kvm_reinject_control
{
283 #endif /* _ASM_X86_KVM_H */