hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28
  29 /* APIC Local Vector Table */
  30 #define APIC_LVT_TIMER   0
  31 #define APIC_LVT_THERMAL 1
  32 #define APIC_LVT_PERFORM 2
  33 #define APIC_LVT_LINT0   3
  34 #define APIC_LVT_LINT1   4
  35 #define APIC_LVT_ERROR   5
  36 #define APIC_LVT_NB      6
  37
  38 /* APIC delivery modes */
  39 #define APIC_DM_FIXED   0
  40 #define APIC_DM_LOWPRI  1
  41 #define APIC_DM_SMI     2
  42 #define APIC_DM_NMI     4
  43 #define APIC_DM_INIT    5
  44 #define APIC_DM_SIPI    6
  45 #define APIC_DM_EXTINT  7
  46
  47 /* APIC destination mode */
  48 #define APIC_DESTMODE_FLAT      0xf
  49 #define APIC_DESTMODE_CLUSTER   1
  50
  51 #define APIC_TRIGGER_EDGE  0
  52 #define APIC_TRIGGER_LEVEL 1
  53
  54 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  55 #define APIC_LVT_MASKED                 (1<<16)
  56 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  57 #define APIC_LVT_REMOTE_IRR             (1<<14)
  58 #define APIC_INPUT_POLARITY             (1<<13)
  59 #define APIC_SEND_PENDING               (1<<12)
  60
  61 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  62
  63 #define APIC_SV_ENABLE (1 << 8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 typedef struct APICState {
  69     CPUState *cpu_env;
  70     uint32_t apicbase;
  71     uint8_t id;
  72     uint8_t arb_id;
  73     uint8_t tpr;
  74     uint32_t spurious_vec;
  75     uint8_t log_dest;
  76     uint8_t dest_mode;
  77     uint32_t isr[8];  /* in service register */
  78     uint32_t tmr[8];  /* trigger mode register */
  79     uint32_t irr[8]; /* interrupt request register */
  80     uint32_t lvt[APIC_LVT_NB];
  81     uint32_t esr; /* error register */
  82     uint32_t icr[2];
  83
  84     uint32_t divide_conf;
  85     int count_shift;
  86     uint32_t initial_count;
  87     int64_t initial_count_load_time, next_time;
  88     QEMUTimer *timer;
  89 } APICState;
  90
  91 static int apic_io_memory;
  92 static APICState *local_apics[MAX_APICS + 1];
  93 static int last_apic_id = 0;
  94 static int apic_irq_delivered;
  95
  96
  97 static void apic_init_ipi(APICState *s);
  98 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
  99 static void apic_update_irq(APICState *s);
 100 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 101                                       uint8_t dest, uint8_t dest_mode);
 102
 103 /* Find first bit starting from msb */
 104 static int fls_bit(uint32_t value)
 105 {
 106     return 31 - clz32(value);
 107 }
 108
 109 /* Find first bit starting from lsb */
 110 static int ffs_bit(uint32_t value)
 111 {
 112     return ctz32(value);
 113 }
 114
 115 static inline void set_bit(uint32_t *tab, int index)
 116 {
 117     int i, mask;
 118     i = index >> 5;
 119     mask = 1 << (index & 0x1f);
 120     tab[i] |= mask;
 121 }
 122
 123 static inline void reset_bit(uint32_t *tab, int index)
 124 {
 125     int i, mask;
 126     i = index >> 5;
 127     mask = 1 << (index & 0x1f);
 128     tab[i] &= ~mask;
 129 }
 130
 131 static inline int get_bit(uint32_t *tab, int index)
 132 {
 133     int i, mask;
 134     i = index >> 5;
 135     mask = 1 << (index & 0x1f);
 136     return !!(tab[i] & mask);
 137 }
 138
 139 static void apic_local_deliver(CPUState *env, int vector)
 140 {
 141     APICState *s = env->apic_state;
 142     uint32_t lvt = s->lvt[vector];
 143     int trigger_mode;
 144
 145     if (lvt & APIC_LVT_MASKED)
 146         return;
 147
 148     switch ((lvt >> 8) & 7) {
 149     case APIC_DM_SMI:
 150         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 151         break;
 152
 153     case APIC_DM_NMI:
 154         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 155         break;
 156
 157     case APIC_DM_EXTINT:
 158         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 159         break;
 160
 161     case APIC_DM_FIXED:
 162         trigger_mode = APIC_TRIGGER_EDGE;
 163         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 164             (lvt & APIC_LVT_LEVEL_TRIGGER))
 165             trigger_mode = APIC_TRIGGER_LEVEL;
 166         apic_set_irq(s, lvt & 0xff, trigger_mode);
 167     }
 168 }
 169
 170 void apic_deliver_pic_intr(CPUState *env, int level)
 171 {
 172     if (level)
 173         apic_local_deliver(env, APIC_LVT_LINT0);
 174     else {
 175         APICState *s = env->apic_state;
 176         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 177
 178         switch ((lvt >> 8) & 7) {
 179         case APIC_DM_FIXED:
 180             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 181                 break;
 182             reset_bit(s->irr, lvt & 0xff);
 183             /* fall through */
 184         case APIC_DM_EXTINT:
 185             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 186             break;
 187         }
 188     }
 189 }
 190
 191 #define foreach_apic(apic, deliver_bitmask, code) \
 192 {\
 193     int __i, __j, __mask;\
 194     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 195         __mask = deliver_bitmask[__i];\
 196         if (__mask) {\
 197             for(__j = 0; __j < 32; __j++) {\
 198                 if (__mask & (1 << __j)) {\
 199                     apic = local_apics[__i * 32 + __j];\
 200                     if (apic) {\
 201                         code;\
 202                     }\
 203                 }\
 204             }\
 205         }\
 206     }\
 207 }
 208
 209 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 210                              uint8_t delivery_mode,
 211                              uint8_t vector_num, uint8_t polarity,
 212                              uint8_t trigger_mode)
 213 {
 214     APICState *apic_iter;
 215
 216     switch (delivery_mode) {
 217         case APIC_DM_LOWPRI:
 218             /* XXX: search for focus processor, arbitration */
 219             {
 220                 int i, d;
 221                 d = -1;
 222                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 223                     if (deliver_bitmask[i]) {
 224                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 225                         break;
 226                     }
 227                 }
 228                 if (d >= 0) {
 229                     apic_iter = local_apics[d];
 230                     if (apic_iter) {
 231                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 232                     }
 233                 }
 234             }
 235             return;
 236
 237         case APIC_DM_FIXED:
 238             break;
 239
 240         case APIC_DM_SMI:
 241             foreach_apic(apic_iter, deliver_bitmask,
 242                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 243             return;
 244
 245         case APIC_DM_NMI:
 246             foreach_apic(apic_iter, deliver_bitmask,
 247                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 248             return;
 249
 250         case APIC_DM_INIT:
 251             /* normal INIT IPI sent to processors */
 252             foreach_apic(apic_iter, deliver_bitmask,
 253                          apic_init_ipi(apic_iter) );
 254             return;
 255
 256         case APIC_DM_EXTINT:
 257             /* handled in I/O APIC code */
 258             break;
 259
 260         default:
 261             return;
 262     }
 263
 264     foreach_apic(apic_iter, deliver_bitmask,
 265                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 266 }
 267
 268 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 269                       uint8_t delivery_mode, uint8_t vector_num,
 270                       uint8_t polarity, uint8_t trigger_mode)
 271 {
 272     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 273
 274     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 275     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 276                      trigger_mode);
 277 }
 278
 279 void cpu_set_apic_base(CPUState *env, uint64_t val)
 280 {
 281     APICState *s = env->apic_state;
 282 #ifdef DEBUG_APIC
 283     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 284 #endif
 285     if (!s)
 286         return;
 287     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 288         s->apicbase = val;
 289     else
 290         s->apicbase = (val & 0xfffff000) |
 291             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 292     /* if disabled, cannot be enabled again */
 293     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 294         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 295         env->cpuid_features &= ~CPUID_APIC;
 296         s->spurious_vec &= ~APIC_SV_ENABLE;
 297     }
 298 }
 299
 300 uint64_t cpu_get_apic_base(CPUState *env)
 301 {
 302     APICState *s = env->apic_state;
 303 #ifdef DEBUG_APIC
 304     printf("cpu_get_apic_base: %016" PRIx64 "\n",
 305            s ? (uint64_t)s->apicbase: 0);
 306 #endif
 307     return s ? s->apicbase : 0;
 308 }
 309
 310 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 311 {
 312     APICState *s = env->apic_state;
 313     if (!s)
 314         return;
 315     s->tpr = (val & 0x0f) << 4;
 316     apic_update_irq(s);
 317 }
 318
 319 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 320 {
 321     APICState *s = env->apic_state;
 322     return s ? s->tpr >> 4 : 0;
 323 }
 324
 325 /* return -1 if no bit is set */
 326 static int get_highest_priority_int(uint32_t *tab)
 327 {
 328     int i;
 329     for(i = 7; i >= 0; i--) {
 330         if (tab[i] != 0) {
 331             return i * 32 + fls_bit(tab[i]);
 332         }
 333     }
 334     return -1;
 335 }
 336
 337 static int apic_get_ppr(APICState *s)
 338 {
 339     int tpr, isrv, ppr;
 340
 341     tpr = (s->tpr >> 4);
 342     isrv = get_highest_priority_int(s->isr);
 343     if (isrv < 0)
 344         isrv = 0;
 345     isrv >>= 4;
 346     if (tpr >= isrv)
 347         ppr = s->tpr;
 348     else
 349         ppr = isrv << 4;
 350     return ppr;
 351 }
 352
 353 static int apic_get_arb_pri(APICState *s)
 354 {
 355     /* XXX: arbitration */
 356     return 0;
 357 }
 358
 359 /* signal the CPU if an irq is pending */
 360 static void apic_update_irq(APICState *s)
 361 {
 362     int irrv, ppr;
 363     if (!(s->spurious_vec & APIC_SV_ENABLE))
 364         return;
 365     irrv = get_highest_priority_int(s->irr);
 366     if (irrv < 0)
 367         return;
 368     ppr = apic_get_ppr(s);
 369     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 370         return;
 371     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 372 }
 373
 374 void apic_reset_irq_delivered(void)
 375 {
 376     apic_irq_delivered = 0;
 377 }
 378
 379 int apic_get_irq_delivered(void)
 380 {
 381     return apic_irq_delivered;
 382 }
 383
 384 void apic_set_irq_delivered(void)
 385 {
 386     apic_irq_delivered = 1;
 387 }
 388
 389 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 390 {
 391     apic_irq_delivered += !get_bit(s->irr, vector_num);
 392
 393     set_bit(s->irr, vector_num);
 394     if (trigger_mode)
 395         set_bit(s->tmr, vector_num);
 396     else
 397         reset_bit(s->tmr, vector_num);
 398     apic_update_irq(s);
 399 }
 400
 401 static void apic_eoi(APICState *s)
 402 {
 403     int isrv;
 404     isrv = get_highest_priority_int(s->isr);
 405     if (isrv < 0)
 406         return;
 407     reset_bit(s->isr, isrv);
 408     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 409             set the remote IRR bit for level triggered interrupts. */
 410     apic_update_irq(s);
 411 }
 412
 413 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 414                                       uint8_t dest, uint8_t dest_mode)
 415 {
 416     APICState *apic_iter;
 417     int i;
 418
 419     if (dest_mode == 0) {
 420         if (dest == 0xff) {
 421             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 422         } else {
 423             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 424             set_bit(deliver_bitmask, dest);
 425         }
 426     } else {
 427         /* XXX: cluster mode */
 428         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 429         for(i = 0; i < MAX_APICS; i++) {
 430             apic_iter = local_apics[i];
 431             if (apic_iter) {
 432                 if (apic_iter->dest_mode == 0xf) {
 433                     if (dest & apic_iter->log_dest)
 434                         set_bit(deliver_bitmask, i);
 435                 } else if (apic_iter->dest_mode == 0x0) {
 436                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 437                         (dest & apic_iter->log_dest & 0x0f)) {
 438                         set_bit(deliver_bitmask, i);
 439                     }
 440                 }
 441             }
 442         }
 443     }
 444 }
 445
 446
 447 static void apic_init_ipi(APICState *s)
 448 {
 449     int i;
 450
 451     s->tpr = 0;
 452     s->spurious_vec = 0xff;
 453     s->log_dest = 0;
 454     s->dest_mode = 0xf;
 455     memset(s->isr, 0, sizeof(s->isr));
 456     memset(s->tmr, 0, sizeof(s->tmr));
 457     memset(s->irr, 0, sizeof(s->irr));
 458     for(i = 0; i < APIC_LVT_NB; i++)
 459         s->lvt[i] = 1 << 16; /* mask LVT */
 460     s->esr = 0;
 461     memset(s->icr, 0, sizeof(s->icr));
 462     s->divide_conf = 0;
 463     s->count_shift = 0;
 464     s->initial_count = 0;
 465     s->initial_count_load_time = 0;
 466     s->next_time = 0;
 467
 468     cpu_reset(s->cpu_env);
 469
 470     if (!(s->apicbase & MSR_IA32_APICBASE_BSP) &&
 471         (!kvm_enabled() || !qemu_kvm_irqchip_in_kernel()))
 472         s->cpu_env->halted = 1;
 473
 474     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 475         if (s->cpu_env)
 476             kvm_apic_init(s->cpu_env);
 477 }
 478
 479 /* send a SIPI message to the CPU to start it */
 480 static void apic_startup(APICState *s, int vector_num)
 481 {
 482     CPUState *env = s->cpu_env;
 483     if (!env->halted)
 484         return;
 485     env->eip = 0;
 486     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 487                            0xffff, 0);
 488     env->halted = 0;
 489     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 490         kvm_update_after_sipi(env);
 491 }
 492
 493 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 494                          uint8_t delivery_mode, uint8_t vector_num,
 495                          uint8_t polarity, uint8_t trigger_mode)
 496 {
 497     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 498     int dest_shorthand = (s->icr[0] >> 18) & 3;
 499     APICState *apic_iter;
 500
 501     switch (dest_shorthand) {
 502     case 0:
 503         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 504         break;
 505     case 1:
 506         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 507         set_bit(deliver_bitmask, s->id);
 508         break;
 509     case 2:
 510         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 511         break;
 512     case 3:
 513         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 514         reset_bit(deliver_bitmask, s->id);
 515         break;
 516     }
 517
 518     switch (delivery_mode) {
 519         case APIC_DM_INIT:
 520             {
 521                 int trig_mode = (s->icr[0] >> 15) & 1;
 522                 int level = (s->icr[0] >> 14) & 1;
 523                 if (level == 0 && trig_mode == 1) {
 524                     foreach_apic(apic_iter, deliver_bitmask,
 525                                  apic_iter->arb_id = apic_iter->id );
 526                     return;
 527                 }
 528             }
 529             break;
 530
 531         case APIC_DM_SIPI:
 532             foreach_apic(apic_iter, deliver_bitmask,
 533                          apic_startup(apic_iter, vector_num) );
 534             return;
 535     }
 536
 537     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 538                      trigger_mode);
 539 }
 540
 541 int apic_get_interrupt(CPUState *env)
 542 {
 543     APICState *s = env->apic_state;
 544     int intno;
 545
 546     /* if the APIC is installed or enabled, we let the 8259 handle the
 547        IRQs */
 548     if (!s)
 549         return -1;
 550     if (!(s->spurious_vec & APIC_SV_ENABLE))
 551         return -1;
 552
 553     /* XXX: spurious IRQ handling */
 554     intno = get_highest_priority_int(s->irr);
 555     if (intno < 0)
 556         return -1;
 557     if (s->tpr && intno <= s->tpr)
 558         return s->spurious_vec & 0xff;
 559     reset_bit(s->irr, intno);
 560     set_bit(s->isr, intno);
 561     apic_update_irq(s);
 562     return intno;
 563 }
 564
 565 int apic_accept_pic_intr(CPUState *env)
 566 {
 567     APICState *s = env->apic_state;
 568     uint32_t lvt0;
 569
 570     if (!s)
 571         return -1;
 572
 573     lvt0 = s->lvt[APIC_LVT_LINT0];
 574
 575     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 576         (lvt0 & APIC_LVT_MASKED) == 0)
 577         return 1;
 578
 579     return 0;
 580 }
 581
 582 static uint32_t apic_get_current_count(APICState *s)
 583 {
 584     int64_t d;
 585     uint32_t val;
 586     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 587         s->count_shift;
 588     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 589         /* periodic */
 590         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 591     } else {
 592         if (d >= s->initial_count)
 593             val = 0;
 594         else
 595             val = s->initial_count - d;
 596     }
 597     return val;
 598 }
 599
 600 static void apic_timer_update(APICState *s, int64_t current_time)
 601 {
 602     int64_t next_time, d;
 603
 604     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 605         d = (current_time - s->initial_count_load_time) >>
 606             s->count_shift;
 607         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 608             if (!s->initial_count)
 609                 goto no_timer;
 610             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 611         } else {
 612             if (d >= s->initial_count)
 613                 goto no_timer;
 614             d = (uint64_t)s->initial_count + 1;
 615         }
 616         next_time = s->initial_count_load_time + (d << s->count_shift);
 617         qemu_mod_timer(s->timer, next_time);
 618         s->next_time = next_time;
 619     } else {
 620     no_timer:
 621         qemu_del_timer(s->timer);
 622     }
 623 }
 624
 625 static void apic_timer(void *opaque)
 626 {
 627     APICState *s = opaque;
 628
 629     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 630     apic_timer_update(s, s->next_time);
 631 }
 632
 633 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 634 {
 635     return 0;
 636 }
 637
 638 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 639 {
 640     return 0;
 641 }
 642
 643 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 644 {
 645 }
 646
 647 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 648 {
 649 }
 650
 651 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 652 {
 653     CPUState *env;
 654     APICState *s;
 655     uint32_t val;
 656     int index;
 657
 658     env = cpu_single_env;
 659     if (!env)
 660         return 0;
 661     s = env->apic_state;
 662
 663     index = (addr >> 4) & 0xff;
 664     switch(index) {
 665     case 0x02: /* id */
 666         val = s->id << 24;
 667         break;
 668     case 0x03: /* version */
 669         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 670         break;
 671     case 0x08:
 672         val = s->tpr;
 673         break;
 674     case 0x09:
 675         val = apic_get_arb_pri(s);
 676         break;
 677     case 0x0a:
 678         /* ppr */
 679         val = apic_get_ppr(s);
 680         break;
 681     case 0x0b:
 682         val = 0;
 683         break;
 684     case 0x0d:
 685         val = s->log_dest << 24;
 686         break;
 687     case 0x0e:
 688         val = s->dest_mode << 28;
 689         break;
 690     case 0x0f:
 691         val = s->spurious_vec;
 692         break;
 693     case 0x10 ... 0x17:
 694         val = s->isr[index & 7];
 695         break;
 696     case 0x18 ... 0x1f:
 697         val = s->tmr[index & 7];
 698         break;
 699     case 0x20 ... 0x27:
 700         val = s->irr[index & 7];
 701         break;
 702     case 0x28:
 703         val = s->esr;
 704         break;
 705     case 0x30:
 706     case 0x31:
 707         val = s->icr[index & 1];
 708         break;
 709     case 0x32 ... 0x37:
 710         val = s->lvt[index - 0x32];
 711         break;
 712     case 0x38:
 713         val = s->initial_count;
 714         break;
 715     case 0x39:
 716         val = apic_get_current_count(s);
 717         break;
 718     case 0x3e:
 719         val = s->divide_conf;
 720         break;
 721     default:
 722         s->esr |= ESR_ILLEGAL_ADDRESS;
 723         val = 0;
 724         break;
 725     }
 726 #ifdef DEBUG_APIC
 727     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 728 #endif
 729     return val;
 730 }
 731
 732 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 733 {
 734     CPUState *env;
 735     APICState *s;
 736     int index;
 737
 738     env = cpu_single_env;
 739     if (!env)
 740         return;
 741     s = env->apic_state;
 742
 743 #ifdef DEBUG_APIC
 744     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 745 #endif
 746
 747     index = (addr >> 4) & 0xff;
 748     switch(index) {
 749     case 0x02:
 750         s->id = (val >> 24);
 751         break;
 752     case 0x03:
 753         break;
 754     case 0x08:
 755         s->tpr = val;
 756         apic_update_irq(s);
 757         break;
 758     case 0x09:
 759     case 0x0a:
 760         break;
 761     case 0x0b: /* EOI */
 762         apic_eoi(s);
 763         break;
 764     case 0x0d:
 765         s->log_dest = val >> 24;
 766         break;
 767     case 0x0e:
 768         s->dest_mode = val >> 28;
 769         break;
 770     case 0x0f:
 771         s->spurious_vec = val & 0x1ff;
 772         apic_update_irq(s);
 773         break;
 774     case 0x10 ... 0x17:
 775     case 0x18 ... 0x1f:
 776     case 0x20 ... 0x27:
 777     case 0x28:
 778         break;
 779     case 0x30:
 780         s->icr[0] = val;
 781         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 782                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 783                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 784         break;
 785     case 0x31:
 786         s->icr[1] = val;
 787         break;
 788     case 0x32 ... 0x37:
 789         {
 790             int n = index - 0x32;
 791             s->lvt[n] = val;
 792             if (n == APIC_LVT_TIMER)
 793                 apic_timer_update(s, qemu_get_clock(vm_clock));
 794         }
 795         break;
 796     case 0x38:
 797         s->initial_count = val;
 798         s->initial_count_load_time = qemu_get_clock(vm_clock);
 799         apic_timer_update(s, s->initial_count_load_time);
 800         break;
 801     case 0x39:
 802         break;
 803     case 0x3e:
 804         {
 805             int v;
 806             s->divide_conf = val & 0xb;
 807             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 808             s->count_shift = (v + 1) & 7;
 809         }
 810         break;
 811     default:
 812         s->esr |= ESR_ILLEGAL_ADDRESS;
 813         break;
 814     }
 815 }
 816
 817 #ifdef KVM_CAP_IRQCHIP
 818
 819 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 820 {
 821     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 822 }
 823
 824 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 825                                  int reg_id, uint32_t val)
 826 {
 827     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 828 }
 829
 830 static void kvm_kernel_lapic_save_to_user(APICState *s)
 831 {
 832     struct kvm_lapic_state apic;
 833     struct kvm_lapic_state *kapic = &apic;
 834     int i, v;
 835
 836     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 837
 838     s->id = kapic_reg(kapic, 0x2) >> 24;
 839     s->tpr = kapic_reg(kapic, 0x8);
 840     s->arb_id = kapic_reg(kapic, 0x9);
 841     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 842     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 843     s->spurious_vec = kapic_reg(kapic, 0xf);
 844     for (i = 0; i < 8; i++) {
 845         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 846         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 847         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 848     }
 849     s->esr = kapic_reg(kapic, 0x28);
 850     s->icr[0] = kapic_reg(kapic, 0x30);
 851     s->icr[1] = kapic_reg(kapic, 0x31);
 852     for (i = 0; i < APIC_LVT_NB; i++)
 853         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 854     s->initial_count = kapic_reg(kapic, 0x38);
 855     s->divide_conf = kapic_reg(kapic, 0x3e);
 856
 857     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 858     s->count_shift = (v + 1) & 7;
 859
 860     s->initial_count_load_time = qemu_get_clock(vm_clock);
 861     apic_timer_update(s, s->initial_count_load_time);
 862 }
 863
 864 static void kvm_kernel_lapic_load_from_user(APICState *s)
 865 {
 866     struct kvm_lapic_state apic;
 867     struct kvm_lapic_state *klapic = &apic;
 868     int i;
 869
 870     memset(klapic, 0, sizeof apic);
 871     kapic_set_reg(klapic, 0x2, s->id << 24);
 872     kapic_set_reg(klapic, 0x8, s->tpr);
 873     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 874     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 875     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 876     for (i = 0; i < 8; i++) {
 877         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 878         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 879         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 880     }
 881     kapic_set_reg(klapic, 0x28, s->esr);
 882     kapic_set_reg(klapic, 0x30, s->icr[0]);
 883     kapic_set_reg(klapic, 0x31, s->icr[1]);
 884     for (i = 0; i < APIC_LVT_NB; i++)
 885         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 886     kapic_set_reg(klapic, 0x38, s->initial_count);
 887     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 888
 889     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 890 }
 891
 892 #endif
 893
 894 static void apic_save(QEMUFile *f, void *opaque)
 895 {
 896     APICState *s = opaque;
 897     int i;
 898
 899 #ifdef KVM_CAP_IRQCHIP
 900     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 901         kvm_kernel_lapic_save_to_user(s);
 902     }
 903 #endif
 904
 905     qemu_put_be32s(f, &s->apicbase);
 906     qemu_put_8s(f, &s->id);
 907     qemu_put_8s(f, &s->arb_id);
 908     qemu_put_8s(f, &s->tpr);
 909     qemu_put_be32s(f, &s->spurious_vec);
 910     qemu_put_8s(f, &s->log_dest);
 911     qemu_put_8s(f, &s->dest_mode);
 912     for (i = 0; i < 8; i++) {
 913         qemu_put_be32s(f, &s->isr[i]);
 914         qemu_put_be32s(f, &s->tmr[i]);
 915         qemu_put_be32s(f, &s->irr[i]);
 916     }
 917     for (i = 0; i < APIC_LVT_NB; i++) {
 918         qemu_put_be32s(f, &s->lvt[i]);
 919     }
 920     qemu_put_be32s(f, &s->esr);
 921     qemu_put_be32s(f, &s->icr[0]);
 922     qemu_put_be32s(f, &s->icr[1]);
 923     qemu_put_be32s(f, &s->divide_conf);
 924     qemu_put_be32(f, s->count_shift);
 925     qemu_put_be32s(f, &s->initial_count);
 926     qemu_put_be64(f, s->initial_count_load_time);
 927     qemu_put_be64(f, s->next_time);
 928
 929     qemu_put_timer(f, s->timer);
 930 }
 931
 932 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 933 {
 934     APICState *s = opaque;
 935     int i;
 936
 937     if (version_id > 2)
 938         return -EINVAL;
 939
 940     /* XXX: what if the base changes? (registered memory regions) */
 941     qemu_get_be32s(f, &s->apicbase);
 942     qemu_get_8s(f, &s->id);
 943     qemu_get_8s(f, &s->arb_id);
 944     qemu_get_8s(f, &s->tpr);
 945     qemu_get_be32s(f, &s->spurious_vec);
 946     qemu_get_8s(f, &s->log_dest);
 947     qemu_get_8s(f, &s->dest_mode);
 948     for (i = 0; i < 8; i++) {
 949         qemu_get_be32s(f, &s->isr[i]);
 950         qemu_get_be32s(f, &s->tmr[i]);
 951         qemu_get_be32s(f, &s->irr[i]);
 952     }
 953     for (i = 0; i < APIC_LVT_NB; i++) {
 954         qemu_get_be32s(f, &s->lvt[i]);
 955     }
 956     qemu_get_be32s(f, &s->esr);
 957     qemu_get_be32s(f, &s->icr[0]);
 958     qemu_get_be32s(f, &s->icr[1]);
 959     qemu_get_be32s(f, &s->divide_conf);
 960     s->count_shift=qemu_get_be32(f);
 961     qemu_get_be32s(f, &s->initial_count);
 962     s->initial_count_load_time=qemu_get_be64(f);
 963     s->next_time=qemu_get_be64(f);
 964
 965     if (version_id >= 2)
 966         qemu_get_timer(f, s->timer);
 967
 968 #ifdef KVM_CAP_IRQCHIP
 969     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 970         kvm_kernel_lapic_load_from_user(s);
 971     }
 972 #endif
 973
 974     return 0;
 975 }
 976
 977 static void apic_reset(void *opaque)
 978 {
 979     APICState *s = opaque;
 980
 981     s->apicbase = 0xfee00000 |
 982         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 983
 984     apic_init_ipi(s);
 985
 986     if (s->id == 0) {
 987         /*
 988          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 989          * time typically by BIOS, so PIC interrupt can be delivered to the
 990          * processor when local APIC is enabled.
 991          */
 992         s->lvt[APIC_LVT_LINT0] = 0x700;
 993     }
 994 #ifdef KVM_CAP_IRQCHIP
 995     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 996         kvm_kernel_lapic_load_from_user(s);
 997     }
 998 #endif
 999 }
1000
1001 static CPUReadMemoryFunc *apic_mem_read[3] = {
1002     apic_mem_readb,
1003     apic_mem_readw,
1004     apic_mem_readl,
1005 };
1006
1007 static CPUWriteMemoryFunc *apic_mem_write[3] = {
1008     apic_mem_writeb,
1009     apic_mem_writew,
1010     apic_mem_writel,
1011 };
1012
1013 int apic_init(CPUState *env)
1014 {
1015     APICState *s;
1016
1017     if (last_apic_id >= MAX_APICS)
1018         return -1;
1019     s = qemu_mallocz(sizeof(APICState));
1020     env->apic_state = s;
1021     s->id = last_apic_id++;
1022     env->cpuid_apic_id = s->id;
1023     s->cpu_env = env;
1024
1025     apic_reset(s);
1026
1027     /* XXX: mapping more APICs at the same memory location */
1028     if (apic_io_memory == 0) {
1029         /* NOTE: the APIC is directly connected to the CPU - it is not
1030            on the global memory bus. */
1031         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1032                                                 apic_mem_write, NULL);
1033         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1034                                      apic_io_memory);
1035     }
1036     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1037
1038     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
1039     qemu_register_reset(apic_reset, s);
1040
1041     local_apics[s->id] = s;
1042     return 0;
1043 }
1044