hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug PIC */
  27 //#define DEBUG_PIC
  28
  29 //#define DEBUG_IRQ_LATENCY
  30 //#define DEBUG_IRQ_COUNT
  31
  32 typedef struct PicState {
  33     uint8_t last_irr; /* edge detection */
  34     uint8_t irr; /* interrupt request register */
  35     uint8_t imr; /* interrupt mask register */
  36     uint8_t isr; /* interrupt service register */
  37     uint8_t priority_add; /* highest irq priority */
  38     uint8_t irq_base;
  39     uint8_t read_reg_select;
  40     uint8_t poll;
  41     uint8_t special_mask;
  42     uint8_t init_state;
  43     uint8_t auto_eoi;
  44     uint8_t rotate_on_auto_eoi;
  45     uint8_t special_fully_nested_mode;
  46     uint8_t init4; /* true if 4 byte init */
  47     uint8_t elcr; /* PIIX edge/trigger selection*/
  48     uint8_t elcr_mask;
  49     PicState2 *pics_state;
  50 } PicState;
  51
  52 struct PicState2 {
  53     /* 0 is master pic, 1 is slave pic */
  54     /* XXX: better separation between the two pics */
  55     PicState pics[2];
  56     IRQRequestFunc *irq_request;
  57     void *irq_request_opaque;
  58     /* IOAPIC callback support */
  59     SetIRQFunc *alt_irq_func;
  60     void *alt_irq_opaque;
  61 };
  62
  63 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  64 static int irq_level[16];
  65 #endif
  66 #ifdef DEBUG_IRQ_COUNT
  67 static uint64_t irq_count[16];
  68 #endif
  69
  70 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  71 static inline void pic_set_irq1(PicState *s, int irq, int level)
  72 {
  73     int mask;
  74     mask = 1 << irq;
  75     if (s->elcr & mask) {
  76         /* level triggered */
  77         if (level) {
  78             s->irr |= mask;
  79             s->last_irr |= mask;
  80         } else {
  81             s->irr &= ~mask;
  82             s->last_irr &= ~mask;
  83         }
  84     } else {
  85         /* edge triggered */
  86         if (level) {
  87             if ((s->last_irr & mask) == 0)
  88                 s->irr |= mask;
  89             s->last_irr |= mask;
  90         } else {
  91             s->last_irr &= ~mask;
  92         }
  93     }
  94 }
  95
  96 /* return the highest priority found in mask (highest = smallest
  97    number). Return 8 if no irq */
  98 static inline int get_priority(PicState *s, int mask)
  99 {
 100     int priority;
 101     if (mask == 0)
 102         return 8;
 103     priority = 0;
 104     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 105         priority++;
 106     return priority;
 107 }
 108
 109 /* return the pic wanted interrupt. return -1 if none */
 110 static int pic_get_irq(PicState *s)
 111 {
 112     int mask, cur_priority, priority;
 113
 114     mask = s->irr & ~s->imr;
 115     priority = get_priority(s, mask);
 116     if (priority == 8)
 117         return -1;
 118     /* compute current priority. If special fully nested mode on the
 119        master, the IRQ coming from the slave is not taken into account
 120        for the priority computation. */
 121     mask = s->isr;
 122     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 123         mask &= ~(1 << 2);
 124     cur_priority = get_priority(s, mask);
 125     if (priority < cur_priority) {
 126         /* higher priority found: an irq should be generated */
 127         return (priority + s->priority_add) & 7;
 128     } else {
 129         return -1;
 130     }
 131 }
 132
 133 /* raise irq to CPU if necessary. must be called every time the active
 134    irq may change */
 135 /* XXX: should not export it, but it is needed for an APIC kludge */
 136 void pic_update_irq(PicState2 *s)
 137 {
 138     int irq2, irq;
 139
 140     /* first look at slave pic */
 141     irq2 = pic_get_irq(&s->pics[1]);
 142     if (irq2 >= 0) {
 143         /* if irq request by slave pic, signal master PIC */
 144         pic_set_irq1(&s->pics[0], 2, 1);
 145         pic_set_irq1(&s->pics[0], 2, 0);
 146     }
 147     /* look at requested irq */
 148     irq = pic_get_irq(&s->pics[0]);
 149     if (irq >= 0) {
 150 #if defined(DEBUG_PIC)
 151         {
 152             int i;
 153             for(i = 0; i < 2; i++) {
 154                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 155                        i, s->pics[i].imr, s->pics[i].irr,
 156                        s->pics[i].priority_add);
 157
 158             }
 159         }
 160         printf("pic: cpu_interrupt\n");
 161 #endif
 162         s->irq_request(s->irq_request_opaque, 1);
 163     }
 164
 165 /* all targets should do this rather than acking the IRQ in the cpu */
 166 #if defined(TARGET_MIPS)
 167     else {
 168         s->irq_request(s->irq_request_opaque, 0);
 169     }
 170 #endif
 171 }
 172
 173 #ifdef DEBUG_IRQ_LATENCY
 174 int64_t irq_time[16];
 175 #endif
 176
 177 void pic_set_irq_new(void *opaque, int irq, int level)
 178 {
 179     PicState2 *s = opaque;
 180 #ifdef USE_KVM
 181     extern int kvm_set_irq(int irq, int level);
 182
 183     if (kvm_allowed)
 184         if (kvm_set_irq(irq, level))
 185             return;
 186 #endif
 187 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 188     if (level != irq_level[irq]) {
 189 #if defined(DEBUG_PIC)
 190         printf("pic_set_irq: irq=%d level=%d\n", irq, level);
 191 #endif
 192         irq_level[irq] = level;
 193 #ifdef DEBUG_IRQ_COUNT
 194         if (level == 1)
 195             irq_count[irq]++;
 196 #endif
 197     }
 198 #endif
 199 #ifdef DEBUG_IRQ_LATENCY
 200     if (level) {
 201         irq_time[irq] = qemu_get_clock(vm_clock);
 202     }
 203 #endif
 204     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 205     /* used for IOAPIC irqs */
 206     if (s->alt_irq_func)
 207         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 208     pic_update_irq(s);
 209 }
 210
 211 /* obsolete function */
 212 void pic_set_irq(int irq, int level)
 213 {
 214     pic_set_irq_new(isa_pic, irq, level);
 215 }
 216
 217 /* acknowledge interrupt 'irq' */
 218 static inline void pic_intack(PicState *s, int irq)
 219 {
 220     if (s->auto_eoi) {
 221         if (s->rotate_on_auto_eoi)
 222             s->priority_add = (irq + 1) & 7;
 223     } else {
 224         s->isr |= (1 << irq);
 225     }
 226     /* We don't clear a level sensitive interrupt here */
 227     if (!(s->elcr & (1 << irq)))
 228         s->irr &= ~(1 << irq);
 229
 230     if (time_drift_fix && irq == 0) {
 231         extern int64_t timer_acks, timer_ints_to_push;
 232         timer_acks++;
 233         if (timer_ints_to_push > 0) {
 234             timer_ints_to_push--;
 235             pic_set_irq(0, 0); /* set it low (edge irq)*/
 236             pic_set_irq(0, 1); /* interrupt again */
 237         }
 238     }
 239 }
 240
 241 int pic_read_irq(PicState2 *s)
 242 {
 243     int irq, irq2, intno;
 244
 245     irq = pic_get_irq(&s->pics[0]);
 246     if (irq >= 0) {
 247         pic_intack(&s->pics[0], irq);
 248         if (irq == 2) {
 249             irq2 = pic_get_irq(&s->pics[1]);
 250             if (irq2 >= 0) {
 251                 pic_intack(&s->pics[1], irq2);
 252             } else {
 253                 /* spurious IRQ on slave controller */
 254                 irq2 = 7;
 255             }
 256             intno = s->pics[1].irq_base + irq2;
 257             irq = irq2 + 8;
 258         } else {
 259             intno = s->pics[0].irq_base + irq;
 260         }
 261     } else {
 262         /* spurious IRQ on host controller */
 263         irq = 7;
 264         intno = s->pics[0].irq_base + irq;
 265     }
 266     pic_update_irq(s);
 267
 268 #ifdef DEBUG_IRQ_LATENCY
 269     printf("IRQ%d latency=%0.3fus\n",
 270            irq,
 271            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 272 #endif
 273 #if defined(DEBUG_PIC)
 274     printf("pic_interrupt: irq=%d\n", irq);
 275 #endif
 276     return intno;
 277 }
 278
 279 static void pic_reset(void *opaque)
 280 {
 281     PicState *s = opaque;
 282
 283     s->last_irr = 0;
 284     s->irr = 0;
 285     s->imr = 0;
 286     s->isr = 0;
 287     s->priority_add = 0;
 288     s->irq_base = 0;
 289     s->read_reg_select = 0;
 290     s->poll = 0;
 291     s->special_mask = 0;
 292     s->init_state = 0;
 293     s->auto_eoi = 0;
 294     s->rotate_on_auto_eoi = 0;
 295     s->special_fully_nested_mode = 0;
 296     s->init4 = 0;
 297     /* Note: ELCR is not reset */
 298 }
 299
 300 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 301 {
 302     PicState *s = opaque;
 303     int priority, cmd, irq;
 304
 305 #ifdef DEBUG_PIC
 306     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 307 #endif
 308     addr &= 1;
 309     if (addr == 0) {
 310         if (val & 0x10) {
 311             /* init */
 312             pic_reset(s);
 313             /* deassert a pending interrupt */
 314             s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
 315             s->init_state = 1;
 316             s->init4 = val & 1;
 317             if (val & 0x02)
 318                 hw_error("single mode not supported");
 319             if (val & 0x08)
 320                 hw_error("level sensitive irq not supported");
 321         } else if (val & 0x08) {
 322             if (val & 0x04)
 323                 s->poll = 1;
 324             if (val & 0x02)
 325                 s->read_reg_select = val & 1;
 326             if (val & 0x40)
 327                 s->special_mask = (val >> 5) & 1;
 328         } else {
 329             cmd = val >> 5;
 330             switch(cmd) {
 331             case 0:
 332             case 4:
 333                 s->rotate_on_auto_eoi = cmd >> 2;
 334                 break;
 335             case 1: /* end of interrupt */
 336             case 5:
 337                 priority = get_priority(s, s->isr);
 338                 if (priority != 8) {
 339                     irq = (priority + s->priority_add) & 7;
 340                     s->isr &= ~(1 << irq);
 341                     if (cmd == 5)
 342                         s->priority_add = (irq + 1) & 7;
 343                     pic_update_irq(s->pics_state);
 344                 }
 345                 break;
 346             case 3:
 347                 irq = val & 7;
 348                 s->isr &= ~(1 << irq);
 349                 pic_update_irq(s->pics_state);
 350                 break;
 351             case 6:
 352                 s->priority_add = (val + 1) & 7;
 353                 pic_update_irq(s->pics_state);
 354                 break;
 355             case 7:
 356                 irq = val & 7;
 357                 s->isr &= ~(1 << irq);
 358                 s->priority_add = (irq + 1) & 7;
 359                 pic_update_irq(s->pics_state);
 360                 break;
 361             default:
 362                 /* no operation */
 363                 break;
 364             }
 365         }
 366     } else {
 367         switch(s->init_state) {
 368         case 0:
 369             /* normal mode */
 370             s->imr = val;
 371             pic_update_irq(s->pics_state);
 372             break;
 373         case 1:
 374             s->irq_base = val & 0xf8;
 375             s->init_state = 2;
 376             break;
 377         case 2:
 378             if (s->init4) {
 379                 s->init_state = 3;
 380             } else {
 381                 s->init_state = 0;
 382             }
 383             break;
 384         case 3:
 385             s->special_fully_nested_mode = (val >> 4) & 1;
 386             s->auto_eoi = (val >> 1) & 1;
 387             s->init_state = 0;
 388             break;
 389         }
 390     }
 391 }
 392
 393 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 394 {
 395     int ret;
 396
 397     ret = pic_get_irq(s);
 398     if (ret >= 0) {
 399         if (addr1 >> 7) {
 400             s->pics_state->pics[0].isr &= ~(1 << 2);
 401             s->pics_state->pics[0].irr &= ~(1 << 2);
 402         }
 403         s->irr &= ~(1 << ret);
 404         s->isr &= ~(1 << ret);
 405         if (addr1 >> 7 || ret != 2)
 406             pic_update_irq(s->pics_state);
 407     } else {
 408         ret = 0x07;
 409         pic_update_irq(s->pics_state);
 410     }
 411
 412     return ret;
 413 }
 414
 415 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 416 {
 417     PicState *s = opaque;
 418     unsigned int addr;
 419     int ret;
 420
 421     addr = addr1;
 422     addr &= 1;
 423     if (s->poll) {
 424         ret = pic_poll_read(s, addr1);
 425         s->poll = 0;
 426     } else {
 427         if (addr == 0) {
 428             if (s->read_reg_select)
 429                 ret = s->isr;
 430             else
 431                 ret = s->irr;
 432         } else {
 433             ret = s->imr;
 434         }
 435     }
 436 #ifdef DEBUG_PIC
 437     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 438 #endif
 439     return ret;
 440 }
 441
 442 /* memory mapped interrupt status */
 443 /* XXX: may be the same than pic_read_irq() */
 444 uint32_t pic_intack_read(PicState2 *s)
 445 {
 446     int ret;
 447
 448     ret = pic_poll_read(&s->pics[0], 0x00);
 449     if (ret == 2)
 450         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 451     /* Prepare for ISR read */
 452     s->pics[0].read_reg_select = 1;
 453
 454     return ret;
 455 }
 456
 457 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 458 {
 459     PicState *s = opaque;
 460     s->elcr = val & s->elcr_mask;
 461 }
 462
 463 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 464 {
 465     PicState *s = opaque;
 466     return s->elcr;
 467 }
 468
 469 #ifdef USE_KVM
 470 #include "qemu-kvm.h"
 471 extern int kvm_allowed;
 472 extern kvm_context_t kvm_context;
 473
 474 static void kvm_kernel_pic_save_to_user(PicState *s)
 475 {
 476     struct kvm_irqchip chip;
 477     struct kvm_pic_state *kpic;
 478
 479     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 480                    KVM_IRQCHIP_PIC_MASTER :
 481                    KVM_IRQCHIP_PIC_SLAVE;
 482     kvm_get_irqchip(kvm_context, &chip);
 483     kpic = &chip.chip.pic;
 484
 485     s->last_irr = kpic->last_irr;
 486     s->irr = kpic->irr;
 487     s->imr = kpic->imr;
 488     s->isr = kpic->isr;
 489     s->priority_add = kpic->priority_add;
 490     s->irq_base = kpic->irq_base;
 491     s->read_reg_select = kpic->read_reg_select;
 492     s->poll = kpic->poll;
 493     s->special_mask = kpic->special_mask;
 494     s->init_state = kpic->init_state;
 495     s->auto_eoi = kpic->auto_eoi;
 496     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 497     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 498     s->init4 = kpic->init4;
 499     s->elcr = kpic->elcr;
 500     s->elcr_mask = kpic->elcr_mask;
 501 }
 502
 503 static void kvm_kernel_pic_load_from_user(PicState *s)
 504 {
 505     struct kvm_irqchip chip;
 506     struct kvm_pic_state *kpic;
 507
 508     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 509                    KVM_IRQCHIP_PIC_MASTER :
 510                    KVM_IRQCHIP_PIC_SLAVE;
 511     kpic = &chip.chip.pic;
 512
 513     kpic->last_irr = s->last_irr;
 514     kpic->irr = s->irr;
 515     kpic->imr = s->imr;
 516     kpic->isr = s->isr;
 517     kpic->priority_add = s->priority_add;
 518     kpic->irq_base = s->irq_base;
 519     kpic->read_reg_select = s->read_reg_select;
 520     kpic->poll = s->poll;
 521     kpic->special_mask = s->special_mask;
 522     kpic->init_state = s->init_state;
 523     kpic->auto_eoi = s->auto_eoi;
 524     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 525     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 526     kpic->init4 = s->init4;
 527     kpic->elcr = s->elcr;
 528     kpic->elcr_mask = s->elcr_mask;
 529
 530     kvm_set_irqchip(kvm_context, &chip);
 531 }
 532 #endif
 533
 534 static void pic_save(QEMUFile *f, void *opaque)
 535 {
 536     PicState *s = opaque;
 537
 538 #ifdef USE_KVM
 539     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 540         kvm_kernel_pic_save_to_user(s);
 541     }
 542 #endif
 543
 544     qemu_put_8s(f, &s->last_irr);
 545     qemu_put_8s(f, &s->irr);
 546     qemu_put_8s(f, &s->imr);
 547     qemu_put_8s(f, &s->isr);
 548     qemu_put_8s(f, &s->priority_add);
 549     qemu_put_8s(f, &s->irq_base);
 550     qemu_put_8s(f, &s->read_reg_select);
 551     qemu_put_8s(f, &s->poll);
 552     qemu_put_8s(f, &s->special_mask);
 553     qemu_put_8s(f, &s->init_state);
 554     qemu_put_8s(f, &s->auto_eoi);
 555     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 556     qemu_put_8s(f, &s->special_fully_nested_mode);
 557     qemu_put_8s(f, &s->init4);
 558     qemu_put_8s(f, &s->elcr);
 559 }
 560
 561 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 562 {
 563     PicState *s = opaque;
 564
 565     if (version_id != 1)
 566         return -EINVAL;
 567
 568     qemu_get_8s(f, &s->last_irr);
 569     qemu_get_8s(f, &s->irr);
 570     qemu_get_8s(f, &s->imr);
 571     qemu_get_8s(f, &s->isr);
 572     qemu_get_8s(f, &s->priority_add);
 573     qemu_get_8s(f, &s->irq_base);
 574     qemu_get_8s(f, &s->read_reg_select);
 575     qemu_get_8s(f, &s->poll);
 576     qemu_get_8s(f, &s->special_mask);
 577     qemu_get_8s(f, &s->init_state);
 578     qemu_get_8s(f, &s->auto_eoi);
 579     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 580     qemu_get_8s(f, &s->special_fully_nested_mode);
 581     qemu_get_8s(f, &s->init4);
 582     qemu_get_8s(f, &s->elcr);
 583
 584 #ifdef USE_KVM
 585     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 586         kvm_kernel_pic_load_from_user(s);
 587     }
 588 #endif
 589
 590     return 0;
 591 }
 592
 593 /* XXX: add generic master/slave system */
 594 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 595 {
 596     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 597     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 598     if (elcr_addr >= 0) {
 599         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 600         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 601     }
 602     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 603     qemu_register_reset(pic_reset, s);
 604 }
 605
 606 void pic_info(void)
 607 {
 608     int i;
 609     PicState *s;
 610
 611     if (!isa_pic)
 612         return;
 613
 614     for(i=0;i<2;i++) {
 615         s = &isa_pic->pics[i];
 616         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 617                     i, s->irr, s->imr, s->isr, s->priority_add,
 618                     s->irq_base, s->read_reg_select, s->elcr,
 619                     s->special_fully_nested_mode);
 620     }
 621 }
 622
 623 void irq_info(void)
 624 {
 625 #ifndef DEBUG_IRQ_COUNT
 626     term_printf("irq statistic code not compiled.\n");
 627 #else
 628     int i;
 629     int64_t count;
 630
 631     term_printf("IRQ statistics:\n");
 632     for (i = 0; i < 16; i++) {
 633         count = irq_count[i];
 634         if (count > 0)
 635             term_printf("%2d: %" PRId64 "\n", i, count);
 636     }
 637 #endif
 638 }
 639
 640 PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
 641 {
 642     PicState2 *s;
 643     s = qemu_mallocz(sizeof(PicState2));
 644     if (!s)
 645         return NULL;
 646     pic_init1(0x20, 0x4d0, &s->pics[0]);
 647     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 648     s->pics[0].elcr_mask = 0xf8;
 649     s->pics[1].elcr_mask = 0xde;
 650     s->irq_request = irq_request;
 651     s->irq_request_opaque = irq_request_opaque;
 652     s->pics[0].pics_state = s;
 653     s->pics[1].pics_state = s;
 654     return s;
 655 }
 656
 657 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 658                           void *alt_irq_opaque)
 659 {
 660     s->alt_irq_func = alt_irq_func;
 661     s->alt_irq_opaque = alt_irq_opaque;
 662 }