2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
10 #include "config-host.h"
18 #include <sys/utsname.h>
19 #include <linux/kvm_para.h>
21 #define MSR_IA32_TSC 0x10
23 static struct kvm_msr_list
*kvm_msr_list
;
24 extern unsigned int kvm_shadow_memory
;
25 extern kvm_context_t kvm_context
;
26 static int kvm_has_msr_star
;
28 static int lm_capable_kernel
;
30 int kvm_arch_qemu_create_context(void)
33 struct utsname utsname
;
36 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
38 if (kvm_shadow_memory
)
39 kvm_set_shadow_pages(kvm_context
, kvm_shadow_memory
);
41 kvm_msr_list
= kvm_get_msr_list(kvm_context
);
44 for (i
= 0; i
< kvm_msr_list
->nmsrs
; ++i
)
45 if (kvm_msr_list
->indices
[i
] == MSR_STAR
)
50 static void set_msr_entry(struct kvm_msr_entry
*entry
, uint32_t index
,
57 /* returns 0 on success, non-0 on failure */
58 static int get_msr_entry(struct kvm_msr_entry
*entry
, CPUState
*env
)
60 switch (entry
->index
) {
61 case MSR_IA32_SYSENTER_CS
:
62 env
->sysenter_cs
= entry
->data
;
64 case MSR_IA32_SYSENTER_ESP
:
65 env
->sysenter_esp
= entry
->data
;
67 case MSR_IA32_SYSENTER_EIP
:
68 env
->sysenter_eip
= entry
->data
;
71 env
->star
= entry
->data
;
75 env
->cstar
= entry
->data
;
77 case MSR_KERNELGSBASE
:
78 env
->kernelgsbase
= entry
->data
;
81 env
->fmask
= entry
->data
;
84 env
->lstar
= entry
->data
;
88 env
->tsc
= entry
->data
;
91 printf("Warning unknown msr index 0x%x\n", entry
->index
);
103 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
105 lhs
->selector
= rhs
->selector
;
106 lhs
->base
= rhs
->base
;
107 lhs
->limit
= rhs
->limit
;
119 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
121 unsigned flags
= rhs
->flags
;
122 lhs
->selector
= rhs
->selector
;
123 lhs
->base
= rhs
->base
;
124 lhs
->limit
= rhs
->limit
;
125 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
126 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
127 lhs
->dpl
= rhs
->selector
& 3;
128 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
129 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
130 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
131 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
132 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
136 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
138 lhs
->selector
= rhs
->selector
;
139 lhs
->base
= rhs
->base
;
140 lhs
->limit
= rhs
->limit
;
142 (rhs
->type
<< DESC_TYPE_SHIFT
)
143 | (rhs
->present
* DESC_P_MASK
)
144 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
145 | (rhs
->db
<< DESC_B_SHIFT
)
146 | (rhs
->s
* DESC_S_MASK
)
147 | (rhs
->l
<< DESC_L_SHIFT
)
148 | (rhs
->g
* DESC_G_MASK
)
149 | (rhs
->avl
* DESC_AVL_MASK
);
152 /* the reset values of qemu are not compatible to SVM
153 * this function is used to fix the segment descriptor values */
154 static void fix_realmode_dataseg(struct kvm_segment
*seg
)
161 void kvm_arch_load_regs(CPUState
*env
)
163 struct kvm_regs regs
;
165 struct kvm_sregs sregs
;
166 struct kvm_msr_entry msrs
[MSR_COUNT
];
169 regs
.rax
= env
->regs
[R_EAX
];
170 regs
.rbx
= env
->regs
[R_EBX
];
171 regs
.rcx
= env
->regs
[R_ECX
];
172 regs
.rdx
= env
->regs
[R_EDX
];
173 regs
.rsi
= env
->regs
[R_ESI
];
174 regs
.rdi
= env
->regs
[R_EDI
];
175 regs
.rsp
= env
->regs
[R_ESP
];
176 regs
.rbp
= env
->regs
[R_EBP
];
178 regs
.r8
= env
->regs
[8];
179 regs
.r9
= env
->regs
[9];
180 regs
.r10
= env
->regs
[10];
181 regs
.r11
= env
->regs
[11];
182 regs
.r12
= env
->regs
[12];
183 regs
.r13
= env
->regs
[13];
184 regs
.r14
= env
->regs
[14];
185 regs
.r15
= env
->regs
[15];
188 regs
.rflags
= env
->eflags
;
191 kvm_set_regs(kvm_context
, env
->cpu_index
, ®s
);
193 memset(&fpu
, 0, sizeof fpu
);
194 fpu
.fsw
= env
->fpus
& ~(7 << 11);
195 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
197 for (i
= 0; i
< 8; ++i
)
198 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
199 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
200 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
201 fpu
.mxcsr
= env
->mxcsr
;
202 kvm_set_fpu(kvm_context
, env
->cpu_index
, &fpu
);
204 memcpy(sregs
.interrupt_bitmap
, env
->kvm_interrupt_bitmap
, sizeof(sregs
.interrupt_bitmap
));
206 if ((env
->eflags
& VM_MASK
)) {
207 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
208 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
209 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
210 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
211 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
212 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
214 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
215 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
216 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
217 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
218 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
219 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
221 if (env
->cr
[0] & CR0_PE_MASK
) {
222 /* force ss cpl to cs cpl */
223 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
224 (sregs
.cs
.selector
& 3);
225 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
228 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
229 fix_realmode_dataseg(&sregs
.cs
);
230 fix_realmode_dataseg(&sregs
.ds
);
231 fix_realmode_dataseg(&sregs
.es
);
232 fix_realmode_dataseg(&sregs
.fs
);
233 fix_realmode_dataseg(&sregs
.gs
);
234 fix_realmode_dataseg(&sregs
.ss
);
238 set_seg(&sregs
.tr
, &env
->tr
);
239 set_seg(&sregs
.ldt
, &env
->ldt
);
241 sregs
.idt
.limit
= env
->idt
.limit
;
242 sregs
.idt
.base
= env
->idt
.base
;
243 sregs
.gdt
.limit
= env
->gdt
.limit
;
244 sregs
.gdt
.base
= env
->gdt
.base
;
246 sregs
.cr0
= env
->cr
[0];
247 sregs
.cr2
= env
->cr
[2];
248 sregs
.cr3
= env
->cr
[3];
249 sregs
.cr4
= env
->cr
[4];
251 sregs
.cr8
= cpu_get_apic_tpr(env
);
252 sregs
.apic_base
= cpu_get_apic_base(env
);
254 sregs
.efer
= env
->efer
;
256 kvm_set_sregs(kvm_context
, env
->cpu_index
, &sregs
);
260 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
261 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
262 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
263 if (kvm_has_msr_star
)
264 set_msr_entry(&msrs
[n
++], MSR_STAR
, env
->star
);
265 set_msr_entry(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
267 if (lm_capable_kernel
) {
268 set_msr_entry(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
269 set_msr_entry(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
270 set_msr_entry(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
271 set_msr_entry(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
275 rc
= kvm_set_msrs(kvm_context
, env
->cpu_index
, msrs
, n
);
277 perror("kvm_set_msrs FAILED");
280 void kvm_save_mpstate(CPUState
*env
)
282 #ifdef KVM_CAP_MP_STATE
284 struct kvm_mp_state mp_state
;
286 r
= kvm_get_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
290 env
->mp_state
= mp_state
.mp_state
;
294 void kvm_load_mpstate(CPUState
*env
)
296 #ifdef KVM_CAP_MP_STATE
297 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
300 * -1 indicates that the host did not support GET_MP_STATE ioctl,
303 if (env
->mp_state
!= -1)
304 kvm_set_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
308 void kvm_arch_save_regs(CPUState
*env
)
310 struct kvm_regs regs
;
312 struct kvm_sregs sregs
;
313 struct kvm_msr_entry msrs
[MSR_COUNT
];
317 kvm_get_regs(kvm_context
, env
->cpu_index
, ®s
);
319 env
->regs
[R_EAX
] = regs
.rax
;
320 env
->regs
[R_EBX
] = regs
.rbx
;
321 env
->regs
[R_ECX
] = regs
.rcx
;
322 env
->regs
[R_EDX
] = regs
.rdx
;
323 env
->regs
[R_ESI
] = regs
.rsi
;
324 env
->regs
[R_EDI
] = regs
.rdi
;
325 env
->regs
[R_ESP
] = regs
.rsp
;
326 env
->regs
[R_EBP
] = regs
.rbp
;
328 env
->regs
[8] = regs
.r8
;
329 env
->regs
[9] = regs
.r9
;
330 env
->regs
[10] = regs
.r10
;
331 env
->regs
[11] = regs
.r11
;
332 env
->regs
[12] = regs
.r12
;
333 env
->regs
[13] = regs
.r13
;
334 env
->regs
[14] = regs
.r14
;
335 env
->regs
[15] = regs
.r15
;
338 env
->eflags
= regs
.rflags
;
341 kvm_get_fpu(kvm_context
, env
->cpu_index
, &fpu
);
342 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
345 for (i
= 0; i
< 8; ++i
)
346 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
347 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
348 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
349 env
->mxcsr
= fpu
.mxcsr
;
351 kvm_get_sregs(kvm_context
, env
->cpu_index
, &sregs
);
353 memcpy(env
->kvm_interrupt_bitmap
, sregs
.interrupt_bitmap
, sizeof(env
->kvm_interrupt_bitmap
));
355 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
356 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
357 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
358 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
359 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
360 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
362 get_seg(&env
->tr
, &sregs
.tr
);
363 get_seg(&env
->ldt
, &sregs
.ldt
);
365 env
->idt
.limit
= sregs
.idt
.limit
;
366 env
->idt
.base
= sregs
.idt
.base
;
367 env
->gdt
.limit
= sregs
.gdt
.limit
;
368 env
->gdt
.base
= sregs
.gdt
.base
;
370 env
->cr
[0] = sregs
.cr0
;
371 env
->cr
[2] = sregs
.cr2
;
372 env
->cr
[3] = sregs
.cr3
;
373 env
->cr
[4] = sregs
.cr4
;
375 cpu_set_apic_base(env
, sregs
.apic_base
);
377 env
->efer
= sregs
.efer
;
378 //cpu_set_apic_tpr(env, sregs.cr8);
380 #define HFLAG_COPY_MASK ~( \
381 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
382 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
383 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
384 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
388 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
389 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
390 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
391 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
392 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
393 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
394 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
396 if (env
->efer
& MSR_EFER_LMA
) {
397 hflags
|= HF_LMA_MASK
;
400 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
401 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
403 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
404 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
405 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
406 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
407 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
408 (env
->eflags
& VM_MASK
) ||
409 !(hflags
& HF_CS32_MASK
)) {
410 hflags
|= HF_ADDSEG_MASK
;
412 hflags
|= ((env
->segs
[R_DS
].base
|
413 env
->segs
[R_ES
].base
|
414 env
->segs
[R_SS
].base
) != 0) <<
418 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
419 env
->cc_src
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
420 env
->df
= 1 - (2 * ((env
->eflags
>> 10) & 1));
421 env
->cc_op
= CC_OP_EFLAGS
;
422 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
426 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
427 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
428 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
429 if (kvm_has_msr_star
)
430 msrs
[n
++].index
= MSR_STAR
;
431 msrs
[n
++].index
= MSR_IA32_TSC
;
433 if (lm_capable_kernel
) {
434 msrs
[n
++].index
= MSR_CSTAR
;
435 msrs
[n
++].index
= MSR_KERNELGSBASE
;
436 msrs
[n
++].index
= MSR_FMASK
;
437 msrs
[n
++].index
= MSR_LSTAR
;
440 rc
= kvm_get_msrs(kvm_context
, env
->cpu_index
, msrs
, n
);
442 perror("kvm_get_msrs FAILED");
445 n
= rc
; /* actual number of MSRs */
446 for (i
=0 ; i
<n
; i
++) {
447 if (get_msr_entry(&msrs
[i
], env
))
453 static void host_cpuid(uint32_t function
, uint32_t *eax
, uint32_t *ebx
,
454 uint32_t *ecx
, uint32_t *edx
)
460 : "=a"(vec
[0]), "=b"(vec
[1]),
461 "=c"(vec
[2]), "=d"(vec
[3])
462 : "0"(function
) : "cc");
464 asm volatile("pusha \n\t"
466 "mov %%eax, 0(%1) \n\t"
467 "mov %%ebx, 4(%1) \n\t"
468 "mov %%ecx, 8(%1) \n\t"
469 "mov %%edx, 12(%1) \n\t"
471 : : "a"(function
), "S"(vec
)
486 static void do_cpuid_ent(struct kvm_cpuid_entry
*e
, uint32_t function
,
489 env
->regs
[R_EAX
] = function
;
490 qemu_kvm_cpuid_on_env(env
);
491 e
->function
= function
;
492 e
->eax
= env
->regs
[R_EAX
];
493 e
->ebx
= env
->regs
[R_EBX
];
494 e
->ecx
= env
->regs
[R_ECX
];
495 e
->edx
= env
->regs
[R_EDX
];
496 if (function
== 0x80000001) {
497 uint32_t h_eax
, h_edx
;
499 host_cpuid(function
, &h_eax
, NULL
, NULL
, &h_edx
);
502 if ((h_edx
& 0x20000000) == 0 || !lm_capable_kernel
)
503 e
->edx
&= ~0x20000000u
;
505 if ((h_edx
& 0x00000800) == 0)
506 e
->edx
&= ~0x00000800u
;
508 if ((h_edx
& 0x00100000) == 0)
509 e
->edx
&= ~0x00100000u
;
514 // sysenter isn't supported on compatibility mode on AMD. and syscall
515 // isn't supported in compatibility mode on Intel. so advertise the
516 // actuall cpu, and say goodbye to migration between different vendors
517 // is you use compatibility mode.
521 host_cpuid(0, NULL
, &bcd
[0], &bcd
[1], &bcd
[2]);
526 // "Hypervisor present" bit for Microsoft guests
528 e
->ecx
|= (1u << 31);
530 // 3dnow isn't properly emulated yet
531 if (function
== 0x80000001)
532 e
->edx
&= ~0xc0000000;
535 struct kvm_para_features
{
538 } para_features
[] = {
539 #ifdef KVM_CAP_CLOCKSOURCE
540 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
542 #ifdef KVM_CAP_NOP_IO_DELAY
543 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
545 #ifdef KVM_CAP_PV_MMU
546 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
548 #ifdef KVM_CAP_CR3_CACHE
549 { KVM_CAP_CR3_CACHE
, KVM_FEATURE_CR3_CACHE
},
554 static int get_para_features(kvm_context_t kvm_context
)
558 for (i
= 0; i
< ARRAY_SIZE(para_features
)-1; i
++) {
559 if (kvm_check_extension(kvm_context
, para_features
[i
].cap
))
560 features
|= (1 << para_features
[i
].feature
);
566 int kvm_arch_qemu_init_env(CPUState
*cenv
)
568 struct kvm_cpuid_entry cpuid_ent
[100];
569 #ifdef KVM_CPUID_SIGNATURE
570 struct kvm_cpuid_entry
*pv_ent
;
571 uint32_t signature
[3];
579 #ifdef KVM_CPUID_SIGNATURE
580 /* Paravirtualization CPUIDs */
581 memcpy(signature
, "KVMKVMKVM", 12);
582 pv_ent
= &cpuid_ent
[cpuid_nent
++];
583 memset(pv_ent
, 0, sizeof(*pv_ent
));
584 pv_ent
->function
= KVM_CPUID_SIGNATURE
;
586 pv_ent
->ebx
= signature
[0];
587 pv_ent
->ecx
= signature
[1];
588 pv_ent
->edx
= signature
[2];
590 pv_ent
= &cpuid_ent
[cpuid_nent
++];
591 memset(pv_ent
, 0, sizeof(*pv_ent
));
592 pv_ent
->function
= KVM_CPUID_FEATURES
;
593 pv_ent
->eax
= get_para_features(kvm_context
);
596 copy
.regs
[R_EAX
] = 0;
597 qemu_kvm_cpuid_on_env(©
);
598 limit
= copy
.regs
[R_EAX
];
600 for (i
= 0; i
<= limit
; ++i
)
601 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, ©
);
603 copy
.regs
[R_EAX
] = 0x80000000;
604 qemu_kvm_cpuid_on_env(©
);
605 limit
= copy
.regs
[R_EAX
];
607 for (i
= 0x80000000; i
<= limit
; ++i
)
608 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, ©
);
610 kvm_setup_cpuid(kvm_context
, cenv
->cpu_index
, cpuid_nent
, cpuid_ent
);
614 int kvm_arch_halt(void *opaque
, int vcpu
)
616 CPUState
*env
= cpu_single_env
;
618 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
619 (env
->eflags
& IF_MASK
))) {
620 env
->hflags
|= HF_HALTED_MASK
;
621 env
->exception_index
= EXCP_HLT
;
626 void kvm_arch_pre_kvm_run(void *opaque
, int vcpu
)
628 CPUState
*env
= cpu_single_env
;
630 if (!kvm_irqchip_in_kernel(kvm_context
))
631 kvm_set_cr8(kvm_context
, vcpu
, cpu_get_apic_tpr(env
));
634 void kvm_arch_post_kvm_run(void *opaque
, int vcpu
)
636 CPUState
*env
= qemu_kvm_cpu_env(vcpu
);
637 cpu_single_env
= env
;
639 env
->eflags
= kvm_get_interrupt_flag(kvm_context
, vcpu
)
640 ? env
->eflags
| IF_MASK
: env
->eflags
& ~IF_MASK
;
641 env
->ready_for_interrupt_injection
642 = kvm_is_ready_for_interrupt_injection(kvm_context
, vcpu
);
644 cpu_set_apic_tpr(env
, kvm_get_cr8(kvm_context
, vcpu
));
645 cpu_set_apic_base(env
, kvm_get_apic_base(kvm_context
, vcpu
));
648 int kvm_arch_has_work(CPUState
*env
)
650 if ((env
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_EXIT
)) &&
651 (env
->eflags
& IF_MASK
))
656 int kvm_arch_try_push_interrupts(void *opaque
)
658 CPUState
*env
= cpu_single_env
;
661 if (env
->ready_for_interrupt_injection
&&
662 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
663 (env
->eflags
& IF_MASK
)) {
664 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
665 irq
= cpu_get_pic_interrupt(env
);
667 r
= kvm_inject_irq(kvm_context
, env
->cpu_index
, irq
);
669 printf("cpu %d fail inject %x\n", env
->cpu_index
, irq
);
673 return (env
->interrupt_request
& CPU_INTERRUPT_HARD
) != 0;
676 void kvm_arch_update_regs_for_sipi(CPUState
*env
)
678 SegmentCache cs
= env
->segs
[R_CS
];
680 kvm_arch_save_regs(env
);
681 env
->segs
[R_CS
] = cs
;
683 kvm_arch_load_regs(env
);
686 int handle_tpr_access(void *opaque
, int vcpu
,
687 uint64_t rip
, int is_write
)
689 kvm_tpr_access_report(cpu_single_env
, rip
, is_write
);