hw/i8254.c

   1 /*
   2  * QEMU 8253/8254 interval timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "qemu-timer.h"
  28 #include "i8254.h"
  29
  30 //#define DEBUG_PIT
  31
  32 static PITState pit_state;
  33
  34 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  35
  36 static int pit_get_count(PITChannelState *s)
  37 {
  38     uint64_t d;
  39     int counter;
  40
  41     d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
  42     switch(s->mode) {
  43     case 0:
  44     case 1:
  45     case 4:
  46     case 5:
  47         counter = (s->count - d) & 0xffff;
  48         break;
  49     case 3:
  50         /* XXX: may be incorrect for odd counts */
  51         counter = s->count - ((2 * d) % s->count);
  52         break;
  53     default:
  54         counter = s->count - (d % s->count);
  55         break;
  56     }
  57     return counter;
  58 }
  59
  60 /* get pit output bit */
  61 static int pit_get_out1(PITChannelState *s, int64_t current_time)
  62 {
  63     uint64_t d;
  64     int out;
  65
  66     d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
  67     switch(s->mode) {
  68     default:
  69     case 0:
  70         out = (d >= s->count);
  71         break;
  72     case 1:
  73         out = (d < s->count);
  74         break;
  75     case 2:
  76         if ((d % s->count) == 0 && d != 0)
  77             out = 1;
  78         else
  79             out = 0;
  80         break;
  81     case 3:
  82         out = (d % s->count) < ((s->count + 1) >> 1);
  83         break;
  84     case 4:
  85     case 5:
  86         out = (d == s->count);
  87         break;
  88     }
  89     return out;
  90 }
  91
  92 int pit_get_out(PITState *pit, int channel, int64_t current_time)
  93 {
  94     PITChannelState *s = &pit->channels[channel];
  95     return pit_get_out1(s, current_time);
  96 }
  97
  98 /* return -1 if no transition will occur.  */
  99 static int64_t pit_get_next_transition_time(PITChannelState *s,
 100                                             int64_t current_time)
 101 {
 102     uint64_t d, next_time, base;
 103     int period2;
 104
 105     d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
 106     switch(s->mode) {
 107     default:
 108     case 0:
 109     case 1:
 110         if (d < s->count)
 111             next_time = s->count;
 112         else
 113             return -1;
 114         break;
 115     case 2:
 116         base = (d / s->count) * s->count;
 117         if ((d - base) == 0 && d != 0)
 118             next_time = base + s->count;
 119         else
 120             next_time = base + s->count + 1;
 121         break;
 122     case 3:
 123         base = (d / s->count) * s->count;
 124         period2 = ((s->count + 1) >> 1);
 125         if ((d - base) < period2)
 126             next_time = base + period2;
 127         else
 128             next_time = base + s->count;
 129         break;
 130     case 4:
 131     case 5:
 132         if (d < s->count)
 133             next_time = s->count;
 134         else if (d == s->count)
 135             next_time = s->count + 1;
 136         else
 137             return -1;
 138         break;
 139     }
 140     /* convert to timer units */
 141     next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
 142     /* fix potential rounding problems */
 143     /* XXX: better solution: use a clock at PIT_FREQ Hz */
 144     if (next_time <= current_time)
 145         next_time = current_time + 1;
 146     return next_time;
 147 }
 148
 149 /* val must be 0 or 1 */
 150 void pit_set_gate(PITState *pit, int channel, int val)
 151 {
 152     PITChannelState *s = &pit->channels[channel];
 153
 154     switch(s->mode) {
 155     default:
 156     case 0:
 157     case 4:
 158         /* XXX: just disable/enable counting */
 159         break;
 160     case 1:
 161     case 5:
 162         if (s->gate < val) {
 163             /* restart counting on rising edge */
 164             s->count_load_time = qemu_get_clock(vm_clock);
 165             pit_irq_timer_update(s, s->count_load_time);
 166         }
 167         break;
 168     case 2:
 169     case 3:
 170         if (s->gate < val) {
 171             /* restart counting on rising edge */
 172             s->count_load_time = qemu_get_clock(vm_clock);
 173             pit_irq_timer_update(s, s->count_load_time);
 174         }
 175         /* XXX: disable/enable counting */
 176         break;
 177     }
 178     s->gate = val;
 179 }
 180
 181 int pit_get_gate(PITState *pit, int channel)
 182 {
 183     PITChannelState *s = &pit->channels[channel];
 184     return s->gate;
 185 }
 186
 187 int pit_get_initial_count(PITState *pit, int channel)
 188 {
 189     PITChannelState *s = &pit->channels[channel];
 190     return s->count;
 191 }
 192
 193 int pit_get_mode(PITState *pit, int channel)
 194 {
 195     PITChannelState *s = &pit->channels[channel];
 196     return s->mode;
 197 }
 198
 199 static inline void pit_load_count(PITChannelState *s, int val)
 200 {
 201     if (val == 0)
 202         val = 0x10000;
 203     s->count_load_time = qemu_get_clock(vm_clock);
 204     s->count = val;
 205     pit_irq_timer_update(s, s->count_load_time);
 206 }
 207
 208 /* if already latched, do not latch again */
 209 static void pit_latch_count(PITChannelState *s)
 210 {
 211     if (!s->count_latched) {
 212         s->latched_count = pit_get_count(s);
 213         s->count_latched = s->rw_mode;
 214     }
 215 }
 216
 217 static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 218 {
 219     PITState *pit = opaque;
 220     int channel, access;
 221     PITChannelState *s;
 222
 223     addr &= 3;
 224     if (addr == 3) {
 225         channel = val >> 6;
 226         if (channel == 3) {
 227             /* read back command */
 228             for(channel = 0; channel < 3; channel++) {
 229                 s = &pit->channels[channel];
 230                 if (val & (2 << channel)) {
 231                     if (!(val & 0x20)) {
 232                         pit_latch_count(s);
 233                     }
 234                     if (!(val & 0x10) && !s->status_latched) {
 235                         /* status latch */
 236                         /* XXX: add BCD and null count */
 237                         s->status =  (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
 238                             (s->rw_mode << 4) |
 239                             (s->mode << 1) |
 240                             s->bcd;
 241                         s->status_latched = 1;
 242                     }
 243                 }
 244             }
 245         } else {
 246             s = &pit->channels[channel];
 247             access = (val >> 4) & 3;
 248             if (access == 0) {
 249                 pit_latch_count(s);
 250             } else {
 251                 s->rw_mode = access;
 252                 s->read_state = access;
 253                 s->write_state = access;
 254
 255                 s->mode = (val >> 1) & 7;
 256                 s->bcd = val & 1;
 257                 /* XXX: update irq timer ? */
 258             }
 259         }
 260     } else {
 261         s = &pit->channels[addr];
 262         switch(s->write_state) {
 263         default:
 264         case RW_STATE_LSB:
 265             pit_load_count(s, val);
 266             break;
 267         case RW_STATE_MSB:
 268             pit_load_count(s, val << 8);
 269             break;
 270         case RW_STATE_WORD0:
 271             s->write_latch = val;
 272             s->write_state = RW_STATE_WORD1;
 273             break;
 274         case RW_STATE_WORD1:
 275             pit_load_count(s, s->write_latch | (val << 8));
 276             s->write_state = RW_STATE_WORD0;
 277             break;
 278         }
 279     }
 280 }
 281
 282 static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
 283 {
 284     PITState *pit = opaque;
 285     int ret, count;
 286     PITChannelState *s;
 287
 288     addr &= 3;
 289     s = &pit->channels[addr];
 290     if (s->status_latched) {
 291         s->status_latched = 0;
 292         ret = s->status;
 293     } else if (s->count_latched) {
 294         switch(s->count_latched) {
 295         default:
 296         case RW_STATE_LSB:
 297             ret = s->latched_count & 0xff;
 298             s->count_latched = 0;
 299             break;
 300         case RW_STATE_MSB:
 301             ret = s->latched_count >> 8;
 302             s->count_latched = 0;
 303             break;
 304         case RW_STATE_WORD0:
 305             ret = s->latched_count & 0xff;
 306             s->count_latched = RW_STATE_MSB;
 307             break;
 308         }
 309     } else {
 310         switch(s->read_state) {
 311         default:
 312         case RW_STATE_LSB:
 313             count = pit_get_count(s);
 314             ret = count & 0xff;
 315             break;
 316         case RW_STATE_MSB:
 317             count = pit_get_count(s);
 318             ret = (count >> 8) & 0xff;
 319             break;
 320         case RW_STATE_WORD0:
 321             count = pit_get_count(s);
 322             ret = count & 0xff;
 323             s->read_state = RW_STATE_WORD1;
 324             break;
 325         case RW_STATE_WORD1:
 326             count = pit_get_count(s);
 327             ret = (count >> 8) & 0xff;
 328             s->read_state = RW_STATE_WORD0;
 329             break;
 330         }
 331     }
 332     return ret;
 333 }
 334
 335 /* global counters for time-drift fix */
 336 int64_t timer_acks=0, timer_interrupts=0, timer_ints_to_push=0;
 337
 338 extern int time_drift_fix;
 339
 340 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
 341 {
 342     int64_t expire_time;
 343     int irq_level;
 344
 345     if (!s->irq_timer)
 346         return;
 347     expire_time = pit_get_next_transition_time(s, current_time);
 348     irq_level = pit_get_out1(s, current_time);
 349     qemu_set_irq(s->irq, irq_level);
 350     if (time_drift_fix && irq_level==1) {
 351         /* FIXME: fine tune timer_max_fix (max fix per tick).
 352          *        Should it be 1 (double time), 2 , 4, 10 ?
 353          *        Currently setting it to 5% of PIT-ticks-per-second (per PIT-tick)
 354          */
 355         const long pit_ticks_per_sec = (s->count>0) ? (PIT_FREQ/s->count) : 0;
 356         const long timer_max_fix = pit_ticks_per_sec/20;
 357         const long delta = timer_interrupts - timer_acks;
 358         const long max_delta = pit_ticks_per_sec * 60; /* one minute */
 359         if ((delta >  max_delta) && (pit_ticks_per_sec > 0)) {
 360             printf("time drift is too long, %ld seconds were lost\n", delta/pit_ticks_per_sec);
 361             timer_acks = timer_interrupts;
 362             timer_ints_to_push = 0;
 363         } else if (delta > 0) {
 364             timer_ints_to_push = MIN(delta, timer_max_fix);
 365         }
 366         timer_interrupts++;
 367     }
 368 #ifdef DEBUG_PIT
 369     printf("irq_level=%d next_delay=%f\n",
 370            irq_level,
 371            (double)(expire_time - current_time) / ticks_per_sec);
 372 #endif
 373     s->next_transition_time = expire_time;
 374     if (expire_time != -1)
 375         qemu_mod_timer(s->irq_timer, expire_time);
 376     else
 377         qemu_del_timer(s->irq_timer);
 378 }
 379
 380 static void pit_irq_timer(void *opaque)
 381 {
 382     PITChannelState *s = opaque;
 383
 384     pit_irq_timer_update(s, s->next_transition_time);
 385 }
 386
 387 void pit_save(QEMUFile *f, void *opaque)
 388 {
 389     PITState *pit = opaque;
 390     PITChannelState *s;
 391     int i;
 392
 393     for(i = 0; i < 3; i++) {
 394         s = &pit->channels[i];
 395         qemu_put_be32(f, s->count);
 396         qemu_put_be16s(f, &s->latched_count);
 397         qemu_put_8s(f, &s->count_latched);
 398         qemu_put_8s(f, &s->status_latched);
 399         qemu_put_8s(f, &s->status);
 400         qemu_put_8s(f, &s->read_state);
 401         qemu_put_8s(f, &s->write_state);
 402         qemu_put_8s(f, &s->write_latch);
 403         qemu_put_8s(f, &s->rw_mode);
 404         qemu_put_8s(f, &s->mode);
 405         qemu_put_8s(f, &s->bcd);
 406         qemu_put_8s(f, &s->gate);
 407         qemu_put_be64(f, s->count_load_time);
 408         if (s->irq_timer) {
 409             qemu_put_be64(f, s->next_transition_time);
 410             qemu_put_timer(f, s->irq_timer);
 411         }
 412     }
 413 }
 414
 415 int pit_load(QEMUFile *f, void *opaque, int version_id)
 416 {
 417     PITState *pit = opaque;
 418     PITChannelState *s;
 419     int i;
 420
 421     if (version_id != 1)
 422         return -EINVAL;
 423
 424     for(i = 0; i < 3; i++) {
 425         s = &pit->channels[i];
 426         s->count=qemu_get_be32(f);
 427         qemu_get_be16s(f, &s->latched_count);
 428         qemu_get_8s(f, &s->count_latched);
 429         qemu_get_8s(f, &s->status_latched);
 430         qemu_get_8s(f, &s->status);
 431         qemu_get_8s(f, &s->read_state);
 432         qemu_get_8s(f, &s->write_state);
 433         qemu_get_8s(f, &s->write_latch);
 434         qemu_get_8s(f, &s->rw_mode);
 435         qemu_get_8s(f, &s->mode);
 436         qemu_get_8s(f, &s->bcd);
 437         qemu_get_8s(f, &s->gate);
 438         s->count_load_time=qemu_get_be64(f);
 439         if (s->irq_timer) {
 440             s->next_transition_time=qemu_get_be64(f);
 441             qemu_get_timer(f, s->irq_timer);
 442         }
 443     }
 444
 445     return 0;
 446 }
 447
 448 void pit_reset(void *opaque)
 449 {
 450     PITState *pit = opaque;
 451     PITChannelState *s;
 452     int i;
 453
 454     for(i = 0;i < 3; i++) {
 455         s = &pit->channels[i];
 456         s->mode = 3;
 457         s->gate = (i != 2);
 458         pit_load_count(s, 0);
 459     }
 460 }
 461
 462 /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
 463 void hpet_pit_disable(void) {
 464     PITChannelState *s;
 465     s = &pit_state.channels[0];
 466     if (s->irq_timer)
 467         qemu_del_timer(s->irq_timer);
 468 }
 469
 470 /* When HPET is reset or leaving legacy mode, it must reenable i8254
 471  * timer 0
 472  */
 473
 474 void hpet_pit_enable(void)
 475 {
 476     PITState *pit = &pit_state;
 477     PITChannelState *s;
 478     s = &pit->channels[0];
 479     s->mode = 3;
 480     s->gate = 1;
 481     pit_load_count(s, 0);
 482 }
 483
 484 PITState *pit_init(int base, qemu_irq irq)
 485 {
 486     PITState *pit = &pit_state;
 487     PITChannelState *s;
 488
 489     s = &pit->channels[0];
 490     /* the timer 0 is connected to an IRQ */
 491     s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
 492     s->irq = irq;
 493
 494     register_savevm(PIT_SAVEVM_NAME, base, PIT_SAVEVM_VERSION,
 495                     pit_save, pit_load, pit);
 496
 497     qemu_register_reset(pit_reset, pit);
 498     register_ioport_write(base, 4, 1, pit_ioport_write, pit);
 499     register_ioport_read(base, 3, 1, pit_ioport_read, pit);
 500
 501     pit_reset(pit);
 502
 503     return pit;
 504 }