hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28 //#define DEBUG_IOAPIC
  29
  30 /* APIC Local Vector Table */
  31 #define APIC_LVT_TIMER   0
  32 #define APIC_LVT_THERMAL 1
  33 #define APIC_LVT_PERFORM 2
  34 #define APIC_LVT_LINT0   3
  35 #define APIC_LVT_LINT1   4
  36 #define APIC_LVT_ERROR   5
  37 #define APIC_LVT_NB      6
  38
  39 /* APIC delivery modes */
  40 #define APIC_DM_FIXED   0
  41 #define APIC_DM_LOWPRI  1
  42 #define APIC_DM_SMI     2
  43 #define APIC_DM_NMI     4
  44 #define APIC_DM_INIT    5
  45 #define APIC_DM_SIPI    6
  46 #define APIC_DM_EXTINT  7
  47
  48 /* APIC destination mode */
  49 #define APIC_DESTMODE_FLAT      0xf
  50 #define APIC_DESTMODE_CLUSTER   1
  51
  52 #define APIC_TRIGGER_EDGE  0
  53 #define APIC_TRIGGER_LEVEL 1
  54
  55 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  56 #define APIC_LVT_MASKED                 (1<<16)
  57 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  58 #define APIC_LVT_REMOTE_IRR             (1<<14)
  59 #define APIC_INPUT_POLARITY             (1<<13)
  60 #define APIC_SEND_PENDING               (1<<12)
  61
  62 /* FIXME: it's now hard coded to be equal with KVM_IOAPIC_NUM_PINS */
  63 #define IOAPIC_NUM_PINS                 0x18
  64 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  65
  66 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  67
  68 #define APIC_SV_ENABLE (1 << 8)
  69
  70 #define MAX_APICS 255
  71 #define MAX_APIC_WORDS 8
  72
  73 typedef struct APICState {
  74     CPUState *cpu_env;
  75     uint32_t apicbase;
  76     uint8_t id;
  77     uint8_t arb_id;
  78     uint8_t tpr;
  79     uint32_t spurious_vec;
  80     uint8_t log_dest;
  81     uint8_t dest_mode;
  82     uint32_t isr[8];  /* in service register */
  83     uint32_t tmr[8];  /* trigger mode register */
  84     uint32_t irr[8]; /* interrupt request register */
  85     uint32_t lvt[APIC_LVT_NB];
  86     uint32_t esr; /* error register */
  87     uint32_t icr[2];
  88
  89     uint32_t divide_conf;
  90     int count_shift;
  91     uint32_t initial_count;
  92     int64_t initial_count_load_time, next_time;
  93     QEMUTimer *timer;
  94 } APICState;
  95
  96 struct IOAPICState {
  97     uint8_t id;
  98     uint8_t ioregsel;
  99     uint64_t base_address;
 100
 101     uint32_t irr;
 102     uint64_t ioredtbl[IOAPIC_NUM_PINS];
 103 };
 104
 105 static int apic_io_memory;
 106 static APICState *local_apics[MAX_APICS + 1];
 107 static int last_apic_id = 0;
 108 static int apic_irq_delivered;
 109
 110
 111 static void apic_init_ipi(APICState *s);
 112 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 113 static void apic_update_irq(APICState *s);
 114
 115 /* Find first bit starting from msb */
 116 static int fls_bit(uint32_t value)
 117 {
 118     return 31 - clz32(value);
 119 }
 120
 121 /* Find first bit starting from lsb */
 122 static int ffs_bit(uint32_t value)
 123 {
 124     return ctz32(value);
 125 }
 126
 127 static inline void set_bit(uint32_t *tab, int index)
 128 {
 129     int i, mask;
 130     i = index >> 5;
 131     mask = 1 << (index & 0x1f);
 132     tab[i] |= mask;
 133 }
 134
 135 static inline void reset_bit(uint32_t *tab, int index)
 136 {
 137     int i, mask;
 138     i = index >> 5;
 139     mask = 1 << (index & 0x1f);
 140     tab[i] &= ~mask;
 141 }
 142
 143 static inline int get_bit(uint32_t *tab, int index)
 144 {
 145     int i, mask;
 146     i = index >> 5;
 147     mask = 1 << (index & 0x1f);
 148     return !!(tab[i] & mask);
 149 }
 150
 151 static void apic_local_deliver(CPUState *env, int vector)
 152 {
 153     APICState *s = env->apic_state;
 154     uint32_t lvt = s->lvt[vector];
 155     int trigger_mode;
 156
 157     if (lvt & APIC_LVT_MASKED)
 158         return;
 159
 160     switch ((lvt >> 8) & 7) {
 161     case APIC_DM_SMI:
 162         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 163         break;
 164
 165     case APIC_DM_NMI:
 166         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 167         break;
 168
 169     case APIC_DM_EXTINT:
 170         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 171         break;
 172
 173     case APIC_DM_FIXED:
 174         trigger_mode = APIC_TRIGGER_EDGE;
 175         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 176             (lvt & APIC_LVT_LEVEL_TRIGGER))
 177             trigger_mode = APIC_TRIGGER_LEVEL;
 178         apic_set_irq(s, lvt & 0xff, trigger_mode);
 179     }
 180 }
 181
 182 void apic_deliver_pic_intr(CPUState *env, int level)
 183 {
 184     if (level)
 185         apic_local_deliver(env, APIC_LVT_LINT0);
 186     else {
 187         APICState *s = env->apic_state;
 188         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 189
 190         switch ((lvt >> 8) & 7) {
 191         case APIC_DM_FIXED:
 192             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 193                 break;
 194             reset_bit(s->irr, lvt & 0xff);
 195             /* fall through */
 196         case APIC_DM_EXTINT:
 197             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 198             break;
 199         }
 200     }
 201 }
 202
 203 #define foreach_apic(apic, deliver_bitmask, code) \
 204 {\
 205     int __i, __j, __mask;\
 206     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 207         __mask = deliver_bitmask[__i];\
 208         if (__mask) {\
 209             for(__j = 0; __j < 32; __j++) {\
 210                 if (__mask & (1 << __j)) {\
 211                     apic = local_apics[__i * 32 + __j];\
 212                     if (apic) {\
 213                         code;\
 214                     }\
 215                 }\
 216             }\
 217         }\
 218     }\
 219 }
 220
 221 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 222                              uint8_t delivery_mode,
 223                              uint8_t vector_num, uint8_t polarity,
 224                              uint8_t trigger_mode)
 225 {
 226     APICState *apic_iter;
 227
 228     switch (delivery_mode) {
 229         case APIC_DM_LOWPRI:
 230             /* XXX: search for focus processor, arbitration */
 231             {
 232                 int i, d;
 233                 d = -1;
 234                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 235                     if (deliver_bitmask[i]) {
 236                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 237                         break;
 238                     }
 239                 }
 240                 if (d >= 0) {
 241                     apic_iter = local_apics[d];
 242                     if (apic_iter) {
 243                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 244                     }
 245                 }
 246             }
 247             return;
 248
 249         case APIC_DM_FIXED:
 250             break;
 251
 252         case APIC_DM_SMI:
 253             foreach_apic(apic_iter, deliver_bitmask,
 254                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 255             return;
 256
 257         case APIC_DM_NMI:
 258             foreach_apic(apic_iter, deliver_bitmask,
 259                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 260             return;
 261
 262         case APIC_DM_INIT:
 263             /* normal INIT IPI sent to processors */
 264             foreach_apic(apic_iter, deliver_bitmask,
 265                          apic_init_ipi(apic_iter) );
 266             return;
 267
 268         case APIC_DM_EXTINT:
 269             /* handled in I/O APIC code */
 270             break;
 271
 272         default:
 273             return;
 274     }
 275
 276     foreach_apic(apic_iter, deliver_bitmask,
 277                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 278 }
 279
 280 void cpu_set_apic_base(CPUState *env, uint64_t val)
 281 {
 282     APICState *s = env->apic_state;
 283 #ifdef DEBUG_APIC
 284     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 285 #endif
 286     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 287         s->apicbase = val;
 288     else
 289         s->apicbase = (val & 0xfffff000) |
 290             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 291     /* if disabled, cannot be enabled again */
 292     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 293         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 294         env->cpuid_features &= ~CPUID_APIC;
 295         s->spurious_vec &= ~APIC_SV_ENABLE;
 296     }
 297 }
 298
 299 uint64_t cpu_get_apic_base(CPUState *env)
 300 {
 301     APICState *s = env->apic_state;
 302 #ifdef DEBUG_APIC
 303     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 304 #endif
 305     return s->apicbase;
 306 }
 307
 308 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 309 {
 310     APICState *s = env->apic_state;
 311     s->tpr = (val & 0x0f) << 4;
 312     apic_update_irq(s);
 313 }
 314
 315 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 316 {
 317     APICState *s = env->apic_state;
 318     return s->tpr >> 4;
 319 }
 320
 321 /* return -1 if no bit is set */
 322 static int get_highest_priority_int(uint32_t *tab)
 323 {
 324     int i;
 325     for(i = 7; i >= 0; i--) {
 326         if (tab[i] != 0) {
 327             return i * 32 + fls_bit(tab[i]);
 328         }
 329     }
 330     return -1;
 331 }
 332
 333 static int apic_get_ppr(APICState *s)
 334 {
 335     int tpr, isrv, ppr;
 336
 337     tpr = (s->tpr >> 4);
 338     isrv = get_highest_priority_int(s->isr);
 339     if (isrv < 0)
 340         isrv = 0;
 341     isrv >>= 4;
 342     if (tpr >= isrv)
 343         ppr = s->tpr;
 344     else
 345         ppr = isrv << 4;
 346     return ppr;
 347 }
 348
 349 static int apic_get_arb_pri(APICState *s)
 350 {
 351     /* XXX: arbitration */
 352     return 0;
 353 }
 354
 355 /* signal the CPU if an irq is pending */
 356 static void apic_update_irq(APICState *s)
 357 {
 358     int irrv, ppr;
 359     if (!(s->spurious_vec & APIC_SV_ENABLE))
 360         return;
 361     irrv = get_highest_priority_int(s->irr);
 362     if (irrv < 0)
 363         return;
 364     ppr = apic_get_ppr(s);
 365     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 366         return;
 367     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 368 }
 369
 370 void apic_reset_irq_delivered(void)
 371 {
 372     apic_irq_delivered = 0;
 373 }
 374
 375 int apic_get_irq_delivered(void)
 376 {
 377     return apic_irq_delivered;
 378 }
 379
 380 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 381 {
 382     apic_irq_delivered += !get_bit(s->irr, vector_num);
 383
 384     set_bit(s->irr, vector_num);
 385     if (trigger_mode)
 386         set_bit(s->tmr, vector_num);
 387     else
 388         reset_bit(s->tmr, vector_num);
 389     apic_update_irq(s);
 390 }
 391
 392 static void apic_eoi(APICState *s)
 393 {
 394     int isrv;
 395     isrv = get_highest_priority_int(s->isr);
 396     if (isrv < 0)
 397         return;
 398     reset_bit(s->isr, isrv);
 399     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 400             set the remote IRR bit for level triggered interrupts. */
 401     apic_update_irq(s);
 402 }
 403
 404 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 405                                       uint8_t dest, uint8_t dest_mode)
 406 {
 407     APICState *apic_iter;
 408     int i;
 409
 410     if (dest_mode == 0) {
 411         if (dest == 0xff) {
 412             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 413         } else {
 414             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 415             set_bit(deliver_bitmask, dest);
 416         }
 417     } else {
 418         /* XXX: cluster mode */
 419         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 420         for(i = 0; i < MAX_APICS; i++) {
 421             apic_iter = local_apics[i];
 422             if (apic_iter) {
 423                 if (apic_iter->dest_mode == 0xf) {
 424                     if (dest & apic_iter->log_dest)
 425                         set_bit(deliver_bitmask, i);
 426                 } else if (apic_iter->dest_mode == 0x0) {
 427                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 428                         (dest & apic_iter->log_dest & 0x0f)) {
 429                         set_bit(deliver_bitmask, i);
 430                     }
 431                 }
 432             }
 433         }
 434     }
 435 }
 436
 437
 438 static void apic_init_ipi(APICState *s)
 439 {
 440     int i;
 441
 442     s->tpr = 0;
 443     s->spurious_vec = 0xff;
 444     s->log_dest = 0;
 445     s->dest_mode = 0xf;
 446     memset(s->isr, 0, sizeof(s->isr));
 447     memset(s->tmr, 0, sizeof(s->tmr));
 448     memset(s->irr, 0, sizeof(s->irr));
 449     for(i = 0; i < APIC_LVT_NB; i++)
 450         s->lvt[i] = 1 << 16; /* mask LVT */
 451     s->esr = 0;
 452     memset(s->icr, 0, sizeof(s->icr));
 453     s->divide_conf = 0;
 454     s->count_shift = 0;
 455     s->initial_count = 0;
 456     s->initial_count_load_time = 0;
 457     s->next_time = 0;
 458
 459     cpu_reset(s->cpu_env);
 460
 461     if (!(s->apicbase & MSR_IA32_APICBASE_BSP) &&
 462         (!kvm_enabled() || !qemu_kvm_irqchip_in_kernel()))
 463         s->cpu_env->halted = 1;
 464
 465     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 466         if (s->cpu_env)
 467             kvm_apic_init(s->cpu_env);
 468 }
 469
 470 /* send a SIPI message to the CPU to start it */
 471 static void apic_startup(APICState *s, int vector_num)
 472 {
 473     CPUState *env = s->cpu_env;
 474     if (!env->halted)
 475         return;
 476     env->eip = 0;
 477     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 478                            0xffff, 0);
 479     env->halted = 0;
 480     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 481         kvm_update_after_sipi(env);
 482 }
 483
 484 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 485                          uint8_t delivery_mode, uint8_t vector_num,
 486                          uint8_t polarity, uint8_t trigger_mode)
 487 {
 488     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 489     int dest_shorthand = (s->icr[0] >> 18) & 3;
 490     APICState *apic_iter;
 491
 492     switch (dest_shorthand) {
 493     case 0:
 494         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 495         break;
 496     case 1:
 497         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 498         set_bit(deliver_bitmask, s->id);
 499         break;
 500     case 2:
 501         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 502         break;
 503     case 3:
 504         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 505         reset_bit(deliver_bitmask, s->id);
 506         break;
 507     }
 508
 509     switch (delivery_mode) {
 510         case APIC_DM_INIT:
 511             {
 512                 int trig_mode = (s->icr[0] >> 15) & 1;
 513                 int level = (s->icr[0] >> 14) & 1;
 514                 if (level == 0 && trig_mode == 1) {
 515                     foreach_apic(apic_iter, deliver_bitmask,
 516                                  apic_iter->arb_id = apic_iter->id );
 517                     return;
 518                 }
 519             }
 520             break;
 521
 522         case APIC_DM_SIPI:
 523             foreach_apic(apic_iter, deliver_bitmask,
 524                          apic_startup(apic_iter, vector_num) );
 525             return;
 526     }
 527
 528     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 529                      trigger_mode);
 530 }
 531
 532 int apic_get_interrupt(CPUState *env)
 533 {
 534     APICState *s = env->apic_state;
 535     int intno;
 536
 537     /* if the APIC is installed or enabled, we let the 8259 handle the
 538        IRQs */
 539     if (!s)
 540         return -1;
 541     if (!(s->spurious_vec & APIC_SV_ENABLE))
 542         return -1;
 543
 544     /* XXX: spurious IRQ handling */
 545     intno = get_highest_priority_int(s->irr);
 546     if (intno < 0)
 547         return -1;
 548     if (s->tpr && intno <= s->tpr)
 549         return s->spurious_vec & 0xff;
 550     reset_bit(s->irr, intno);
 551     set_bit(s->isr, intno);
 552     apic_update_irq(s);
 553     return intno;
 554 }
 555
 556 int apic_accept_pic_intr(CPUState *env)
 557 {
 558     APICState *s = env->apic_state;
 559     uint32_t lvt0;
 560
 561     if (!s)
 562         return -1;
 563
 564     lvt0 = s->lvt[APIC_LVT_LINT0];
 565
 566     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 567         (lvt0 & APIC_LVT_MASKED) == 0)
 568         return 1;
 569
 570     return 0;
 571 }
 572
 573 static uint32_t apic_get_current_count(APICState *s)
 574 {
 575     int64_t d;
 576     uint32_t val;
 577     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 578         s->count_shift;
 579     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 580         /* periodic */
 581         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 582     } else {
 583         if (d >= s->initial_count)
 584             val = 0;
 585         else
 586             val = s->initial_count - d;
 587     }
 588     return val;
 589 }
 590
 591 static void apic_timer_update(APICState *s, int64_t current_time)
 592 {
 593     int64_t next_time, d;
 594
 595     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 596         d = (current_time - s->initial_count_load_time) >>
 597             s->count_shift;
 598         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 599             if (!s->initial_count)
 600                 goto no_timer;
 601             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 602         } else {
 603             if (d >= s->initial_count)
 604                 goto no_timer;
 605             d = (uint64_t)s->initial_count + 1;
 606         }
 607         next_time = s->initial_count_load_time + (d << s->count_shift);
 608         qemu_mod_timer(s->timer, next_time);
 609         s->next_time = next_time;
 610     } else {
 611     no_timer:
 612         qemu_del_timer(s->timer);
 613     }
 614 }
 615
 616 static void apic_timer(void *opaque)
 617 {
 618     APICState *s = opaque;
 619
 620     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 621     apic_timer_update(s, s->next_time);
 622 }
 623
 624 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 625 {
 626     return 0;
 627 }
 628
 629 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 630 {
 631     return 0;
 632 }
 633
 634 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 635 {
 636 }
 637
 638 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 639 {
 640 }
 641
 642 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 643 {
 644     CPUState *env;
 645     APICState *s;
 646     uint32_t val;
 647     int index;
 648
 649     env = cpu_single_env;
 650     if (!env)
 651         return 0;
 652     s = env->apic_state;
 653
 654     index = (addr >> 4) & 0xff;
 655     switch(index) {
 656     case 0x02: /* id */
 657         val = s->id << 24;
 658         break;
 659     case 0x03: /* version */
 660         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 661         break;
 662     case 0x08:
 663         val = s->tpr;
 664         break;
 665     case 0x09:
 666         val = apic_get_arb_pri(s);
 667         break;
 668     case 0x0a:
 669         /* ppr */
 670         val = apic_get_ppr(s);
 671         break;
 672     case 0x0b:
 673         val = 0;
 674         break;
 675     case 0x0d:
 676         val = s->log_dest << 24;
 677         break;
 678     case 0x0e:
 679         val = s->dest_mode << 28;
 680         break;
 681     case 0x0f:
 682         val = s->spurious_vec;
 683         break;
 684     case 0x10 ... 0x17:
 685         val = s->isr[index & 7];
 686         break;
 687     case 0x18 ... 0x1f:
 688         val = s->tmr[index & 7];
 689         break;
 690     case 0x20 ... 0x27:
 691         val = s->irr[index & 7];
 692         break;
 693     case 0x28:
 694         val = s->esr;
 695         break;
 696     case 0x30:
 697     case 0x31:
 698         val = s->icr[index & 1];
 699         break;
 700     case 0x32 ... 0x37:
 701         val = s->lvt[index - 0x32];
 702         break;
 703     case 0x38:
 704         val = s->initial_count;
 705         break;
 706     case 0x39:
 707         val = apic_get_current_count(s);
 708         break;
 709     case 0x3e:
 710         val = s->divide_conf;
 711         break;
 712     default:
 713         s->esr |= ESR_ILLEGAL_ADDRESS;
 714         val = 0;
 715         break;
 716     }
 717 #ifdef DEBUG_APIC
 718     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 719 #endif
 720     return val;
 721 }
 722
 723 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 724 {
 725     CPUState *env;
 726     APICState *s;
 727     int index;
 728
 729     env = cpu_single_env;
 730     if (!env)
 731         return;
 732     s = env->apic_state;
 733
 734 #ifdef DEBUG_APIC
 735     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 736 #endif
 737
 738     index = (addr >> 4) & 0xff;
 739     switch(index) {
 740     case 0x02:
 741         s->id = (val >> 24);
 742         break;
 743     case 0x03:
 744         break;
 745     case 0x08:
 746         s->tpr = val;
 747         apic_update_irq(s);
 748         break;
 749     case 0x09:
 750     case 0x0a:
 751         break;
 752     case 0x0b: /* EOI */
 753         apic_eoi(s);
 754         break;
 755     case 0x0d:
 756         s->log_dest = val >> 24;
 757         break;
 758     case 0x0e:
 759         s->dest_mode = val >> 28;
 760         break;
 761     case 0x0f:
 762         s->spurious_vec = val & 0x1ff;
 763         apic_update_irq(s);
 764         break;
 765     case 0x10 ... 0x17:
 766     case 0x18 ... 0x1f:
 767     case 0x20 ... 0x27:
 768     case 0x28:
 769         break;
 770     case 0x30:
 771         s->icr[0] = val;
 772         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 773                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 774                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 775         break;
 776     case 0x31:
 777         s->icr[1] = val;
 778         break;
 779     case 0x32 ... 0x37:
 780         {
 781             int n = index - 0x32;
 782             s->lvt[n] = val;
 783             if (n == APIC_LVT_TIMER)
 784                 apic_timer_update(s, qemu_get_clock(vm_clock));
 785         }
 786         break;
 787     case 0x38:
 788         s->initial_count = val;
 789         s->initial_count_load_time = qemu_get_clock(vm_clock);
 790         apic_timer_update(s, s->initial_count_load_time);
 791         break;
 792     case 0x39:
 793         break;
 794     case 0x3e:
 795         {
 796             int v;
 797             s->divide_conf = val & 0xb;
 798             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 799             s->count_shift = (v + 1) & 7;
 800         }
 801         break;
 802     default:
 803         s->esr |= ESR_ILLEGAL_ADDRESS;
 804         break;
 805     }
 806 }
 807
 808 #ifdef KVM_CAP_IRQCHIP
 809
 810 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 811 {
 812     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 813 }
 814
 815 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 816                                  int reg_id, uint32_t val)
 817 {
 818     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 819 }
 820
 821 static void kvm_kernel_lapic_save_to_user(APICState *s)
 822 {
 823     struct kvm_lapic_state apic;
 824     struct kvm_lapic_state *kapic = &apic;
 825     int i, v;
 826
 827     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 828
 829     s->id = kapic_reg(kapic, 0x2);
 830     s->tpr = kapic_reg(kapic, 0x8);
 831     s->arb_id = kapic_reg(kapic, 0x9);
 832     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 833     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 834     s->spurious_vec = kapic_reg(kapic, 0xf);
 835     for (i = 0; i < 8; i++) {
 836         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 837         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 838         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 839     }
 840     s->esr = kapic_reg(kapic, 0x28);
 841     s->icr[0] = kapic_reg(kapic, 0x30);
 842     s->icr[1] = kapic_reg(kapic, 0x31);
 843     for (i = 0; i < APIC_LVT_NB; i++)
 844         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 845     s->initial_count = kapic_reg(kapic, 0x38);
 846     s->divide_conf = kapic_reg(kapic, 0x3e);
 847
 848     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 849     s->count_shift = (v + 1) & 7;
 850
 851     s->initial_count_load_time = qemu_get_clock(vm_clock);
 852     apic_timer_update(s, s->initial_count_load_time);
 853 }
 854
 855 static void kvm_kernel_lapic_load_from_user(APICState *s)
 856 {
 857     struct kvm_lapic_state apic;
 858     struct kvm_lapic_state *klapic = &apic;
 859     int i;
 860
 861     memset(klapic, 0, sizeof apic);
 862     kapic_set_reg(klapic, 0x2, s->id);
 863     kapic_set_reg(klapic, 0x8, s->tpr);
 864     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 865     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 866     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 867     for (i = 0; i < 8; i++) {
 868         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 869         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 870         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 871     }
 872     kapic_set_reg(klapic, 0x28, s->esr);
 873     kapic_set_reg(klapic, 0x30, s->icr[0]);
 874     kapic_set_reg(klapic, 0x31, s->icr[1]);
 875     for (i = 0; i < APIC_LVT_NB; i++)
 876         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 877     kapic_set_reg(klapic, 0x38, s->initial_count);
 878     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 879
 880     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 881 }
 882
 883 #endif
 884
 885 static void apic_save(QEMUFile *f, void *opaque)
 886 {
 887     APICState *s = opaque;
 888     int i;
 889
 890 #ifdef KVM_CAP_IRQCHIP
 891     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 892         kvm_kernel_lapic_save_to_user(s);
 893     }
 894 #endif
 895
 896     qemu_put_be32s(f, &s->apicbase);
 897     qemu_put_8s(f, &s->id);
 898     qemu_put_8s(f, &s->arb_id);
 899     qemu_put_8s(f, &s->tpr);
 900     qemu_put_be32s(f, &s->spurious_vec);
 901     qemu_put_8s(f, &s->log_dest);
 902     qemu_put_8s(f, &s->dest_mode);
 903     for (i = 0; i < 8; i++) {
 904         qemu_put_be32s(f, &s->isr[i]);
 905         qemu_put_be32s(f, &s->tmr[i]);
 906         qemu_put_be32s(f, &s->irr[i]);
 907     }
 908     for (i = 0; i < APIC_LVT_NB; i++) {
 909         qemu_put_be32s(f, &s->lvt[i]);
 910     }
 911     qemu_put_be32s(f, &s->esr);
 912     qemu_put_be32s(f, &s->icr[0]);
 913     qemu_put_be32s(f, &s->icr[1]);
 914     qemu_put_be32s(f, &s->divide_conf);
 915     qemu_put_be32(f, s->count_shift);
 916     qemu_put_be32s(f, &s->initial_count);
 917     qemu_put_be64(f, s->initial_count_load_time);
 918     qemu_put_be64(f, s->next_time);
 919
 920     qemu_put_timer(f, s->timer);
 921 }
 922
 923 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 924 {
 925     APICState *s = opaque;
 926     int i;
 927
 928     if (version_id > 2)
 929         return -EINVAL;
 930
 931     /* XXX: what if the base changes? (registered memory regions) */
 932     qemu_get_be32s(f, &s->apicbase);
 933     qemu_get_8s(f, &s->id);
 934     qemu_get_8s(f, &s->arb_id);
 935     qemu_get_8s(f, &s->tpr);
 936     qemu_get_be32s(f, &s->spurious_vec);
 937     qemu_get_8s(f, &s->log_dest);
 938     qemu_get_8s(f, &s->dest_mode);
 939     for (i = 0; i < 8; i++) {
 940         qemu_get_be32s(f, &s->isr[i]);
 941         qemu_get_be32s(f, &s->tmr[i]);
 942         qemu_get_be32s(f, &s->irr[i]);
 943     }
 944     for (i = 0; i < APIC_LVT_NB; i++) {
 945         qemu_get_be32s(f, &s->lvt[i]);
 946     }
 947     qemu_get_be32s(f, &s->esr);
 948     qemu_get_be32s(f, &s->icr[0]);
 949     qemu_get_be32s(f, &s->icr[1]);
 950     qemu_get_be32s(f, &s->divide_conf);
 951     s->count_shift=qemu_get_be32(f);
 952     qemu_get_be32s(f, &s->initial_count);
 953     s->initial_count_load_time=qemu_get_be64(f);
 954     s->next_time=qemu_get_be64(f);
 955
 956     if (version_id >= 2)
 957         qemu_get_timer(f, s->timer);
 958
 959 #ifdef KVM_CAP_IRQCHIP
 960     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 961         kvm_kernel_lapic_load_from_user(s);
 962     }
 963 #endif
 964
 965     return 0;
 966 }
 967
 968 static void apic_reset(void *opaque)
 969 {
 970     APICState *s = opaque;
 971
 972     s->apicbase = 0xfee00000 |
 973         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 974
 975     apic_init_ipi(s);
 976
 977     if (s->id == 0) {
 978         /*
 979          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 980          * time typically by BIOS, so PIC interrupt can be delivered to the
 981          * processor when local APIC is enabled.
 982          */
 983         s->lvt[APIC_LVT_LINT0] = 0x700;
 984     }
 985 #ifdef KVM_CAP_IRQCHIP
 986     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 987         kvm_kernel_lapic_load_from_user(s);
 988     }
 989 #endif
 990 }
 991
 992 static CPUReadMemoryFunc *apic_mem_read[3] = {
 993     apic_mem_readb,
 994     apic_mem_readw,
 995     apic_mem_readl,
 996 };
 997
 998 static CPUWriteMemoryFunc *apic_mem_write[3] = {
 999     apic_mem_writeb,
1000     apic_mem_writew,
1001     apic_mem_writel,
1002 };
1003
1004 int apic_init(CPUState *env)
1005 {
1006     APICState *s;
1007
1008     if (last_apic_id >= MAX_APICS)
1009         return -1;
1010     s = qemu_mallocz(sizeof(APICState));
1011     if (!s)
1012         return -1;
1013     env->apic_state = s;
1014     s->id = last_apic_id++;
1015     env->cpuid_apic_id = s->id;
1016     s->cpu_env = env;
1017
1018     apic_reset(s);
1019
1020     /* XXX: mapping more APICs at the same memory location */
1021     if (apic_io_memory == 0) {
1022         /* NOTE: the APIC is directly connected to the CPU - it is not
1023            on the global memory bus. */
1024         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1025                                                 apic_mem_write, NULL);
1026         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1027                                      apic_io_memory);
1028     }
1029     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1030
1031     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
1032     qemu_register_reset(apic_reset, s);
1033
1034     local_apics[s->id] = s;
1035     return 0;
1036 }
1037
1038 static void ioapic_service(IOAPICState *s)
1039 {
1040     uint8_t i;
1041     uint8_t trig_mode;
1042     uint8_t vector;
1043     uint8_t delivery_mode;
1044     uint32_t mask;
1045     uint64_t entry;
1046     uint8_t dest;
1047     uint8_t dest_mode;
1048     uint8_t polarity;
1049     uint32_t deliver_bitmask[MAX_APIC_WORDS];
1050
1051     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1052         mask = 1 << i;
1053         if (s->irr & mask) {
1054             entry = s->ioredtbl[i];
1055             if (!(entry & APIC_LVT_MASKED)) {
1056                 trig_mode = ((entry >> 15) & 1);
1057                 dest = entry >> 56;
1058                 dest_mode = (entry >> 11) & 1;
1059                 delivery_mode = (entry >> 8) & 7;
1060                 polarity = (entry >> 13) & 1;
1061                 if (trig_mode == APIC_TRIGGER_EDGE)
1062                     s->irr &= ~mask;
1063                 if (delivery_mode == APIC_DM_EXTINT)
1064                     vector = pic_read_irq(isa_pic);
1065                 else
1066                     vector = entry & 0xff;
1067
1068                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
1069                 apic_bus_deliver(deliver_bitmask, delivery_mode,
1070                                  vector, polarity, trig_mode);
1071             }
1072         }
1073     }
1074 }
1075
1076 void ioapic_set_irq(void *opaque, int vector, int level)
1077 {
1078     IOAPICState *s = opaque;
1079
1080 #if 0
1081     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
1082      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
1083      * the cleanest way of doing it but it should work. */
1084
1085     if (vector == 0)
1086         vector = 2;
1087 #endif
1088
1089     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1090         uint32_t mask = 1 << vector;
1091         uint64_t entry = s->ioredtbl[vector];
1092
1093         if ((entry >> 15) & 1) {
1094             /* level triggered */
1095             if (level) {
1096                 s->irr |= mask;
1097                 ioapic_service(s);
1098             } else {
1099                 s->irr &= ~mask;
1100             }
1101         } else {
1102             /* edge triggered */
1103             if (level) {
1104                 s->irr |= mask;
1105                 ioapic_service(s);
1106             }
1107         }
1108     }
1109 }
1110
1111 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1112 {
1113     IOAPICState *s = opaque;
1114     int index;
1115     uint32_t val = 0;
1116
1117     addr &= 0xff;
1118     if (addr == 0x00) {
1119         val = s->ioregsel;
1120     } else if (addr == 0x10) {
1121         switch (s->ioregsel) {
1122             case 0x00:
1123                 val = s->id << 24;
1124                 break;
1125             case 0x01:
1126                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1127                 break;
1128             case 0x02:
1129                 val = 0;
1130                 break;
1131             default:
1132                 index = (s->ioregsel - 0x10) >> 1;
1133                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1134                     if (s->ioregsel & 1)
1135                         val = s->ioredtbl[index] >> 32;
1136                     else
1137                         val = s->ioredtbl[index] & 0xffffffff;
1138                 }
1139         }
1140 #ifdef DEBUG_IOAPIC
1141         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1142 #endif
1143     }
1144     return val;
1145 }
1146
1147 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1148 {
1149     IOAPICState *s = opaque;
1150     int index;
1151
1152     addr &= 0xff;
1153     if (addr == 0x00)  {
1154         s->ioregsel = val;
1155         return;
1156     } else if (addr == 0x10) {
1157 #ifdef DEBUG_IOAPIC
1158         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1159 #endif
1160         switch (s->ioregsel) {
1161             case 0x00:
1162                 s->id = (val >> 24) & 0xff;
1163                 return;
1164             case 0x01:
1165             case 0x02:
1166                 return;
1167             default:
1168                 index = (s->ioregsel - 0x10) >> 1;
1169                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1170                     if (s->ioregsel & 1) {
1171                         s->ioredtbl[index] &= 0xffffffff;
1172                         s->ioredtbl[index] |= (uint64_t)val << 32;
1173                     } else {
1174                         s->ioredtbl[index] &= ~0xffffffffULL;
1175                         s->ioredtbl[index] |= val;
1176                     }
1177                     ioapic_service(s);
1178                 }
1179         }
1180     }
1181 }
1182
1183 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
1184 {
1185 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1186     struct kvm_irqchip chip;
1187     struct kvm_ioapic_state *kioapic;
1188     int i;
1189
1190     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1191     kvm_get_irqchip(kvm_context, &chip);
1192     kioapic = &chip.chip.ioapic;
1193
1194     s->id = kioapic->id;
1195     s->ioregsel = kioapic->ioregsel;
1196     s->base_address = kioapic->base_address;
1197     s->irr = kioapic->irr;
1198     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1199         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
1200     }
1201 #endif
1202 }
1203
1204 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
1205 {
1206 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1207     struct kvm_irqchip chip;
1208     struct kvm_ioapic_state *kioapic;
1209     int i;
1210
1211     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1212     kioapic = &chip.chip.ioapic;
1213
1214     kioapic->id = s->id;
1215     kioapic->ioregsel = s->ioregsel;
1216     kioapic->base_address = s->base_address;
1217     kioapic->irr = s->irr;
1218     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1219         kioapic->redirtbl[i].bits = s->ioredtbl[i];
1220     }
1221
1222     kvm_set_irqchip(kvm_context, &chip);
1223 #endif
1224 }
1225
1226 static void ioapic_save(QEMUFile *f, void *opaque)
1227 {
1228     IOAPICState *s = opaque;
1229     int i;
1230
1231     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1232         kvm_kernel_ioapic_save_to_user(s);
1233     }
1234
1235     qemu_put_8s(f, &s->id);
1236     qemu_put_8s(f, &s->ioregsel);
1237     qemu_put_be64s(f, &s->base_address);
1238     qemu_put_be32s(f, &s->irr);
1239     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1240         qemu_put_be64s(f, &s->ioredtbl[i]);
1241     }
1242 }
1243
1244 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1245 {
1246     IOAPICState *s = opaque;
1247     int i;
1248
1249     if (version_id < 1 || version_id > 2)
1250         return -EINVAL;
1251
1252     qemu_get_8s(f, &s->id);
1253     qemu_get_8s(f, &s->ioregsel);
1254     if (version_id == 2) {
1255       /* for version 2, we get this data off of the wire */
1256       qemu_get_be64s(f, &s->base_address);
1257       qemu_get_be32s(f, &s->irr);
1258     }
1259     else {
1260       /* in case we are doing version 1, we just set these to sane values */
1261       s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1262       s->irr = 0;
1263     }
1264     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1265         qemu_get_be64s(f, &s->ioredtbl[i]);
1266     }
1267
1268     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1269         kvm_kernel_ioapic_load_from_user(s);
1270     }
1271
1272     return 0;
1273 }
1274
1275 static void ioapic_reset(void *opaque)
1276 {
1277     IOAPICState *s = opaque;
1278     int i;
1279
1280     memset(s, 0, sizeof(*s));
1281     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1282     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1283         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1284 #ifdef KVM_CAP_IRQCHIP
1285     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1286         kvm_kernel_ioapic_load_from_user(s);
1287     }
1288 #endif
1289 }
1290
1291 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1292     ioapic_mem_readl,
1293     ioapic_mem_readl,
1294     ioapic_mem_readl,
1295 };
1296
1297 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1298     ioapic_mem_writel,
1299     ioapic_mem_writel,
1300     ioapic_mem_writel,
1301 };
1302
1303 IOAPICState *ioapic_init(void)
1304 {
1305     IOAPICState *s;
1306     int io_memory;
1307
1308     s = qemu_mallocz(sizeof(IOAPICState));
1309     if (!s)
1310         return NULL;
1311     ioapic_reset(s);
1312     s->id = last_apic_id++;
1313
1314     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1315                                        ioapic_mem_write, s);
1316     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1317
1318     register_savevm("ioapic", 0, 2, ioapic_save, ioapic_load, s);
1319     qemu_register_reset(ioapic_reset, s);
1320
1321     return s;
1322 }