hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "qemu-timer.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "kvm.h"
  27 #ifdef USE_KVM
  28 #include "qemu-kvm.h"
  29 #endif
  30 #include "string.h"
  31
  32 //#define DEBUG
  33
  34 /* i82731AB (PIIX4) compatible power management function */
  35 #define PM_FREQ 3579545
  36
  37 #define ACPI_DBG_IO_ADDR  0xb044
  38
  39 typedef struct PIIX4PMState {
  40     PCIDevice dev;
  41     uint16_t pmsts;
  42     uint16_t pmen;
  43     uint16_t pmcntrl;
  44     uint8_t apmc;
  45     uint8_t apms;
  46     QEMUTimer *tmr_timer;
  47     int64_t tmr_overflow_time;
  48     i2c_bus *smbus;
  49     uint8_t smb_stat;
  50     uint8_t smb_ctl;
  51     uint8_t smb_cmd;
  52     uint8_t smb_addr;
  53     uint8_t smb_data0;
  54     uint8_t smb_data1;
  55     uint8_t smb_data[32];
  56     uint8_t smb_index;
  57     qemu_irq irq;
  58 } PIIX4PMState;
  59
  60 #define RTC_EN (1 << 10)
  61 #define PWRBTN_EN (1 << 8)
  62 #define GBL_EN (1 << 5)
  63 #define TMROF_EN (1 << 0)
  64
  65 #define SCI_EN (1 << 0)
  66
  67 #define SUS_EN (1 << 13)
  68
  69 #define ACPI_ENABLE 0xf1
  70 #define ACPI_DISABLE 0xf0
  71
  72 #define SMBHSTSTS 0x00
  73 #define SMBHSTCNT 0x02
  74 #define SMBHSTCMD 0x03
  75 #define SMBHSTADD 0x04
  76 #define SMBHSTDAT0 0x05
  77 #define SMBHSTDAT1 0x06
  78 #define SMBBLKDAT 0x07
  79
  80 static PIIX4PMState *pm_state;
  81
  82 static uint32_t get_pmtmr(PIIX4PMState *s)
  83 {
  84     uint32_t d;
  85     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  86     return d & 0xffffff;
  87 }
  88
  89 static int get_pmsts(PIIX4PMState *s)
  90 {
  91     int64_t d;
  92     int pmsts;
  93     pmsts = s->pmsts;
  94     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  95     if (d >= s->tmr_overflow_time)
  96         s->pmsts |= TMROF_EN;
  97     return pmsts;
  98 }
  99
 100 static void pm_update_sci(PIIX4PMState *s)
 101 {
 102     int sci_level, pmsts;
 103     int64_t expire_time;
 104
 105     pmsts = get_pmsts(s);
 106     sci_level = (((pmsts & s->pmen) &
 107                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 108     qemu_set_irq(s->irq, sci_level);
 109     /* schedule a timer interruption if needed */
 110     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 111         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 112         qemu_mod_timer(s->tmr_timer, expire_time);
 113     } else {
 114         qemu_del_timer(s->tmr_timer);
 115     }
 116 }
 117
 118 static void pm_tmr_timer(void *opaque)
 119 {
 120     PIIX4PMState *s = opaque;
 121     pm_update_sci(s);
 122 }
 123
 124 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 125 {
 126     PIIX4PMState *s = opaque;
 127     addr &= 0x3f;
 128     switch(addr) {
 129     case 0x00:
 130         {
 131             int64_t d;
 132             int pmsts;
 133             pmsts = get_pmsts(s);
 134             if (pmsts & val & TMROF_EN) {
 135                 /* if TMRSTS is reset, then compute the new overflow time */
 136                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 137                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 138             }
 139             s->pmsts &= ~val;
 140             pm_update_sci(s);
 141         }
 142         break;
 143     case 0x02:
 144         s->pmen = val;
 145         pm_update_sci(s);
 146         break;
 147     case 0x04:
 148         {
 149             int sus_typ;
 150             s->pmcntrl = val & ~(SUS_EN);
 151             if (val & SUS_EN) {
 152                 /* change suspend type */
 153                 sus_typ = (val >> 10) & 7;
 154                 switch(sus_typ) {
 155                 case 0: /* soft power off */
 156                     qemu_system_shutdown_request();
 157                     break;
 158                 default:
 159                     break;
 160                 }
 161             }
 162         }
 163         break;
 164     default:
 165         break;
 166     }
 167 #ifdef DEBUG
 168     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 169 #endif
 170 }
 171
 172 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 173 {
 174     PIIX4PMState *s = opaque;
 175     uint32_t val;
 176
 177     addr &= 0x3f;
 178     switch(addr) {
 179     case 0x00:
 180         val = get_pmsts(s);
 181         break;
 182     case 0x02:
 183         val = s->pmen;
 184         break;
 185     case 0x04:
 186         val = s->pmcntrl;
 187         break;
 188     default:
 189         val = 0;
 190         break;
 191     }
 192 #ifdef DEBUG
 193     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 194 #endif
 195     return val;
 196 }
 197
 198 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 199 {
 200     //    PIIX4PMState *s = opaque;
 201     addr &= 0x3f;
 202 #ifdef DEBUG
 203     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 204 #endif
 205 }
 206
 207 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 208 {
 209     PIIX4PMState *s = opaque;
 210     uint32_t val;
 211
 212     addr &= 0x3f;
 213     switch(addr) {
 214     case 0x08:
 215         val = get_pmtmr(s);
 216         break;
 217     default:
 218         val = 0;
 219         break;
 220     }
 221 #ifdef DEBUG
 222     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 223 #endif
 224     return val;
 225 }
 226
 227 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 228 {
 229     PIIX4PMState *s = opaque;
 230     addr &= 1;
 231 #ifdef DEBUG
 232     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 233 #endif
 234     if (addr == 0) {
 235         s->apmc = val;
 236
 237         /* ACPI specs 3.0, 4.7.2.5 */
 238         if (val == ACPI_ENABLE) {
 239             s->pmcntrl |= SCI_EN;
 240         } else if (val == ACPI_DISABLE) {
 241             s->pmcntrl &= ~SCI_EN;
 242         }
 243
 244         if (s->dev.config[0x5b] & (1 << 1)) {
 245             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 246         }
 247     } else {
 248         s->apms = val;
 249     }
 250 }
 251
 252 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 253 {
 254     PIIX4PMState *s = opaque;
 255     uint32_t val;
 256
 257     addr &= 1;
 258     if (addr == 0) {
 259         val = s->apmc;
 260     } else {
 261         val = s->apms;
 262     }
 263 #ifdef DEBUG
 264     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 265 #endif
 266     return val;
 267 }
 268
 269 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 270 {
 271 #if defined(DEBUG)
 272     printf("ACPI: DBG: 0x%08x\n", val);
 273 #endif
 274 }
 275
 276 static void smb_transaction(PIIX4PMState *s)
 277 {
 278     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 279     uint8_t read = s->smb_addr & 0x01;
 280     uint8_t cmd = s->smb_cmd;
 281     uint8_t addr = s->smb_addr >> 1;
 282     i2c_bus *bus = s->smbus;
 283
 284 #ifdef DEBUG
 285     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 286 #endif
 287     switch(prot) {
 288     case 0x0:
 289         smbus_quick_command(bus, addr, read);
 290         break;
 291     case 0x1:
 292         if (read) {
 293             s->smb_data0 = smbus_receive_byte(bus, addr);
 294         } else {
 295             smbus_send_byte(bus, addr, cmd);
 296         }
 297         break;
 298     case 0x2:
 299         if (read) {
 300             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 301         } else {
 302             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 303         }
 304         break;
 305     case 0x3:
 306         if (read) {
 307             uint16_t val;
 308             val = smbus_read_word(bus, addr, cmd);
 309             s->smb_data0 = val;
 310             s->smb_data1 = val >> 8;
 311         } else {
 312             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 313         }
 314         break;
 315     case 0x5:
 316         if (read) {
 317             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 318         } else {
 319             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 320         }
 321         break;
 322     default:
 323         goto error;
 324     }
 325     return;
 326
 327   error:
 328     s->smb_stat |= 0x04;
 329 }
 330
 331 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 332 {
 333     PIIX4PMState *s = opaque;
 334     addr &= 0x3f;
 335 #ifdef DEBUG
 336     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 337 #endif
 338     switch(addr) {
 339     case SMBHSTSTS:
 340         s->smb_stat = 0;
 341         s->smb_index = 0;
 342         break;
 343     case SMBHSTCNT:
 344         s->smb_ctl = val;
 345         if (val & 0x40)
 346             smb_transaction(s);
 347         break;
 348     case SMBHSTCMD:
 349         s->smb_cmd = val;
 350         break;
 351     case SMBHSTADD:
 352         s->smb_addr = val;
 353         break;
 354     case SMBHSTDAT0:
 355         s->smb_data0 = val;
 356         break;
 357     case SMBHSTDAT1:
 358         s->smb_data1 = val;
 359         break;
 360     case SMBBLKDAT:
 361         s->smb_data[s->smb_index++] = val;
 362         if (s->smb_index > 31)
 363             s->smb_index = 0;
 364         break;
 365     default:
 366         break;
 367     }
 368 }
 369
 370 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 371 {
 372     PIIX4PMState *s = opaque;
 373     uint32_t val;
 374
 375     addr &= 0x3f;
 376     switch(addr) {
 377     case SMBHSTSTS:
 378         val = s->smb_stat;
 379         break;
 380     case SMBHSTCNT:
 381         s->smb_index = 0;
 382         val = s->smb_ctl & 0x1f;
 383         break;
 384     case SMBHSTCMD:
 385         val = s->smb_cmd;
 386         break;
 387     case SMBHSTADD:
 388         val = s->smb_addr;
 389         break;
 390     case SMBHSTDAT0:
 391         val = s->smb_data0;
 392         break;
 393     case SMBHSTDAT1:
 394         val = s->smb_data1;
 395         break;
 396     case SMBBLKDAT:
 397         val = s->smb_data[s->smb_index++];
 398         if (s->smb_index > 31)
 399             s->smb_index = 0;
 400         break;
 401     default:
 402         val = 0;
 403         break;
 404     }
 405 #ifdef DEBUG
 406     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 407 #endif
 408     return val;
 409 }
 410
 411 static void pm_io_space_update(PIIX4PMState *s)
 412 {
 413     uint32_t pm_io_base;
 414
 415     if (s->dev.config[0x80] & 1) {
 416         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 417         pm_io_base &= 0xffc0;
 418
 419         /* XXX: need to improve memory and ioport allocation */
 420 #if defined(DEBUG)
 421         printf("PM: mapping to 0x%x\n", pm_io_base);
 422 #endif
 423         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 424         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 425         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 426         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 427     }
 428 }
 429
 430 static void pm_write_config(PCIDevice *d,
 431                             uint32_t address, uint32_t val, int len)
 432 {
 433     pci_default_write_config(d, address, val, len);
 434     if (address == 0x80)
 435         pm_io_space_update((PIIX4PMState *)d);
 436 }
 437
 438 static void pm_save(QEMUFile* f,void *opaque)
 439 {
 440     PIIX4PMState *s = opaque;
 441
 442     pci_device_save(&s->dev, f);
 443
 444     qemu_put_be16s(f, &s->pmsts);
 445     qemu_put_be16s(f, &s->pmen);
 446     qemu_put_be16s(f, &s->pmcntrl);
 447     qemu_put_8s(f, &s->apmc);
 448     qemu_put_8s(f, &s->apms);
 449     qemu_put_timer(f, s->tmr_timer);
 450     qemu_put_be64(f, s->tmr_overflow_time);
 451 }
 452
 453 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 454 {
 455     PIIX4PMState *s = opaque;
 456     int ret;
 457
 458     if (version_id > 1)
 459         return -EINVAL;
 460
 461     ret = pci_device_load(&s->dev, f);
 462     if (ret < 0)
 463         return ret;
 464
 465     qemu_get_be16s(f, &s->pmsts);
 466     qemu_get_be16s(f, &s->pmen);
 467     qemu_get_be16s(f, &s->pmcntrl);
 468     qemu_get_8s(f, &s->apmc);
 469     qemu_get_8s(f, &s->apms);
 470     qemu_get_timer(f, s->tmr_timer);
 471     s->tmr_overflow_time=qemu_get_be64(f);
 472
 473     pm_io_space_update(s);
 474
 475     return 0;
 476 }
 477
 478 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 479                        qemu_irq sci_irq)
 480 {
 481     PIIX4PMState *s;
 482     uint8_t *pci_conf;
 483
 484     s = (PIIX4PMState *)pci_register_device(bus,
 485                                          "PM", sizeof(PIIX4PMState),
 486                                          devfn, NULL, pm_write_config);
 487     pm_state = s;
 488     pci_conf = s->dev.config;
 489     pci_conf[0x00] = 0x86;
 490     pci_conf[0x01] = 0x80;
 491     pci_conf[0x02] = 0x13;
 492     pci_conf[0x03] = 0x71;
 493     pci_conf[0x06] = 0x80;
 494     pci_conf[0x07] = 0x02;
 495     pci_conf[0x08] = 0x03; // revision number
 496     pci_conf[0x09] = 0x00;
 497     pci_conf[0x0a] = 0x80; // other bridge device
 498     pci_conf[0x0b] = 0x06; // bridge device
 499     pci_conf[0x0e] = 0x00; // header_type
 500     pci_conf[0x3d] = 0x01; // interrupt pin 1
 501
 502     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 503
 504 #if defined(TARGET_IA64)
 505     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 506     pci_conf[0x41] = 0x1f;
 507     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 508     s->pmcntrl = SCI_EN;
 509 #endif
 510
 511     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 512     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 513
 514     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 515
 516     if (kvm_enabled()) {
 517         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 518          * support SMM mode. */
 519         pci_conf[0x5B] = 0x02;
 520     }
 521
 522     /* XXX: which specification is used ? The i82731AB has different
 523        mappings */
 524     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 525     pci_conf[0x63] = 0x60;
 526     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 527         (serial_hds[1] != NULL ? 0x90 : 0);
 528
 529     pci_conf[0x90] = smb_io_base | 1;
 530     pci_conf[0x91] = smb_io_base >> 8;
 531     pci_conf[0xd2] = 0x09;
 532     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 533     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 534
 535     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 536
 537     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 538
 539     s->smbus = i2c_init_bus();
 540     s->irq = sci_irq;
 541     return s->smbus;
 542 }
 543
 544 #if defined(TARGET_I386)
 545 void qemu_system_powerdown(void)
 546 {
 547     if (!pm_state) {
 548         qemu_system_shutdown_request();
 549     } else if (pm_state->pmen & PWRBTN_EN) {
 550         pm_state->pmsts |= PWRBTN_EN;
 551         pm_update_sci(pm_state);
 552     }
 553 }
 554 #endif
 555 #define GPE_BASE 0xafe0
 556 #define PROC_BASE 0xaf00
 557 #define PCI_BASE 0xae00
 558 #define PCI_EJ_BASE 0xae08
 559
 560 struct gpe_regs {
 561     uint16_t sts; /* status */
 562     uint16_t en;  /* enabled */
 563     uint8_t up;
 564     uint8_t down;
 565 };
 566
 567 struct pci_status {
 568     uint32_t up;
 569     uint32_t down;
 570 };
 571
 572 static struct gpe_regs gpe;
 573 static struct pci_status pci0_status;
 574
 575 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 576 {
 577     uint32_t val = 0;
 578     struct gpe_regs *g = opaque;
 579     switch (addr) {
 580         case PROC_BASE:
 581             val = g->up;
 582             break;
 583         case PROC_BASE + 1:
 584             val = g->down;
 585             break;
 586
 587         case GPE_BASE:
 588             val = g->sts & 0xFF;
 589             break;
 590         case GPE_BASE + 1:
 591             val =  (g->sts >> 8) & 0xFF;
 592             break;
 593         case GPE_BASE + 2:
 594             val =  g->en & 0xFF;
 595             break;
 596         case GPE_BASE + 3:
 597             val =  (g->en >> 8) & 0xFF;
 598             break;
 599         default:
 600             break;
 601     }
 602
 603 #if defined(DEBUG)
 604     printf("gpe read %x == %x\n", addr, val);
 605 #endif
 606     return val;
 607 }
 608
 609 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 610 {
 611     struct gpe_regs *g = opaque;
 612     switch (addr) {
 613         case PROC_BASE:
 614             g->up = val;
 615             break;
 616         case PROC_BASE + 1:
 617             g->down = val;
 618             break;
 619
 620         case GPE_BASE:
 621             g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
 622             break;
 623         case GPE_BASE + 1:
 624             g->sts = (g->sts & 0xFFFF) | (val << 8);
 625             break;
 626         case GPE_BASE + 2:
 627             g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
 628             break;
 629         case GPE_BASE + 3:
 630             g->en = (g->en & 0xFFFF) | (val << 8);
 631             break;
 632         default:
 633             break;
 634    }
 635
 636 #if defined(DEBUG)
 637     printf("gpe write %x <== %d\n", addr, val);
 638 #endif
 639 }
 640
 641 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 642 {
 643     uint32_t val = 0;
 644     struct pci_status *g = opaque;
 645     switch (addr) {
 646         case PCI_BASE:
 647             val = g->up;
 648             break;
 649         case PCI_BASE + 4:
 650             val = g->down;
 651             break;
 652         default:
 653             break;
 654     }
 655
 656 #if defined(DEBUG)
 657     printf("pcihotplug read %x == %x\n", addr, val);
 658 #endif
 659     return val;
 660 }
 661
 662 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 663 {
 664     struct pci_status *g = opaque;
 665     switch (addr) {
 666         case PCI_BASE:
 667             g->up = val;
 668             break;
 669         case PCI_BASE + 4:
 670             g->down = val;
 671             break;
 672    }
 673
 674 #if defined(DEBUG)
 675     printf("pcihotplug write %x <== %d\n", addr, val);
 676 #endif
 677 }
 678
 679 static uint32_t pciej_read(void *opaque, uint32_t addr)
 680 {
 681 #if defined(DEBUG)
 682     printf("pciej read %x\n", addr);
 683 #endif
 684     return 0;
 685 }
 686
 687 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 688 {
 689     int slot = ffs(val) - 1;
 690
 691     device_hot_remove_success(0, slot);
 692
 693 #if defined(DEBUG)
 694     printf("pciej write %x <== %d\n", addr, val);
 695 #endif
 696 }
 697
 698 static const char *model;
 699
 700 void qemu_system_hot_add_init(const char *cpu_model)
 701 {
 702     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 703     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 704
 705     register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe);
 706     register_ioport_read(PROC_BASE, 4, 1,  gpe_readb, &gpe);
 707
 708     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 709     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 710
 711     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
 712     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 713
 714     model = cpu_model;
 715 }
 716
 717 static void enable_processor(struct gpe_regs *g, int cpu)
 718 {
 719     g->sts |= 1;
 720     g->en |= 1;
 721     g->up |= (1 << cpu);
 722 }
 723
 724 static void disable_processor(struct gpe_regs *g, int cpu)
 725 {
 726     g->sts |= 1;
 727     g->en |= 1;
 728     g->down |= (1 << cpu);
 729 }
 730
 731 #if defined(TARGET_I386) || defined(TARGET_X86_64)
 732 #ifdef USE_KVM
 733 static CPUState *qemu_kvm_cpu_env(int index)
 734 {
 735     CPUState *penv;
 736
 737     penv = first_cpu;
 738
 739     while (penv) {
 740         if (penv->cpu_index == index)
 741             return penv;
 742         penv = (CPUState *)penv->next_cpu;
 743     }
 744
 745     return NULL;
 746 }
 747 #endif
 748
 749
 750 void qemu_system_cpu_hot_add(int cpu, int state)
 751 {
 752     CPUState *env;
 753
 754     if (state
 755 #ifdef USE_KVM
 756         && (!qemu_kvm_cpu_env(cpu))
 757 #endif
 758     ) {
 759         env = pc_new_cpu(cpu, model, 1);
 760         if (!env) {
 761             fprintf(stderr, "cpu %d creation failed\n", cpu);
 762             return;
 763         }
 764 #ifdef USE_KVM
 765         kvm_init_vcpu(env);
 766 #endif
 767     }
 768
 769     qemu_set_irq(pm_state->irq, 1);
 770     gpe.up = 0;
 771     gpe.down = 0;
 772     if (state)
 773         enable_processor(&gpe, cpu);
 774     else
 775         disable_processor(&gpe, cpu);
 776     qemu_set_irq(pm_state->irq, 0);
 777 }
 778 #endif
 779
 780 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 781 {
 782     g->sts |= 2;
 783     g->en |= 2;
 784     p->up |= (1 << slot);
 785 }
 786
 787 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 788 {
 789     g->sts |= 2;
 790     g->en |= 2;
 791     p->down |= (1 << slot);
 792 }
 793
 794 void qemu_system_device_hot_add(int pcibus, int slot, int state)
 795 {
 796     qemu_set_irq(pm_state->irq, 1);
 797     pci0_status.up = 0;
 798     pci0_status.down = 0;
 799     if (state)
 800         enable_device(&pci0_status, &gpe, slot);
 801     else
 802         disable_device(&pci0_status, &gpe, slot);
 803     qemu_set_irq(pm_state->irq, 0);
 804 }