qemu-kvm-x86.c

   1
   2 #include "config.h"
   3 #include "config-host.h"
   4
   5 #include <string.h>
   6 #include "hw/hw.h"
   7
   8 #include "qemu-kvm.h"
   9 #include <libkvm.h>
  10 #include <pthread.h>
  11 #include <sys/utsname.h>
  12
  13 #define MSR_IA32_TSC            0x10
  14
  15 static struct kvm_msr_list *kvm_msr_list;
  16 extern unsigned int kvm_shadow_memory;
  17 extern kvm_context_t kvm_context;
  18 static int kvm_has_msr_star;
  19
  20 static int lm_capable_kernel;
  21
  22 int kvm_arch_qemu_create_context(void)
  23 {
  24     int i;
  25     struct utsname utsname;
  26
  27     uname(&utsname);
  28     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
  29
  30     if (kvm_shadow_memory)
  31         kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
  32
  33     kvm_msr_list = kvm_get_msr_list(kvm_context);
  34     if (!kvm_msr_list)
  35                 return -1;
  36     for (i = 0; i < kvm_msr_list->nmsrs; ++i)
  37         if (kvm_msr_list->indices[i] == MSR_STAR)
  38             kvm_has_msr_star = 1;
  39         return 0;
  40 }
  41
  42 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
  43                           uint64_t data)
  44 {
  45     entry->index = index;
  46     entry->data  = data;
  47 }
  48
  49 /* returns 0 on success, non-0 on failure */
  50 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
  51 {
  52         switch (entry->index) {
  53         case MSR_IA32_SYSENTER_CS:
  54             env->sysenter_cs  = entry->data;
  55             break;
  56         case MSR_IA32_SYSENTER_ESP:
  57             env->sysenter_esp = entry->data;
  58             break;
  59         case MSR_IA32_SYSENTER_EIP:
  60             env->sysenter_eip = entry->data;
  61             break;
  62         case MSR_STAR:
  63             env->star         = entry->data;
  64             break;
  65 #ifdef TARGET_X86_64
  66         case MSR_CSTAR:
  67             env->cstar        = entry->data;
  68             break;
  69         case MSR_KERNELGSBASE:
  70             env->kernelgsbase = entry->data;
  71             break;
  72         case MSR_FMASK:
  73             env->fmask        = entry->data;
  74             break;
  75         case MSR_LSTAR:
  76             env->lstar        = entry->data;
  77             break;
  78 #endif
  79         case MSR_IA32_TSC:
  80             env->tsc          = entry->data;
  81             break;
  82         default:
  83             printf("Warning unknown msr index 0x%x\n", entry->index);
  84             return 1;
  85         }
  86         return 0;
  87 }
  88
  89 #ifdef TARGET_X86_64
  90 #define MSR_COUNT 9
  91 #else
  92 #define MSR_COUNT 5
  93 #endif
  94
  95 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
  96 {
  97     lhs->selector = rhs->selector;
  98     lhs->base = rhs->base;
  99     lhs->limit = rhs->limit;
 100     lhs->type = 3;
 101     lhs->present = 1;
 102     lhs->dpl = 3;
 103     lhs->db = 0;
 104     lhs->s = 1;
 105     lhs->l = 0;
 106     lhs->g = 0;
 107     lhs->avl = 0;
 108     lhs->unusable = 0;
 109 }
 110
 111 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 112 {
 113     unsigned flags = rhs->flags;
 114     lhs->selector = rhs->selector;
 115     lhs->base = rhs->base;
 116     lhs->limit = rhs->limit;
 117     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 118     lhs->present = (flags & DESC_P_MASK) != 0;
 119     lhs->dpl = rhs->selector & 3;
 120     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 121     lhs->s = (flags & DESC_S_MASK) != 0;
 122     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 123     lhs->g = (flags & DESC_G_MASK) != 0;
 124     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 125     lhs->unusable = 0;
 126 }
 127
 128 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 129 {
 130     lhs->selector = rhs->selector;
 131     lhs->base = rhs->base;
 132     lhs->limit = rhs->limit;
 133     lhs->flags =
 134         (rhs->type << DESC_TYPE_SHIFT)
 135         | (rhs->present * DESC_P_MASK)
 136         | (rhs->dpl << DESC_DPL_SHIFT)
 137         | (rhs->db << DESC_B_SHIFT)
 138         | (rhs->s * DESC_S_MASK)
 139         | (rhs->l << DESC_L_SHIFT)
 140         | (rhs->g * DESC_G_MASK)
 141         | (rhs->avl * DESC_AVL_MASK);
 142 }
 143
 144 /* the reset values of qemu are not compatible to SVM
 145  * this function is used to fix the segment descriptor values */
 146 static void fix_realmode_dataseg(struct kvm_segment *seg)
 147 {
 148         seg->type = 0x02;
 149         seg->present = 1;
 150         seg->s = 1;
 151 }
 152
 153 void kvm_arch_load_regs(CPUState *env)
 154 {
 155     struct kvm_regs regs;
 156     struct kvm_fpu fpu;
 157     struct kvm_sregs sregs;
 158     struct kvm_msr_entry msrs[MSR_COUNT];
 159     int rc, n, i;
 160
 161     regs.rax = env->regs[R_EAX];
 162     regs.rbx = env->regs[R_EBX];
 163     regs.rcx = env->regs[R_ECX];
 164     regs.rdx = env->regs[R_EDX];
 165     regs.rsi = env->regs[R_ESI];
 166     regs.rdi = env->regs[R_EDI];
 167     regs.rsp = env->regs[R_ESP];
 168     regs.rbp = env->regs[R_EBP];
 169 #ifdef TARGET_X86_64
 170     regs.r8 = env->regs[8];
 171     regs.r9 = env->regs[9];
 172     regs.r10 = env->regs[10];
 173     regs.r11 = env->regs[11];
 174     regs.r12 = env->regs[12];
 175     regs.r13 = env->regs[13];
 176     regs.r14 = env->regs[14];
 177     regs.r15 = env->regs[15];
 178 #endif
 179
 180     regs.rflags = env->eflags;
 181     regs.rip = env->eip;
 182
 183     kvm_set_regs(kvm_context, env->cpu_index, &regs);
 184
 185     memset(&fpu, 0, sizeof fpu);
 186     fpu.fsw = env->fpus & ~(7 << 11);
 187     fpu.fsw |= (env->fpstt & 7) << 11;
 188     fpu.fcw = env->fpuc;
 189     for (i = 0; i < 8; ++i)
 190         fpu.ftwx |= (!env->fptags[i]) << i;
 191     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 192     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 193     fpu.mxcsr = env->mxcsr;
 194     kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
 195
 196     memcpy(sregs.interrupt_bitmap, env->kvm_interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
 197
 198     if ((env->eflags & VM_MASK)) {
 199             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 200             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 201             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 202             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 203             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 204             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 205     } else {
 206             set_seg(&sregs.cs, &env->segs[R_CS]);
 207             set_seg(&sregs.ds, &env->segs[R_DS]);
 208             set_seg(&sregs.es, &env->segs[R_ES]);
 209             set_seg(&sregs.fs, &env->segs[R_FS]);
 210             set_seg(&sregs.gs, &env->segs[R_GS]);
 211             set_seg(&sregs.ss, &env->segs[R_SS]);
 212
 213             if (env->cr[0] & CR0_PE_MASK) {
 214                 /* force ss cpl to cs cpl */
 215                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 216                         (sregs.cs.selector & 3);
 217                 sregs.ss.dpl = sregs.ss.selector & 3;
 218             }
 219
 220             if (!(env->cr[0] & CR0_PG_MASK)) {
 221                     fix_realmode_dataseg(&sregs.cs);
 222                     fix_realmode_dataseg(&sregs.ds);
 223                     fix_realmode_dataseg(&sregs.es);
 224                     fix_realmode_dataseg(&sregs.fs);
 225                     fix_realmode_dataseg(&sregs.gs);
 226                     fix_realmode_dataseg(&sregs.ss);
 227             }
 228     }
 229
 230     set_seg(&sregs.tr, &env->tr);
 231     set_seg(&sregs.ldt, &env->ldt);
 232
 233     sregs.idt.limit = env->idt.limit;
 234     sregs.idt.base = env->idt.base;
 235     sregs.gdt.limit = env->gdt.limit;
 236     sregs.gdt.base = env->gdt.base;
 237
 238     sregs.cr0 = env->cr[0];
 239     sregs.cr2 = env->cr[2];
 240     sregs.cr3 = env->cr[3];
 241     sregs.cr4 = env->cr[4];
 242
 243     sregs.apic_base = cpu_get_apic_base(env);
 244     sregs.efer = env->efer;
 245     sregs.cr8 = cpu_get_apic_tpr(env);
 246
 247     kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
 248
 249     /* msrs */
 250     n = 0;
 251     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS,  env->sysenter_cs);
 252     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 253     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 254     if (kvm_has_msr_star)
 255         set_msr_entry(&msrs[n++], MSR_STAR,              env->star);
 256     set_msr_entry(&msrs[n++], MSR_IA32_TSC, env->tsc);
 257 #ifdef TARGET_X86_64
 258     if (lm_capable_kernel) {
 259         set_msr_entry(&msrs[n++], MSR_CSTAR,             env->cstar);
 260         set_msr_entry(&msrs[n++], MSR_KERNELGSBASE,      env->kernelgsbase);
 261         set_msr_entry(&msrs[n++], MSR_FMASK,             env->fmask);
 262         set_msr_entry(&msrs[n++], MSR_LSTAR  ,           env->lstar);
 263     }
 264 #endif
 265
 266     rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
 267     if (rc == -1)
 268         perror("kvm_set_msrs FAILED");
 269 }
 270
 271
 272 void kvm_arch_save_regs(CPUState *env)
 273 {
 274     struct kvm_regs regs;
 275     struct kvm_fpu fpu;
 276     struct kvm_sregs sregs;
 277     struct kvm_msr_entry msrs[MSR_COUNT];
 278     uint32_t hflags;
 279     uint32_t i, n, rc;
 280
 281     kvm_get_regs(kvm_context, env->cpu_index, &regs);
 282
 283     env->regs[R_EAX] = regs.rax;
 284     env->regs[R_EBX] = regs.rbx;
 285     env->regs[R_ECX] = regs.rcx;
 286     env->regs[R_EDX] = regs.rdx;
 287     env->regs[R_ESI] = regs.rsi;
 288     env->regs[R_EDI] = regs.rdi;
 289     env->regs[R_ESP] = regs.rsp;
 290     env->regs[R_EBP] = regs.rbp;
 291 #ifdef TARGET_X86_64
 292     env->regs[8] = regs.r8;
 293     env->regs[9] = regs.r9;
 294     env->regs[10] = regs.r10;
 295     env->regs[11] = regs.r11;
 296     env->regs[12] = regs.r12;
 297     env->regs[13] = regs.r13;
 298     env->regs[14] = regs.r14;
 299     env->regs[15] = regs.r15;
 300 #endif
 301
 302     env->eflags = regs.rflags;
 303     env->eip = regs.rip;
 304
 305     kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
 306     env->fpstt = (fpu.fsw >> 11) & 7;
 307     env->fpus = fpu.fsw;
 308     env->fpuc = fpu.fcw;
 309     for (i = 0; i < 8; ++i)
 310         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 311     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 312     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 313     env->mxcsr = fpu.mxcsr;
 314
 315     kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
 316
 317     memcpy(env->kvm_interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->kvm_interrupt_bitmap));
 318
 319     get_seg(&env->segs[R_CS], &sregs.cs);
 320     get_seg(&env->segs[R_DS], &sregs.ds);
 321     get_seg(&env->segs[R_ES], &sregs.es);
 322     get_seg(&env->segs[R_FS], &sregs.fs);
 323     get_seg(&env->segs[R_GS], &sregs.gs);
 324     get_seg(&env->segs[R_SS], &sregs.ss);
 325
 326     get_seg(&env->tr, &sregs.tr);
 327     get_seg(&env->ldt, &sregs.ldt);
 328
 329     env->idt.limit = sregs.idt.limit;
 330     env->idt.base = sregs.idt.base;
 331     env->gdt.limit = sregs.gdt.limit;
 332     env->gdt.base = sregs.gdt.base;
 333
 334     env->cr[0] = sregs.cr0;
 335     env->cr[2] = sregs.cr2;
 336     env->cr[3] = sregs.cr3;
 337     env->cr[4] = sregs.cr4;
 338
 339     cpu_set_apic_base(env, sregs.apic_base);
 340
 341     env->efer = sregs.efer;
 342     //cpu_set_apic_tpr(env, sregs.cr8);
 343
 344 #define HFLAG_COPY_MASK ~( \
 345                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 346                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 347                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 348                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 349
 350
 351
 352     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 353     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 354     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 355             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 356     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 357     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 358             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 359
 360     if (env->efer & MSR_EFER_LMA) {
 361         hflags |= HF_LMA_MASK;
 362     }
 363
 364     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 365         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 366     } else {
 367         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 368                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 369         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 370                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 371         if (!(env->cr[0] & CR0_PE_MASK) ||
 372                    (env->eflags & VM_MASK) ||
 373                    !(hflags & HF_CS32_MASK)) {
 374                 hflags |= HF_ADDSEG_MASK;
 375             } else {
 376                 hflags |= ((env->segs[R_DS].base |
 377                                 env->segs[R_ES].base |
 378                                 env->segs[R_SS].base) != 0) <<
 379                     HF_ADDSEG_SHIFT;
 380             }
 381     }
 382     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 383     env->cc_src = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 384     env->df = 1 - (2 * ((env->eflags >> 10) & 1));
 385     env->cc_op = CC_OP_EFLAGS;
 386     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 387
 388     /* msrs */
 389     n = 0;
 390     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 391     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 392     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 393     if (kvm_has_msr_star)
 394         msrs[n++].index = MSR_STAR;
 395     msrs[n++].index = MSR_IA32_TSC;
 396 #ifdef TARGET_X86_64
 397     if (lm_capable_kernel) {
 398         msrs[n++].index = MSR_CSTAR;
 399         msrs[n++].index = MSR_KERNELGSBASE;
 400         msrs[n++].index = MSR_FMASK;
 401         msrs[n++].index = MSR_LSTAR;
 402     }
 403 #endif
 404     rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
 405     if (rc == -1) {
 406         perror("kvm_get_msrs FAILED");
 407     }
 408     else {
 409         n = rc; /* actual number of MSRs */
 410         for (i=0 ; i<n; i++) {
 411             if (get_msr_entry(&msrs[i], env))
 412                 return;
 413         }
 414     }
 415 }
 416
 417 static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
 418                        uint32_t *ecx, uint32_t *edx)
 419 {
 420     uint32_t vec[4];
 421
 422     vec[0] = function;
 423     asm volatile (
 424 #ifdef __x86_64__
 425          "sub $128, %%rsp \n\t"  /* skip red zone */
 426          "push %0;  push %%rsi \n\t"
 427          "push %%rax; push %%rbx; push %%rcx; push %%rdx \n\t"
 428          "mov 8*5(%%rsp), %%rsi \n\t"
 429          "mov (%%rsi), %%eax \n\t"
 430          "cpuid \n\t"
 431          "mov %%eax, (%%rsi) \n\t"
 432          "mov %%ebx, 4(%%rsi) \n\t"
 433          "mov %%ecx, 8(%%rsi) \n\t"
 434          "mov %%edx, 12(%%rsi) \n\t"
 435          "pop %%rdx; pop %%rcx; pop %%rbx; pop %%rax \n\t"
 436          "pop %%rsi; pop %0 \n\t"
 437          "add $128, %%rsp"
 438 #else
 439          "push %0;  push %%esi \n\t"
 440          "push %%eax; push %%ebx; push %%ecx; push %%edx \n\t"
 441          "mov 4*5(%%esp), %%esi \n\t"
 442          "mov (%%esi), %%eax \n\t"
 443          "cpuid \n\t"
 444          "mov %%eax, (%%esi) \n\t"
 445          "mov %%ebx, 4(%%esi) \n\t"
 446          "mov %%ecx, 8(%%esi) \n\t"
 447          "mov %%edx, 12(%%esi) \n\t"
 448          "pop %%edx; pop %%ecx; pop %%ebx; pop %%eax \n\t"
 449          "pop %%esi; pop %0 \n\t"
 450 #endif
 451          : : "rm"(vec) : "memory");
 452     if (eax)
 453         *eax = vec[0];
 454     if (ebx)
 455         *ebx = vec[1];
 456     if (ecx)
 457         *ecx = vec[2];
 458     if (edx)
 459         *edx = vec[3];
 460 }
 461
 462
 463 static void do_cpuid_ent(struct kvm_cpuid_entry *e, uint32_t function,
 464                          CPUState *env)
 465 {
 466     env->regs[R_EAX] = function;
 467     qemu_kvm_cpuid_on_env(env);
 468     e->function = function;
 469     e->eax = env->regs[R_EAX];
 470     e->ebx = env->regs[R_EBX];
 471     e->ecx = env->regs[R_ECX];
 472     e->edx = env->regs[R_EDX];
 473     if (function == 0x80000001) {
 474         uint32_t h_eax, h_edx;
 475
 476         host_cpuid(function, &h_eax, NULL, NULL, &h_edx);
 477
 478         // long mode
 479         if ((h_edx & 0x20000000) == 0 || !lm_capable_kernel)
 480             e->edx &= ~0x20000000u;
 481         // syscall
 482         if ((h_edx & 0x00000800) == 0)
 483             e->edx &= ~0x00000800u;
 484         // nx
 485         if ((h_edx & 0x00100000) == 0)
 486             e->edx &= ~0x00100000u;
 487         // svm
 488         if (e->ecx & 4)
 489             e->ecx &= ~4u;
 490     }
 491     // sysenter isn't supported on compatibility mode on AMD.  and syscall
 492     // isn't supported in compatibility mode on Intel.  so advertise the
 493     // actuall cpu, and say goodbye to migration between different vendors
 494     // is you use compatibility mode.
 495     if (function == 0) {
 496         uint32_t bcd[3];
 497
 498         host_cpuid(0, NULL, &bcd[0], &bcd[1], &bcd[2]);
 499         e->ebx = bcd[0];
 500         e->ecx = bcd[1];
 501         e->edx = bcd[2];
 502     }
 503 }
 504
 505 int kvm_arch_qemu_init_env(CPUState *cenv)
 506 {
 507     struct kvm_cpuid_entry cpuid_ent[100];
 508 #ifdef KVM_CPUID_SIGNATURE
 509     struct kvm_cpuid_entry *pv_ent;
 510     uint32_t signature[3];
 511 #endif
 512     int cpuid_nent = 0;
 513     CPUState copy;
 514     uint32_t i, limit;
 515
 516     copy = *cenv;
 517
 518 #ifdef KVM_CPUID_SIGNATURE
 519     /* Paravirtualization CPUIDs */
 520     memcpy(signature, "KVMKVMKVM", 12);
 521     pv_ent = &cpuid_ent[cpuid_nent++];
 522     memset(pv_ent, 0, sizeof(*pv_ent));
 523     pv_ent->function = KVM_CPUID_SIGNATURE;
 524     pv_ent->eax = 0;
 525     pv_ent->ebx = signature[0];
 526     pv_ent->ecx = signature[1];
 527     pv_ent->edx = signature[2];
 528
 529     pv_ent = &cpuid_ent[cpuid_nent++];
 530     memset(pv_ent, 0, sizeof(*pv_ent));
 531     pv_ent->function = KVM_CPUID_FEATURES;
 532     pv_ent->eax = 0;
 533 #endif
 534
 535     copy.regs[R_EAX] = 0;
 536     qemu_kvm_cpuid_on_env(&copy);
 537     limit = copy.regs[R_EAX];
 538
 539     for (i = 0; i <= limit; ++i)
 540         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 541
 542     copy.regs[R_EAX] = 0x80000000;
 543     qemu_kvm_cpuid_on_env(&copy);
 544     limit = copy.regs[R_EAX];
 545
 546     for (i = 0x80000000; i <= limit; ++i)
 547         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 548
 549     kvm_setup_cpuid(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
 550     return 0;
 551 }
 552
 553 int kvm_arch_halt(void *opaque, int vcpu)
 554 {
 555     CPUState *env = cpu_single_env;
 556
 557     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 558           (env->eflags & IF_MASK))) {
 559             env->hflags |= HF_HALTED_MASK;
 560             env->exception_index = EXCP_HLT;
 561     }
 562     return 1;
 563 }
 564
 565 void kvm_arch_pre_kvm_run(void *opaque, int vcpu)
 566 {
 567     CPUState *env = cpu_single_env;
 568
 569     if (!kvm_irqchip_in_kernel(kvm_context))
 570         kvm_set_cr8(kvm_context, vcpu, cpu_get_apic_tpr(env));
 571 }
 572
 573 void kvm_arch_post_kvm_run(void *opaque, int vcpu)
 574 {
 575     CPUState *env = qemu_kvm_cpu_env(vcpu);
 576     cpu_single_env = env;
 577
 578     env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
 579         ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
 580     env->ready_for_interrupt_injection
 581         = kvm_is_ready_for_interrupt_injection(kvm_context, vcpu);
 582
 583     cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
 584     cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
 585 }
 586
 587 int kvm_arch_has_work(CPUState *env)
 588 {
 589     if ((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
 590         (env->eflags & IF_MASK))
 591         return 1;
 592     return 0;
 593 }
 594
 595 int kvm_arch_try_push_interrupts(void *opaque)
 596 {
 597     CPUState *env = cpu_single_env;
 598     int r, irq;
 599
 600     if (env->ready_for_interrupt_injection &&
 601         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 602         (env->eflags & IF_MASK)) {
 603             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 604             irq = cpu_get_pic_interrupt(env);
 605             if (irq >= 0) {
 606                 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
 607                 if (r < 0)
 608                     printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 609             }
 610     }
 611
 612     return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
 613 }
 614
 615 void kvm_arch_update_regs_for_sipi(CPUState *env)
 616 {
 617     SegmentCache cs = env->segs[R_CS];
 618
 619     kvm_arch_save_regs(env);
 620     env->segs[R_CS] = cs;
 621     env->eip = 0;
 622     kvm_arch_load_regs(env);
 623 }
 624
 625 int handle_tpr_access(void *opaque, int vcpu,
 626                              uint64_t rip, int is_write)
 627 {
 628     kvm_tpr_access_report(cpu_single_env, rip, is_write);
 629     return 0;
 630 }