4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 pci_set_irq_fn set_irq
;
36 pci_map_irq_fn map_irq
;
37 uint32_t config_reg
; /* XXX: suppress */
39 SetIRQFunc
*low_set_irq
;
41 PCIDevice
*devices
[256];
42 PCIDevice
*parent_dev
;
44 /* The bus IRQ state is the logical OR of the connected devices.
45 Keep a count of the number of devices with raised IRQs. */
50 static void pci_update_mappings(PCIDevice
*d
);
51 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
53 target_phys_addr_t pci_mem_base
;
54 static int pci_irq_index
;
55 static PCIBus
*first_bus
;
57 static void pcibus_save(QEMUFile
*f
, void *opaque
)
59 PCIBus
*bus
= (PCIBus
*)opaque
;
62 qemu_put_be32(f
, bus
->nirq
);
63 for (i
= 0; i
< bus
->nirq
; i
++)
64 qemu_put_be32(f
, bus
->irq_count
[i
]);
67 static int pcibus_load(QEMUFile
*f
, void *opaque
, int version_id
)
69 PCIBus
*bus
= (PCIBus
*)opaque
;
75 nirq
= qemu_get_be32(f
);
76 if (bus
->nirq
!= nirq
) {
77 fprintf(stderr
, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
82 for (i
= 0; i
< nirq
; i
++)
83 bus
->irq_count
[i
] = qemu_get_be32(f
);
88 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
89 qemu_irq
*pic
, int devfn_min
, int nirq
)
94 bus
= qemu_mallocz(sizeof(PCIBus
) + (nirq
* sizeof(int)));
95 bus
->set_irq
= set_irq
;
96 bus
->map_irq
= map_irq
;
97 bus
->irq_opaque
= pic
;
98 bus
->devfn_min
= devfn_min
;
101 register_savevm("PCIBUS", nbus
++, 1, pcibus_save
, pcibus_load
, bus
);
105 static PCIBus
*pci_register_secondary_bus(PCIDevice
*dev
, pci_map_irq_fn map_irq
)
108 bus
= qemu_mallocz(sizeof(PCIBus
));
109 bus
->map_irq
= map_irq
;
110 bus
->parent_dev
= dev
;
111 bus
->next
= dev
->bus
->next
;
112 dev
->bus
->next
= bus
;
116 int pci_bus_num(PCIBus
*s
)
121 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
125 qemu_put_be32(f
, 2); /* PCI device version */
126 qemu_put_buffer(f
, s
->config
, 256);
127 for (i
= 0; i
< 4; i
++)
128 qemu_put_be32(f
, s
->irq_state
[i
]);
131 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
136 version_id
= qemu_get_be32(f
);
139 qemu_get_buffer(f
, s
->config
, 256);
140 pci_update_mappings(s
);
143 for (i
= 0; i
< 4; i
++)
144 s
->irq_state
[i
] = qemu_get_be32(f
);
149 /* -1 for devfn means auto assign */
150 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
151 int instance_size
, int devfn
,
152 PCIConfigReadFunc
*config_read
,
153 PCIConfigWriteFunc
*config_write
)
157 if (pci_irq_index
>= PCI_DEVICES_MAX
)
161 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
162 if (!bus
->devices
[devfn
])
168 pci_dev
= qemu_mallocz(instance_size
);
172 pci_dev
->devfn
= devfn
;
173 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
174 memset(pci_dev
->irq_state
, 0, sizeof(pci_dev
->irq_state
));
177 config_read
= pci_default_read_config
;
179 config_write
= pci_default_write_config
;
180 pci_dev
->config_read
= config_read
;
181 pci_dev
->config_write
= config_write
;
182 pci_dev
->irq_index
= pci_irq_index
++;
183 bus
->devices
[devfn
] = pci_dev
;
184 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, 4);
188 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
189 uint32_t size
, int type
,
190 PCIMapIORegionFunc
*map_func
)
195 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
197 r
= &pci_dev
->io_regions
[region_num
];
201 r
->map_func
= map_func
;
202 if (region_num
== PCI_ROM_SLOT
) {
205 addr
= 0x10 + region_num
* 4;
207 *(uint32_t *)(pci_dev
->config
+ addr
) = cpu_to_le32(type
);
210 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
212 return addr
+ pci_mem_base
;
215 static void pci_update_mappings(PCIDevice
*d
)
219 uint32_t last_addr
, new_addr
, config_ofs
;
221 cmd
= le16_to_cpu(*(uint16_t *)(d
->config
+ PCI_COMMAND
));
222 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
223 r
= &d
->io_regions
[i
];
224 if (i
== PCI_ROM_SLOT
) {
227 config_ofs
= 0x10 + i
* 4;
230 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
231 if (cmd
& PCI_COMMAND_IO
) {
232 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
234 new_addr
= new_addr
& ~(r
->size
- 1);
235 last_addr
= new_addr
+ r
->size
- 1;
236 /* NOTE: we have only 64K ioports on PC */
237 if (last_addr
<= new_addr
|| new_addr
== 0 ||
238 last_addr
>= 0x10000) {
245 if (cmd
& PCI_COMMAND_MEMORY
) {
246 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
248 /* the ROM slot has a specific enable bit */
249 if (i
== PCI_ROM_SLOT
&& !(new_addr
& 1))
251 new_addr
= new_addr
& ~(r
->size
- 1);
252 last_addr
= new_addr
+ r
->size
- 1;
253 /* NOTE: we do not support wrapping */
254 /* XXX: as we cannot support really dynamic
255 mappings, we handle specific values as invalid
257 if (last_addr
<= new_addr
|| new_addr
== 0 ||
266 /* now do the real mapping */
267 if (new_addr
!= r
->addr
) {
269 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
271 /* NOTE: specific hack for IDE in PC case:
272 only one byte must be mapped. */
273 class = d
->config
[0x0a] | (d
->config
[0x0b] << 8);
274 if (class == 0x0101 && r
->size
== 4) {
275 isa_unassign_ioport(r
->addr
+ 2, 1);
277 isa_unassign_ioport(r
->addr
, r
->size
);
280 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
287 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
294 uint32_t pci_default_read_config(PCIDevice
*d
,
295 uint32_t address
, int len
)
302 if (address
<= 0xfc) {
303 val
= le32_to_cpu(*(uint32_t *)(d
->config
+ address
));
308 if (address
<= 0xfe) {
309 val
= le16_to_cpu(*(uint16_t *)(d
->config
+ address
));
314 val
= d
->config
[address
];
320 void pci_default_write_config(PCIDevice
*d
,
321 uint32_t address
, uint32_t val
, int len
)
326 if (len
== 4 && ((address
>= 0x10 && address
< 0x10 + 4 * 6) ||
327 (address
>= 0x30 && address
< 0x34))) {
331 if ( address
>= 0x30 ) {
334 reg
= (address
- 0x10) >> 2;
336 r
= &d
->io_regions
[reg
];
339 /* compute the stored value */
340 if (reg
== PCI_ROM_SLOT
) {
341 /* keep ROM enable bit */
342 val
&= (~(r
->size
- 1)) | 1;
344 val
&= ~(r
->size
- 1);
347 *(uint32_t *)(d
->config
+ address
) = cpu_to_le32(val
);
348 pci_update_mappings(d
);
352 /* not efficient, but simple */
354 for(i
= 0; i
< len
; i
++) {
355 /* default read/write accesses */
356 switch(d
->config
[0x0e]) {
369 case 0x10 ... 0x27: /* base */
370 case 0x30 ... 0x33: /* rom */
391 case 0x38 ... 0x3b: /* rom */
402 d
->config
[addr
] = val
;
410 if (end
> PCI_COMMAND
&& address
< (PCI_COMMAND
+ 2)) {
411 /* if the command register is modified, we must modify the mappings */
412 pci_update_mappings(d
);
416 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
420 int config_addr
, bus_num
;
422 #if defined(DEBUG_PCI) && 0
423 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
426 bus_num
= (addr
>> 16) & 0xff;
427 while (s
&& s
->bus_num
!= bus_num
)
431 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
434 config_addr
= addr
& 0xff;
435 #if defined(DEBUG_PCI)
436 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
437 pci_dev
->name
, config_addr
, val
, len
);
439 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
442 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
446 int config_addr
, bus_num
;
449 bus_num
= (addr
>> 16) & 0xff;
450 while (s
&& s
->bus_num
!= bus_num
)
454 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
471 config_addr
= addr
& 0xff;
472 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
473 #if defined(DEBUG_PCI)
474 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
475 pci_dev
->name
, config_addr
, val
, len
);
478 #if defined(DEBUG_PCI) && 0
479 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
485 /***********************************************************/
486 /* generic PCI irq support */
488 /* 0 <= irq_num <= 3. level must be 0 or 1 */
489 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
491 PCIDevice
*pci_dev
= (PCIDevice
*)opaque
;
495 change
= level
- pci_dev
->irq_state
[irq_num
];
499 pci_dev
->irq_state
[irq_num
] = level
;
502 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
505 pci_dev
= bus
->parent_dev
;
507 bus
->irq_count
[irq_num
] += change
;
508 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
511 /***********************************************************/
512 /* monitor info on PCI */
519 static pci_class_desc pci_class_descriptions
[] =
521 { 0x0100, "SCSI controller"},
522 { 0x0101, "IDE controller"},
523 { 0x0102, "Floppy controller"},
524 { 0x0103, "IPI controller"},
525 { 0x0104, "RAID controller"},
526 { 0x0106, "SATA controller"},
527 { 0x0107, "SAS controller"},
528 { 0x0180, "Storage controller"},
529 { 0x0200, "Ethernet controller"},
530 { 0x0201, "Token Ring controller"},
531 { 0x0202, "FDDI controller"},
532 { 0x0203, "ATM controller"},
533 { 0x0280, "Network controller"},
534 { 0x0300, "VGA controller"},
535 { 0x0301, "XGA controller"},
536 { 0x0302, "3D controller"},
537 { 0x0380, "Display controller"},
538 { 0x0400, "Video controller"},
539 { 0x0401, "Audio controller"},
541 { 0x0480, "Multimedia controller"},
542 { 0x0500, "RAM controller"},
543 { 0x0501, "Flash controller"},
544 { 0x0580, "Memory controller"},
545 { 0x0600, "Host bridge"},
546 { 0x0601, "ISA bridge"},
547 { 0x0602, "EISA bridge"},
548 { 0x0603, "MC bridge"},
549 { 0x0604, "PCI bridge"},
550 { 0x0605, "PCMCIA bridge"},
551 { 0x0606, "NUBUS bridge"},
552 { 0x0607, "CARDBUS bridge"},
553 { 0x0608, "RACEWAY bridge"},
555 { 0x0c03, "USB controller"},
559 static void pci_info_device(PCIDevice
*d
)
563 pci_class_desc
*desc
;
565 term_printf(" Bus %2d, device %3d, function %d:\n",
566 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7);
567 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
569 desc
= pci_class_descriptions
;
570 while (desc
->desc
&& class != desc
->class)
573 term_printf("%s", desc
->desc
);
575 term_printf("Class %04x", class);
577 term_printf(": PCI device %04x:%04x\n",
578 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
579 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))));
581 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
582 term_printf(" IRQ %d.\n", d
->config
[PCI_INTERRUPT_LINE
]);
584 if (class == 0x0604) {
585 term_printf(" BUS %d.\n", d
->config
[0x19]);
587 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
588 r
= &d
->io_regions
[i
];
590 term_printf(" BAR%d: ", i
);
591 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
592 term_printf("I/O at 0x%04x [0x%04x].\n",
593 r
->addr
, r
->addr
+ r
->size
- 1);
595 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
596 r
->addr
, r
->addr
+ r
->size
- 1);
600 if (class == 0x0604 && d
->config
[0x19] != 0) {
601 pci_for_each_device(d
->config
[0x19], pci_info_device
);
605 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
))
607 PCIBus
*bus
= first_bus
;
611 while (bus
&& bus
->bus_num
!= bus_num
)
614 for(devfn
= 0; devfn
< 256; devfn
++) {
615 d
= bus
->devices
[devfn
];
624 pci_for_each_device(0, pci_info_device
);
627 /* Initialize a PCI NIC. */
628 void pci_nic_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
)
630 if (strcmp(nd
->model
, "ne2k_pci") == 0) {
631 pci_ne2000_init(bus
, nd
, devfn
);
632 } else if (strcmp(nd
->model
, "i82551") == 0) {
633 pci_i82551_init(bus
, nd
, devfn
);
634 } else if (strcmp(nd
->model
, "i82557b") == 0) {
635 pci_i82557b_init(bus
, nd
, devfn
);
636 } else if (strcmp(nd
->model
, "i82559er") == 0) {
637 pci_i82559er_init(bus
, nd
, devfn
);
638 } else if (strcmp(nd
->model
, "rtl8139") == 0) {
639 pci_rtl8139_init(bus
, nd
, devfn
);
640 } else if (strcmp(nd
->model
, "pcnet") == 0) {
641 pci_pcnet_init(bus
, nd
, devfn
);
642 } else if (strcmp(nd
->model
, "virtio") == 0) {
643 virtio_net_init(bus
, nd
, devfn
);
644 } else if (strcmp(nd
->model
, "?") == 0) {
645 fprintf(stderr
, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
646 " ne2k_pci pcnet rtl8139 virtio\n");
649 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd
->model
);
659 static void pci_bridge_write_config(PCIDevice
*d
,
660 uint32_t address
, uint32_t val
, int len
)
662 PCIBridge
*s
= (PCIBridge
*)d
;
664 if (address
== 0x19 || (address
== 0x18 && len
> 1)) {
666 s
->bus
->bus_num
= val
& 0xff;
668 s
->bus
->bus_num
= (val
>> 8) & 0xff;
669 #if defined(DEBUG_PCI)
670 printf ("pci-bridge: %s: Assigned bus %d\n", d
->name
, s
->bus
->bus_num
);
673 pci_default_write_config(d
, address
, val
, len
);
676 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint32_t id
,
677 pci_map_irq_fn map_irq
, const char *name
)
680 s
= (PCIBridge
*)pci_register_device(bus
, name
, sizeof(PCIBridge
),
681 devfn
, NULL
, pci_bridge_write_config
);
682 s
->dev
.config
[0x00] = id
>> 16;
683 s
->dev
.config
[0x01] = id
>> 24;
684 s
->dev
.config
[0x02] = id
; // device_id
685 s
->dev
.config
[0x03] = id
>> 8;
686 s
->dev
.config
[0x04] = 0x06; // command = bus master, pci mem
687 s
->dev
.config
[0x05] = 0x00;
688 s
->dev
.config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
689 s
->dev
.config
[0x07] = 0x00; // status = fast devsel
690 s
->dev
.config
[0x08] = 0x00; // revision
691 s
->dev
.config
[0x09] = 0x00; // programming i/f
692 s
->dev
.config
[0x0A] = 0x04; // class_sub = PCI to PCI bridge
693 s
->dev
.config
[0x0B] = 0x06; // class_base = PCI_bridge
694 s
->dev
.config
[0x0D] = 0x10; // latency_timer
695 s
->dev
.config
[0x0E] = 0x81; // header_type
696 s
->dev
.config
[0x1E] = 0xa0; // secondary status
698 s
->bus
= pci_register_secondary_bus(&s
->dev
, map_irq
);