hw/mips_timer.c

   1 #include "vl.h"
   2
   3 void cpu_mips_irqctrl_init (void)
   4 {
   5 }
   6
   7 /* XXX: do not use a global */
   8 uint32_t cpu_mips_get_random (CPUState *env)
   9 {
  10     static uint32_t seed = 0;
  11     uint32_t idx;
  12     seed = seed * 314159 + 1;
  13     idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
  14     return idx;
  15 }
  16
  17 /* MIPS R4K timer */
  18 uint32_t cpu_mips_get_count (CPUState *env)
  19 {
  20     return env->CP0_Count +
  21         (uint32_t)muldiv64(qemu_get_clock(vm_clock),
  22                            100 * 1000 * 1000, ticks_per_sec);
  23 }
  24
  25 static void cpu_mips_update_count (CPUState *env, uint32_t count,
  26                                    uint32_t compare)
  27 {
  28     uint64_t now, next;
  29     uint32_t tmp;
  30
  31     tmp = count;
  32     if (count == compare)
  33         tmp++;
  34     now = qemu_get_clock(vm_clock);
  35     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
  36     if (next == now)
  37         next++;
  38 #if 0
  39     if (logfile) {
  40         fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
  41                 __func__, now, count, compare, next - now);
  42     }
  43 #endif
  44     /* Store new count and compare registers */
  45     env->CP0_Compare = compare;
  46     env->CP0_Count =
  47         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
  48     /* Adjust timer */
  49     qemu_mod_timer(env->timer, next);
  50 }
  51
  52 void cpu_mips_store_count (CPUState *env, uint32_t value)
  53 {
  54     cpu_mips_update_count(env, value, env->CP0_Compare);
  55 }
  56
  57 void cpu_mips_store_compare (CPUState *env, uint32_t value)
  58 {
  59     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
  60     cpu_mips_irq_request(env, 7, 0);
  61 }
  62
  63 static void mips_timer_cb (void *opaque)
  64 {
  65     CPUState *env;
  66
  67     env = opaque;
  68 #if 0
  69     if (logfile) {
  70         fprintf(logfile, "%s\n", __func__);
  71     }
  72 #endif
  73     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
  74     cpu_mips_irq_request(env, 7, 1);
  75 }
  76
  77 void cpu_mips_clock_init (CPUState *env)
  78 {
  79     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
  80     env->CP0_Compare = 0;
  81     cpu_mips_update_count(env, 1, 0);
  82 }
  83
  84 #include "vl.h"
  85
  86 void cpu_mips_irqctrl_init (void)
  87 {
  88 }
  89
  90 /* XXX: do not use a global */
  91 uint32_t cpu_mips_get_random (CPUState *env)
  92 {
  93     static uint32_t seed = 0;
  94     uint32_t idx;
  95     seed = seed * 314159 + 1;
  96     idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
  97     return idx;
  98 }
  99
 100 /* MIPS R4K timer */
 101 uint32_t cpu_mips_get_count (CPUState *env)
 102 {
 103     return env->CP0_Count +
 104         (uint32_t)muldiv64(qemu_get_clock(vm_clock),
 105                            100 * 1000 * 1000, ticks_per_sec);
 106 }
 107
 108 static void cpu_mips_update_count (CPUState *env, uint32_t count,
 109                                    uint32_t compare)
 110 {
 111     uint64_t now, next;
 112     uint32_t tmp;
 113
 114     tmp = count;
 115     if (count == compare)
 116         tmp++;
 117     now = qemu_get_clock(vm_clock);
 118     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
 119     if (next == now)
 120         next++;
 121 #if 0
 122     if (logfile) {
 123         fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
 124                 __func__, now, count, compare, next - now);
 125     }
 126 #endif
 127     /* Store new count and compare registers */
 128     env->CP0_Compare = compare;
 129     env->CP0_Count =
 130         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
 131     /* Adjust timer */
 132     qemu_mod_timer(env->timer, next);
 133 }
 134
 135 void cpu_mips_store_count (CPUState *env, uint32_t value)
 136 {
 137     cpu_mips_update_count(env, value, env->CP0_Compare);
 138 }
 139
 140 void cpu_mips_store_compare (CPUState *env, uint32_t value)
 141 {
 142     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
 143     cpu_mips_irq_request(env, 7, 0);
 144 }
 145
 146 static void mips_timer_cb (void *opaque)
 147 {
 148     CPUState *env;
 149
 150     env = opaque;
 151 #if 0
 152     if (logfile) {
 153         fprintf(logfile, "%s\n", __func__);
 154     }
 155 #endif
 156     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
 157     cpu_mips_irq_request(env, 7, 1);
 158 }
 159
 160 void cpu_mips_clock_init (CPUState *env)
 161 {
 162     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
 163     env->CP0_Compare = 0;
 164     cpu_mips_update_count(env, 1, 0);
 165 }
 166