hw/mips_int.c

   1 #include "vl.h"
   2 #include "cpu.h"
   3
   4 /* Raise IRQ to CPU if necessary. It must be called every time the active
   5    IRQ may change */
   6 void cpu_mips_update_irq(CPUState *env)
   7 {
   8     if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
   9         (env->CP0_Status & (1 << CP0St_IE)) &&
  10         !(env->hflags & MIPS_HFLAG_EXL) &&
  11         !(env->hflags & MIPS_HFLAG_ERL) &&
  12         !(env->hflags & MIPS_HFLAG_DM)) {
  13         if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
  14             cpu_interrupt(env, CPU_INTERRUPT_HARD);
  15         }
  16     } else {
  17         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  18     }
  19 }
  20
  21 void cpu_mips_irq_request(void *opaque, int irq, int level)
  22 {
  23     CPUState *env = first_cpu;
  24
  25     uint32_t mask;
  26
  27     if (irq >= 16)
  28         return;
  29
  30     mask = 1 << (irq + CP0Ca_IP);
  31
  32     if (level) {
  33         env->CP0_Cause |= mask;
  34     } else {
  35         env->CP0_Cause &= ~mask;
  36     }
  37     cpu_mips_update_irq(env);
  38 }
  39
  40 #include "vl.h"
  41 #include "cpu.h"
  42
  43 /* Raise IRQ to CPU if necessary. It must be called every time the active
  44    IRQ may change */
  45 void cpu_mips_update_irq(CPUState *env)
  46 {
  47     if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
  48         (env->CP0_Status & (1 << CP0St_IE)) &&
  49         !(env->hflags & MIPS_HFLAG_EXL) &&
  50         !(env->hflags & MIPS_HFLAG_ERL) &&
  51         !(env->hflags & MIPS_HFLAG_DM)) {
  52         if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
  53             cpu_interrupt(env, CPU_INTERRUPT_HARD);
  54         }
  55     } else {
  56         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  57     }
  58 }
  59
  60 void cpu_mips_irq_request(void *opaque, int irq, int level)
  61 {
  62     CPUState *env = first_cpu;
  63
  64     uint32_t mask;
  65
  66     if (irq >= 16)
  67         return;
  68
  69     mask = 1 << (irq + CP0Ca_IP);
  70
  71     if (level) {
  72         env->CP0_Cause |= mask;
  73     } else {
  74         env->CP0_Cause &= ~mask;
  75     }
  76     cpu_mips_update_irq(env);
  77 }
  78