hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "qemu-timer.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "kvm.h"
  27 #include "qemu-kvm.h"
  28 #include "string.h"
  29
  30 //#define DEBUG
  31
  32 /* i82731AB (PIIX4) compatible power management function */
  33 #define PM_FREQ 3579545
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 typedef struct PIIX4PMState {
  38     PCIDevice dev;
  39     uint16_t pmsts;
  40     uint16_t pmen;
  41     uint16_t pmcntrl;
  42     uint8_t apmc;
  43     uint8_t apms;
  44     QEMUTimer *tmr_timer;
  45     int64_t tmr_overflow_time;
  46     i2c_bus *smbus;
  47     uint8_t smb_stat;
  48     uint8_t smb_ctl;
  49     uint8_t smb_cmd;
  50     uint8_t smb_addr;
  51     uint8_t smb_data0;
  52     uint8_t smb_data1;
  53     uint8_t smb_data[32];
  54     uint8_t smb_index;
  55     qemu_irq irq;
  56 } PIIX4PMState;
  57
  58 #define RTC_EN (1 << 10)
  59 #define PWRBTN_EN (1 << 8)
  60 #define GBL_EN (1 << 5)
  61 #define TMROF_EN (1 << 0)
  62
  63 #define SCI_EN (1 << 0)
  64
  65 #define SUS_EN (1 << 13)
  66
  67 #define ACPI_ENABLE 0xf1
  68 #define ACPI_DISABLE 0xf0
  69
  70 #define SMBHSTSTS 0x00
  71 #define SMBHSTCNT 0x02
  72 #define SMBHSTCMD 0x03
  73 #define SMBHSTADD 0x04
  74 #define SMBHSTDAT0 0x05
  75 #define SMBHSTDAT1 0x06
  76 #define SMBBLKDAT 0x07
  77
  78 static PIIX4PMState *pm_state;
  79
  80 static uint32_t get_pmtmr(PIIX4PMState *s)
  81 {
  82     uint32_t d;
  83     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  84     return d & 0xffffff;
  85 }
  86
  87 static int get_pmsts(PIIX4PMState *s)
  88 {
  89     int64_t d;
  90     int pmsts;
  91     pmsts = s->pmsts;
  92     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  93     if (d >= s->tmr_overflow_time)
  94         s->pmsts |= TMROF_EN;
  95     return pmsts;
  96 }
  97
  98 static void pm_update_sci(PIIX4PMState *s)
  99 {
 100     int sci_level, pmsts;
 101     int64_t expire_time;
 102
 103     pmsts = get_pmsts(s);
 104     sci_level = (((pmsts & s->pmen) &
 105                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 106     qemu_set_irq(s->irq, sci_level);
 107     /* schedule a timer interruption if needed */
 108     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 109         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 110         qemu_mod_timer(s->tmr_timer, expire_time);
 111     } else {
 112         qemu_del_timer(s->tmr_timer);
 113     }
 114 }
 115
 116 static void pm_tmr_timer(void *opaque)
 117 {
 118     PIIX4PMState *s = opaque;
 119     pm_update_sci(s);
 120 }
 121
 122 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 123 {
 124     PIIX4PMState *s = opaque;
 125     addr &= 0x3f;
 126     switch(addr) {
 127     case 0x00:
 128         {
 129             int64_t d;
 130             int pmsts;
 131             pmsts = get_pmsts(s);
 132             if (pmsts & val & TMROF_EN) {
 133                 /* if TMRSTS is reset, then compute the new overflow time */
 134                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 135                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 136             }
 137             s->pmsts &= ~val;
 138             pm_update_sci(s);
 139         }
 140         break;
 141     case 0x02:
 142         s->pmen = val;
 143         pm_update_sci(s);
 144         break;
 145     case 0x04:
 146         {
 147             int sus_typ;
 148             s->pmcntrl = val & ~(SUS_EN);
 149             if (val & SUS_EN) {
 150                 /* change suspend type */
 151                 sus_typ = (val >> 10) & 7;
 152                 switch(sus_typ) {
 153                 case 0: /* soft power off */
 154                     qemu_system_shutdown_request();
 155                     break;
 156                 default:
 157                     break;
 158                 }
 159             }
 160         }
 161         break;
 162     default:
 163         break;
 164     }
 165 #ifdef DEBUG
 166     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 167 #endif
 168 }
 169
 170 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 171 {
 172     PIIX4PMState *s = opaque;
 173     uint32_t val;
 174
 175     addr &= 0x3f;
 176     switch(addr) {
 177     case 0x00:
 178         val = get_pmsts(s);
 179         break;
 180     case 0x02:
 181         val = s->pmen;
 182         break;
 183     case 0x04:
 184         val = s->pmcntrl;
 185         break;
 186     default:
 187         val = 0;
 188         break;
 189     }
 190 #ifdef DEBUG
 191     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 192 #endif
 193     return val;
 194 }
 195
 196 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 197 {
 198     //    PIIX4PMState *s = opaque;
 199     addr &= 0x3f;
 200 #ifdef DEBUG
 201     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 202 #endif
 203 }
 204
 205 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 206 {
 207     PIIX4PMState *s = opaque;
 208     uint32_t val;
 209
 210     addr &= 0x3f;
 211     switch(addr) {
 212     case 0x08:
 213         val = get_pmtmr(s);
 214         break;
 215     default:
 216         val = 0;
 217         break;
 218     }
 219 #ifdef DEBUG
 220     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 221 #endif
 222     return val;
 223 }
 224
 225 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 226 {
 227     PIIX4PMState *s = opaque;
 228     addr &= 1;
 229 #ifdef DEBUG
 230     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 231 #endif
 232     if (addr == 0) {
 233         s->apmc = val;
 234
 235         /* ACPI specs 3.0, 4.7.2.5 */
 236         if (val == ACPI_ENABLE) {
 237             s->pmcntrl |= SCI_EN;
 238         } else if (val == ACPI_DISABLE) {
 239             s->pmcntrl &= ~SCI_EN;
 240         }
 241
 242         if (s->dev.config[0x5b] & (1 << 1)) {
 243             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 244         }
 245     } else {
 246         s->apms = val;
 247     }
 248 }
 249
 250 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 251 {
 252     PIIX4PMState *s = opaque;
 253     uint32_t val;
 254
 255     addr &= 1;
 256     if (addr == 0) {
 257         val = s->apmc;
 258     } else {
 259         val = s->apms;
 260     }
 261 #ifdef DEBUG
 262     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 263 #endif
 264     return val;
 265 }
 266
 267 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 268 {
 269 #if defined(DEBUG)
 270     printf("ACPI: DBG: 0x%08x\n", val);
 271 #endif
 272 }
 273
 274 static void smb_transaction(PIIX4PMState *s)
 275 {
 276     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 277     uint8_t read = s->smb_addr & 0x01;
 278     uint8_t cmd = s->smb_cmd;
 279     uint8_t addr = s->smb_addr >> 1;
 280     i2c_bus *bus = s->smbus;
 281
 282 #ifdef DEBUG
 283     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 284 #endif
 285     switch(prot) {
 286     case 0x0:
 287         smbus_quick_command(bus, addr, read);
 288         break;
 289     case 0x1:
 290         if (read) {
 291             s->smb_data0 = smbus_receive_byte(bus, addr);
 292         } else {
 293             smbus_send_byte(bus, addr, cmd);
 294         }
 295         break;
 296     case 0x2:
 297         if (read) {
 298             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 299         } else {
 300             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 301         }
 302         break;
 303     case 0x3:
 304         if (read) {
 305             uint16_t val;
 306             val = smbus_read_word(bus, addr, cmd);
 307             s->smb_data0 = val;
 308             s->smb_data1 = val >> 8;
 309         } else {
 310             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 311         }
 312         break;
 313     case 0x5:
 314         if (read) {
 315             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 316         } else {
 317             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 318         }
 319         break;
 320     default:
 321         goto error;
 322     }
 323     return;
 324
 325   error:
 326     s->smb_stat |= 0x04;
 327 }
 328
 329 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 330 {
 331     PIIX4PMState *s = opaque;
 332     addr &= 0x3f;
 333 #ifdef DEBUG
 334     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 335 #endif
 336     switch(addr) {
 337     case SMBHSTSTS:
 338         s->smb_stat = 0;
 339         s->smb_index = 0;
 340         break;
 341     case SMBHSTCNT:
 342         s->smb_ctl = val;
 343         if (val & 0x40)
 344             smb_transaction(s);
 345         break;
 346     case SMBHSTCMD:
 347         s->smb_cmd = val;
 348         break;
 349     case SMBHSTADD:
 350         s->smb_addr = val;
 351         break;
 352     case SMBHSTDAT0:
 353         s->smb_data0 = val;
 354         break;
 355     case SMBHSTDAT1:
 356         s->smb_data1 = val;
 357         break;
 358     case SMBBLKDAT:
 359         s->smb_data[s->smb_index++] = val;
 360         if (s->smb_index > 31)
 361             s->smb_index = 0;
 362         break;
 363     default:
 364         break;
 365     }
 366 }
 367
 368 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 369 {
 370     PIIX4PMState *s = opaque;
 371     uint32_t val;
 372
 373     addr &= 0x3f;
 374     switch(addr) {
 375     case SMBHSTSTS:
 376         val = s->smb_stat;
 377         break;
 378     case SMBHSTCNT:
 379         s->smb_index = 0;
 380         val = s->smb_ctl & 0x1f;
 381         break;
 382     case SMBHSTCMD:
 383         val = s->smb_cmd;
 384         break;
 385     case SMBHSTADD:
 386         val = s->smb_addr;
 387         break;
 388     case SMBHSTDAT0:
 389         val = s->smb_data0;
 390         break;
 391     case SMBHSTDAT1:
 392         val = s->smb_data1;
 393         break;
 394     case SMBBLKDAT:
 395         val = s->smb_data[s->smb_index++];
 396         if (s->smb_index > 31)
 397             s->smb_index = 0;
 398         break;
 399     default:
 400         val = 0;
 401         break;
 402     }
 403 #ifdef DEBUG
 404     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 405 #endif
 406     return val;
 407 }
 408
 409 static void pm_io_space_update(PIIX4PMState *s)
 410 {
 411     uint32_t pm_io_base;
 412
 413     if (s->dev.config[0x80] & 1) {
 414         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 415         pm_io_base &= 0xffc0;
 416
 417         /* XXX: need to improve memory and ioport allocation */
 418 #if defined(DEBUG)
 419         printf("PM: mapping to 0x%x\n", pm_io_base);
 420 #endif
 421         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 422         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 423         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 424         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 425     }
 426 }
 427
 428 static void pm_write_config(PCIDevice *d,
 429                             uint32_t address, uint32_t val, int len)
 430 {
 431     pci_default_write_config(d, address, val, len);
 432     if (address == 0x80)
 433         pm_io_space_update((PIIX4PMState *)d);
 434 }
 435
 436 static void pm_save(QEMUFile* f,void *opaque)
 437 {
 438     PIIX4PMState *s = opaque;
 439
 440     pci_device_save(&s->dev, f);
 441
 442     qemu_put_be16s(f, &s->pmsts);
 443     qemu_put_be16s(f, &s->pmen);
 444     qemu_put_be16s(f, &s->pmcntrl);
 445     qemu_put_8s(f, &s->apmc);
 446     qemu_put_8s(f, &s->apms);
 447     qemu_put_timer(f, s->tmr_timer);
 448     qemu_put_be64(f, s->tmr_overflow_time);
 449 }
 450
 451 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 452 {
 453     PIIX4PMState *s = opaque;
 454     int ret;
 455
 456     if (version_id > 1)
 457         return -EINVAL;
 458
 459     ret = pci_device_load(&s->dev, f);
 460     if (ret < 0)
 461         return ret;
 462
 463     qemu_get_be16s(f, &s->pmsts);
 464     qemu_get_be16s(f, &s->pmen);
 465     qemu_get_be16s(f, &s->pmcntrl);
 466     qemu_get_8s(f, &s->apmc);
 467     qemu_get_8s(f, &s->apms);
 468     qemu_get_timer(f, s->tmr_timer);
 469     s->tmr_overflow_time=qemu_get_be64(f);
 470
 471     pm_io_space_update(s);
 472
 473     return 0;
 474 }
 475
 476 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 477                        qemu_irq sci_irq)
 478 {
 479     PIIX4PMState *s;
 480     uint8_t *pci_conf;
 481
 482     s = (PIIX4PMState *)pci_register_device(bus,
 483                                          "PM", sizeof(PIIX4PMState),
 484                                          devfn, NULL, pm_write_config);
 485     pm_state = s;
 486     pci_conf = s->dev.config;
 487     pci_conf[0x00] = 0x86;
 488     pci_conf[0x01] = 0x80;
 489     pci_conf[0x02] = 0x13;
 490     pci_conf[0x03] = 0x71;
 491     pci_conf[0x06] = 0x80;
 492     pci_conf[0x07] = 0x02;
 493     pci_conf[0x08] = 0x03; // revision number
 494     pci_conf[0x09] = 0x00;
 495     pci_conf[0x0a] = 0x80; // other bridge device
 496     pci_conf[0x0b] = 0x06; // bridge device
 497     pci_conf[0x0e] = 0x00; // header_type
 498     pci_conf[0x3d] = 0x01; // interrupt pin 1
 499
 500     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 501
 502 #if defined(TARGET_IA64)
 503     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 504     pci_conf[0x41] = 0x1f;
 505     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 506     s->pmcntrl = SCI_EN;
 507 #endif
 508
 509     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 510     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 511
 512     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 513
 514     if (kvm_enabled()) {
 515         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 516          * support SMM mode. */
 517         pci_conf[0x5B] = 0x02;
 518     }
 519
 520     /* XXX: which specification is used ? The i82731AB has different
 521        mappings */
 522     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 523     pci_conf[0x63] = 0x60;
 524     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 525         (serial_hds[1] != NULL ? 0x90 : 0);
 526
 527     pci_conf[0x90] = smb_io_base | 1;
 528     pci_conf[0x91] = smb_io_base >> 8;
 529     pci_conf[0xd2] = 0x09;
 530     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 531     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 532
 533     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 534
 535     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 536
 537     s->smbus = i2c_init_bus();
 538     s->irq = sci_irq;
 539     return s->smbus;
 540 }
 541
 542 #if defined(TARGET_I386)
 543 void qemu_system_powerdown(void)
 544 {
 545     if (!pm_state) {
 546         qemu_system_shutdown_request();
 547     } else if (pm_state->pmen & PWRBTN_EN) {
 548         pm_state->pmsts |= PWRBTN_EN;
 549         pm_update_sci(pm_state);
 550     }
 551 }
 552 #endif
 553 #define GPE_BASE 0xafe0
 554 #define PROC_BASE 0xaf00
 555 #define PCI_BASE 0xae00
 556 #define PCI_EJ_BASE 0xae08
 557
 558 struct gpe_regs {
 559     uint16_t sts; /* status */
 560     uint16_t en;  /* enabled */
 561     uint8_t up;
 562     uint8_t down;
 563 };
 564
 565 struct pci_status {
 566     uint32_t up;
 567     uint32_t down;
 568 };
 569
 570 static struct gpe_regs gpe;
 571 static struct pci_status pci0_status;
 572
 573 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 574 {
 575     uint32_t val = 0;
 576     struct gpe_regs *g = opaque;
 577     switch (addr) {
 578         case PROC_BASE:
 579             val = g->up;
 580             break;
 581         case PROC_BASE + 1:
 582             val = g->down;
 583             break;
 584
 585         case GPE_BASE:
 586             val = g->sts & 0xFF;
 587             break;
 588         case GPE_BASE + 1:
 589             val =  (g->sts >> 8) & 0xFF;
 590             break;
 591         case GPE_BASE + 2:
 592             val =  g->en & 0xFF;
 593             break;
 594         case GPE_BASE + 3:
 595             val =  (g->en >> 8) & 0xFF;
 596             break;
 597         default:
 598             break;
 599     }
 600
 601 #if defined(DEBUG)
 602     printf("gpe read %x == %x\n", addr, val);
 603 #endif
 604     return val;
 605 }
 606
 607 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 608 {
 609     struct gpe_regs *g = opaque;
 610     switch (addr) {
 611         case PROC_BASE:
 612             g->up = val;
 613             break;
 614         case PROC_BASE + 1:
 615             g->down = val;
 616             break;
 617
 618         case GPE_BASE:
 619             g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
 620             break;
 621         case GPE_BASE + 1:
 622             g->sts = (g->sts & 0xFFFF) | (val << 8);
 623             break;
 624         case GPE_BASE + 2:
 625             g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
 626             break;
 627         case GPE_BASE + 3:
 628             g->en = (g->en & 0xFFFF) | (val << 8);
 629             break;
 630         default:
 631             break;
 632    }
 633
 634 #if defined(DEBUG)
 635     printf("gpe write %x <== %d\n", addr, val);
 636 #endif
 637 }
 638
 639 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 640 {
 641     uint32_t val = 0;
 642     struct pci_status *g = opaque;
 643     switch (addr) {
 644         case PCI_BASE:
 645             val = g->up;
 646             break;
 647         case PCI_BASE + 4:
 648             val = g->down;
 649             break;
 650         default:
 651             break;
 652     }
 653
 654 #if defined(DEBUG)
 655     printf("pcihotplug read %x == %x\n", addr, val);
 656 #endif
 657     return val;
 658 }
 659
 660 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 661 {
 662     struct pci_status *g = opaque;
 663     switch (addr) {
 664         case PCI_BASE:
 665             g->up = val;
 666             break;
 667         case PCI_BASE + 4:
 668             g->down = val;
 669             break;
 670    }
 671
 672 #if defined(DEBUG)
 673     printf("pcihotplug write %x <== %d\n", addr, val);
 674 #endif
 675 }
 676
 677 static uint32_t pciej_read(void *opaque, uint32_t addr)
 678 {
 679 #if defined(DEBUG)
 680     printf("pciej read %x\n", addr);
 681 #endif
 682     return 0;
 683 }
 684
 685 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 686 {
 687     int slot = ffs(val) - 1;
 688
 689     device_hot_remove_success(0, slot);
 690
 691 #if defined(DEBUG)
 692     printf("pciej write %x <== %d\n", addr, val);
 693 #endif
 694 }
 695
 696 static const char *model;
 697
 698 void qemu_system_hot_add_init(const char *cpu_model)
 699 {
 700     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 701     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 702
 703     register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe);
 704     register_ioport_read(PROC_BASE, 4, 1,  gpe_readb, &gpe);
 705
 706     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 707     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 708
 709     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
 710     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 711
 712     model = cpu_model;
 713 }
 714
 715 static void enable_processor(struct gpe_regs *g, int cpu)
 716 {
 717     g->sts |= 1;
 718     g->en |= 1;
 719     g->up |= (1 << cpu);
 720 }
 721
 722 static void disable_processor(struct gpe_regs *g, int cpu)
 723 {
 724     g->sts |= 1;
 725     g->en |= 1;
 726     g->down |= (1 << cpu);
 727 }
 728
 729 #if defined(TARGET_I386) || defined(TARGET_X86_64)
 730 #ifdef USE_KVM
 731 static CPUState *qemu_kvm_cpu_env(int index)
 732 {
 733     CPUState *penv;
 734
 735     penv = first_cpu;
 736
 737     while (penv) {
 738         if (penv->cpu_index == index)
 739             return penv;
 740         penv = (CPUState *)penv->next_cpu;
 741     }
 742
 743     return NULL;
 744 }
 745 #endif
 746
 747
 748 void qemu_system_cpu_hot_add(int cpu, int state)
 749 {
 750     CPUState *env;
 751
 752     if (state
 753 #ifdef USE_KVM
 754         && (!qemu_kvm_cpu_env(cpu))
 755 #endif
 756     ) {
 757         env = pc_new_cpu(cpu, model, 1);
 758         if (!env) {
 759             fprintf(stderr, "cpu %d creation failed\n", cpu);
 760             return;
 761         }
 762 #ifdef USE_KVM
 763         kvm_init_vcpu(env);
 764 #endif
 765     }
 766
 767     qemu_set_irq(pm_state->irq, 1);
 768     gpe.up = 0;
 769     gpe.down = 0;
 770     if (state)
 771         enable_processor(&gpe, cpu);
 772     else
 773         disable_processor(&gpe, cpu);
 774     qemu_set_irq(pm_state->irq, 0);
 775 }
 776 #endif
 777
 778 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 779 {
 780     g->sts |= 2;
 781     g->en |= 2;
 782     p->up |= (1 << slot);
 783 }
 784
 785 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 786 {
 787     g->sts |= 2;
 788     g->en |= 2;
 789     p->down |= (1 << slot);
 790 }
 791
 792 void qemu_system_device_hot_add(int pcibus, int slot, int state)
 793 {
 794     qemu_set_irq(pm_state->irq, 1);
 795     pci0_status.up = 0;
 796     pci0_status.down = 0;
 797     if (state)
 798         enable_device(&pci0_status, &gpe, slot);
 799     else
 800         disable_device(&pci0_status, &gpe, slot);
 801     qemu_set_irq(pm_state->irq, 0);
 802 }