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Pci hotplug GPE support
[qemu-kvm/fedora.git] / hw / omap.c
blob854198e0907e1eaebeac8b89edd527cf4b993fbf
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 /* We use pc-style serial ports. */
27 #include "pc.h"
28
29 /* Should signal the TCMI */
30 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
31 {
32 uint8_t ret;
33
34 OMAP_8B_REG(addr);
35 cpu_physical_memory_read(addr, (void *) &ret, 1);
36 return ret;
37 }
38
39 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
40 uint32_t value)
41 {
42 uint8_t val8 = value;
43
44 OMAP_8B_REG(addr);
45 cpu_physical_memory_write(addr, (void *) &val8, 1);
46 }
47
48 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
49 {
50 uint16_t ret;
51
52 OMAP_16B_REG(addr);
53 cpu_physical_memory_read(addr, (void *) &ret, 2);
54 return ret;
55 }
56
57 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
58 uint32_t value)
59 {
60 uint16_t val16 = value;
61
62 OMAP_16B_REG(addr);
63 cpu_physical_memory_write(addr, (void *) &val16, 2);
64 }
65
66 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
67 {
68 uint32_t ret;
69
70 OMAP_32B_REG(addr);
71 cpu_physical_memory_read(addr, (void *) &ret, 4);
72 return ret;
73 }
74
75 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
76 uint32_t value)
77 {
78 OMAP_32B_REG(addr);
79 cpu_physical_memory_write(addr, (void *) &value, 4);
80 }
81
82 /* Interrupt Handlers */
83 struct omap_intr_handler_bank_s {
84 uint32_t irqs;
85 uint32_t inputs;
86 uint32_t mask;
87 uint32_t fiq;
88 uint32_t sens_edge;
89 unsigned char priority[32];
90 };
91
92 struct omap_intr_handler_s {
93 qemu_irq *pins;
94 qemu_irq parent_intr[2];
95 target_phys_addr_t base;
96 unsigned char nbanks;
97
98 /* state */
99 uint32_t new_agr[2];
100 int sir_intr[2];
101 struct omap_intr_handler_bank_s banks[];
102 };
103
104 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
105 {
106 int i, j, sir_intr, p_intr, p, f;
107 uint32_t level;
108 sir_intr = 0;
109 p_intr = 255;
110
111 /* Find the interrupt line with the highest dynamic priority.
112 * Note: 0 denotes the hightest priority.
113 * If all interrupts have the same priority, the default order is IRQ_N,
114 * IRQ_N-1,...,IRQ_0. */
115 for (j = 0; j < s->nbanks; ++j) {
116 level = s->banks[j].irqs & ~s->banks[j].mask &
117 (is_fiq ? s->banks[j].fiq : ~s->banks[j].fiq);
118 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
119 level >>= f) {
120 p = s->banks[j].priority[i];
121 if (p <= p_intr) {
122 p_intr = p;
123 sir_intr = 32 * j + i;
124 }
125 f = ffs(level >> 1);
126 }
127 }
128 s->sir_intr[is_fiq] = sir_intr;
129 }
130
131 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
132 {
133 int i;
134 uint32_t has_intr = 0;
135
136 for (i = 0; i < s->nbanks; ++i)
137 has_intr |= s->banks[i].irqs & ~s->banks[i].mask &
138 (is_fiq ? s->banks[i].fiq : ~s->banks[i].fiq);
139
140 if (s->new_agr[is_fiq] && has_intr) {
141 s->new_agr[is_fiq] = 0;
142 omap_inth_sir_update(s, is_fiq);
143 qemu_set_irq(s->parent_intr[is_fiq], 1);
144 }
145 }
146
147 #define INT_FALLING_EDGE 0
148 #define INT_LOW_LEVEL 1
149
150 static void omap_set_intr(void *opaque, int irq, int req)
151 {
152 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
153 uint32_t rise;
154
155 struct omap_intr_handler_bank_s *bank = &ih->banks[irq >> 5];
156 int n = irq & 31;
157
158 if (req) {
159 rise = ~bank->irqs & (1 << n);
160 if (~bank->sens_edge & (1 << n))
161 rise &= ~bank->inputs & (1 << n);
162
163 bank->inputs |= (1 << n);
164 if (rise) {
165 bank->irqs |= rise;
166 omap_inth_update(ih, 0);
167 omap_inth_update(ih, 1);
168 }
169 } else {
170 rise = bank->sens_edge & bank->irqs & (1 << n);
171 bank->irqs &= ~rise;
172 bank->inputs &= ~(1 << n);
173 }
174 }
175
176 static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
177 {
178 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
179 int i, offset = addr - s->base;
180 int bank_no = offset >> 8;
181 int line_no;
182 struct omap_intr_handler_bank_s *bank = &s->banks[bank_no];
183 offset &= 0xff;
184
185 switch (offset) {
186 case 0x00: /* ITR */
187 return bank->irqs;
188
189 case 0x04: /* MIR */
190 return bank->mask;
191
192 case 0x10: /* SIR_IRQ_CODE */
193 case 0x14: /* SIR_FIQ_CODE */
194 if (bank_no != 0)
195 break;
196 line_no = s->sir_intr[(offset - 0x10) >> 2];
197 bank = &s->banks[line_no >> 5];
198 i = line_no & 31;
199 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
200 bank->irqs &= ~(1 << i);
201 return line_no;
202
203 case 0x18: /* CONTROL_REG */
204 if (bank_no != 0)
205 break;
206 return 0;
207
208 case 0x1c: /* ILR0 */
209 case 0x20: /* ILR1 */
210 case 0x24: /* ILR2 */
211 case 0x28: /* ILR3 */
212 case 0x2c: /* ILR4 */
213 case 0x30: /* ILR5 */
214 case 0x34: /* ILR6 */
215 case 0x38: /* ILR7 */
216 case 0x3c: /* ILR8 */
217 case 0x40: /* ILR9 */
218 case 0x44: /* ILR10 */
219 case 0x48: /* ILR11 */
220 case 0x4c: /* ILR12 */
221 case 0x50: /* ILR13 */
222 case 0x54: /* ILR14 */
223 case 0x58: /* ILR15 */
224 case 0x5c: /* ILR16 */
225 case 0x60: /* ILR17 */
226 case 0x64: /* ILR18 */
227 case 0x68: /* ILR19 */
228 case 0x6c: /* ILR20 */
229 case 0x70: /* ILR21 */
230 case 0x74: /* ILR22 */
231 case 0x78: /* ILR23 */
232 case 0x7c: /* ILR24 */
233 case 0x80: /* ILR25 */
234 case 0x84: /* ILR26 */
235 case 0x88: /* ILR27 */
236 case 0x8c: /* ILR28 */
237 case 0x90: /* ILR29 */
238 case 0x94: /* ILR30 */
239 case 0x98: /* ILR31 */
240 i = (offset - 0x1c) >> 2;
241 return (bank->priority[i] << 2) |
242 (((bank->sens_edge >> i) & 1) << 1) |
243 ((bank->fiq >> i) & 1);
244
245 case 0x9c: /* ISR */
246 return 0x00000000;
247
248 }
249 OMAP_BAD_REG(addr);
250 return 0;
251 }
252
253 static void omap_inth_write(void *opaque, target_phys_addr_t addr,
254 uint32_t value)
255 {
256 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
257 int i, offset = addr - s->base;
258 int bank_no = offset >> 8;
259 struct omap_intr_handler_bank_s *bank = &s->banks[bank_no];
260 offset &= 0xff;
261
262 switch (offset) {
263 case 0x00: /* ITR */
264 /* Important: ignore the clearing if the IRQ is level-triggered and
265 the input bit is 1 */
266 bank->irqs &= value | (bank->inputs & bank->sens_edge);
267 return;
268
269 case 0x04: /* MIR */
270 bank->mask = value;
271 omap_inth_update(s, 0);
272 omap_inth_update(s, 1);
273 return;
274
275 case 0x10: /* SIR_IRQ_CODE */
276 case 0x14: /* SIR_FIQ_CODE */
277 OMAP_RO_REG(addr);
278 break;
279
280 case 0x18: /* CONTROL_REG */
281 if (bank_no != 0)
282 break;
283 if (value & 2) {
284 qemu_set_irq(s->parent_intr[1], 0);
285 s->new_agr[1] = ~0;
286 omap_inth_update(s, 1);
287 }
288 if (value & 1) {
289 qemu_set_irq(s->parent_intr[0], 0);
290 s->new_agr[0] = ~0;
291 omap_inth_update(s, 0);
292 }
293 return;
294
295 case 0x1c: /* ILR0 */
296 case 0x20: /* ILR1 */
297 case 0x24: /* ILR2 */
298 case 0x28: /* ILR3 */
299 case 0x2c: /* ILR4 */
300 case 0x30: /* ILR5 */
301 case 0x34: /* ILR6 */
302 case 0x38: /* ILR7 */
303 case 0x3c: /* ILR8 */
304 case 0x40: /* ILR9 */
305 case 0x44: /* ILR10 */
306 case 0x48: /* ILR11 */
307 case 0x4c: /* ILR12 */
308 case 0x50: /* ILR13 */
309 case 0x54: /* ILR14 */
310 case 0x58: /* ILR15 */
311 case 0x5c: /* ILR16 */
312 case 0x60: /* ILR17 */
313 case 0x64: /* ILR18 */
314 case 0x68: /* ILR19 */
315 case 0x6c: /* ILR20 */
316 case 0x70: /* ILR21 */
317 case 0x74: /* ILR22 */
318 case 0x78: /* ILR23 */
319 case 0x7c: /* ILR24 */
320 case 0x80: /* ILR25 */
321 case 0x84: /* ILR26 */
322 case 0x88: /* ILR27 */
323 case 0x8c: /* ILR28 */
324 case 0x90: /* ILR29 */
325 case 0x94: /* ILR30 */
326 case 0x98: /* ILR31 */
327 i = (offset - 0x1c) >> 2;
328 bank->priority[i] = (value >> 2) & 0x1f;
329 bank->sens_edge &= ~(1 << i);
330 bank->sens_edge |= ((value >> 1) & 1) << i;
331 bank->fiq &= ~(1 << i);
332 bank->fiq |= (value & 1) << i;
333 return;
334
335 case 0x9c: /* ISR */
336 for (i = 0; i < 32; i ++)
337 if (value & (1 << i)) {
338 omap_set_intr(s, 32 * bank_no + i, 1);
339 return;
340 }
341 return;
342 }
343 OMAP_BAD_REG(addr);
344 }
345
346 static CPUReadMemoryFunc *omap_inth_readfn[] = {
347 omap_badwidth_read32,
348 omap_badwidth_read32,
349 omap_inth_read,
350 };
351
352 static CPUWriteMemoryFunc *omap_inth_writefn[] = {
353 omap_inth_write,
354 omap_inth_write,
355 omap_inth_write,
356 };
357
358 void omap_inth_reset(struct omap_intr_handler_s *s)
359 {
360 int i;
361
362 for (i = 0; i < s->nbanks; ++i){
363 s->banks[i].irqs = 0x00000000;
364 s->banks[i].mask = 0xffffffff;
365 s->banks[i].sens_edge = 0x00000000;
366 s->banks[i].fiq = 0x00000000;
367 s->banks[i].inputs = 0x00000000;
368 memset(s->banks[i].priority, 0, sizeof(s->banks[i].priority));
369 }
370
371 s->new_agr[0] = ~0;
372 s->new_agr[1] = ~0;
373 s->sir_intr[0] = 0;
374 s->sir_intr[1] = 0;
375
376 qemu_set_irq(s->parent_intr[0], 0);
377 qemu_set_irq(s->parent_intr[1], 0);
378 }
379
380 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
381 unsigned long size, unsigned char nbanks,
382 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
383 {
384 int iomemtype;
385 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
386 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
387 sizeof(struct omap_intr_handler_bank_s) * nbanks);
388
389 s->parent_intr[0] = parent_irq;
390 s->parent_intr[1] = parent_fiq;
391 s->base = base;
392 s->nbanks = nbanks;
393 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
394
395 omap_inth_reset(s);
396
397 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
398 omap_inth_writefn, s);
399 cpu_register_physical_memory(s->base, size, iomemtype);
400
401 return s;
402 }
403
404 /* OMAP1 DMA module */
405 struct omap_dma_channel_s {
406 /* transfer data */
407 int burst[2];
408 int pack[2];
409 enum omap_dma_port port[2];
410 target_phys_addr_t addr[2];
411 omap_dma_addressing_t mode[2];
412 uint16_t elements;
413 uint16_t frames;
414 int16_t frame_index[2];
415 int16_t element_index[2];
416 int data_type;
417
418 /* transfer type */
419 int transparent_copy;
420 int constant_fill;
421 uint32_t color;
422
423 /* auto init and linked channel data */
424 int end_prog;
425 int repeat;
426 int auto_init;
427 int link_enabled;
428 int link_next_ch;
429
430 /* interruption data */
431 int interrupts;
432 int status;
433
434 /* state data */
435 int active;
436 int enable;
437 int sync;
438 int pending_request;
439 int waiting_end_prog;
440 uint16_t cpc;
441
442 /* sync type */
443 int fs;
444 int bs;
445
446 /* compatibility */
447 int omap_3_1_compatible_disable;
448
449 qemu_irq irq;
450 struct omap_dma_channel_s *sibling;
451
452 struct omap_dma_reg_set_s {
453 target_phys_addr_t src, dest;
454 int frame;
455 int element;
456 int frame_delta[2];
457 int elem_delta[2];
458 int frames;
459 int elements;
460 } active_set;
461
462 /* unused parameters */
463 int priority;
464 int interleave_disabled;
465 int type;
466 };
467
468 struct omap_dma_s {
469 QEMUTimer *tm;
470 struct omap_mpu_state_s *mpu;
471 target_phys_addr_t base;
472 omap_clk clk;
473 int64_t delay;
474 uint32_t drq;
475 enum omap_dma_model model;
476 int omap_3_1_mapping_disabled;
477
478 uint16_t gcr;
479 int run_count;
480
481 int chans;
482 struct omap_dma_channel_s ch[16];
483 struct omap_dma_lcd_channel_s lcd_ch;
484 };
485
486 /* Interrupts */
487 #define TIMEOUT_INTR (1 << 0)
488 #define EVENT_DROP_INTR (1 << 1)
489 #define HALF_FRAME_INTR (1 << 2)
490 #define END_FRAME_INTR (1 << 3)
491 #define LAST_FRAME_INTR (1 << 4)
492 #define END_BLOCK_INTR (1 << 5)
493 #define SYNC (1 << 6)
494
495 static void omap_dma_interrupts_update(struct omap_dma_s *s)
496 {
497 struct omap_dma_channel_s *ch = s->ch;
498 int i;
499
500 if (s->omap_3_1_mapping_disabled) {
501 for (i = 0; i < s->chans; i ++, ch ++)
502 if (ch->status)
503 qemu_irq_raise(ch->irq);
504 } else {
505 /* First three interrupts are shared between two channels each. */
506 for (i = 0; i < 6; i ++, ch ++) {
507 if (ch->status || (ch->sibling && ch->sibling->status))
508 qemu_irq_raise(ch->irq);
509 }
510 }
511 }
512
513 static void omap_dma_channel_load(struct omap_dma_s *s,
514 struct omap_dma_channel_s *ch)
515 {
516 struct omap_dma_reg_set_s *a = &ch->active_set;
517 int i;
518 int omap_3_1 = !ch->omap_3_1_compatible_disable;
519
520 /*
521 * TODO: verify address ranges and alignment
522 * TODO: port endianness
523 */
524
525 a->src = ch->addr[0];
526 a->dest = ch->addr[1];
527 a->frames = ch->frames;
528 a->elements = ch->elements;
529 a->frame = 0;
530 a->element = 0;
531
532 if (unlikely(!ch->elements || !ch->frames)) {
533 printf("%s: bad DMA request\n", __FUNCTION__);
534 return;
535 }
536
537 for (i = 0; i < 2; i ++)
538 switch (ch->mode[i]) {
539 case constant:
540 a->elem_delta[i] = 0;
541 a->frame_delta[i] = 0;
542 break;
543 case post_incremented:
544 a->elem_delta[i] = ch->data_type;
545 a->frame_delta[i] = 0;
546 break;
547 case single_index:
548 a->elem_delta[i] = ch->data_type +
549 ch->element_index[omap_3_1 ? 0 : i] - 1;
550 a->frame_delta[i] = 0;
551 break;
552 case double_index:
553 a->elem_delta[i] = ch->data_type +
554 ch->element_index[omap_3_1 ? 0 : i] - 1;
555 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
556 ch->element_index[omap_3_1 ? 0 : i];
557 break;
558 default:
559 break;
560 }
561 }
562
563 static void omap_dma_activate_channel(struct omap_dma_s *s,
564 struct omap_dma_channel_s *ch)
565 {
566 if (!ch->active) {
567 ch->active = 1;
568 if (ch->sync)
569 ch->status |= SYNC;
570 s->run_count ++;
571 }
572
573 if (s->delay && !qemu_timer_pending(s->tm))
574 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
575 }
576
577 static void omap_dma_deactivate_channel(struct omap_dma_s *s,
578 struct omap_dma_channel_s *ch)
579 {
580 /* Update cpc */
581 ch->cpc = ch->active_set.dest & 0xffff;
582
583 if (ch->pending_request && !ch->waiting_end_prog) {
584 /* Don't deactivate the channel */
585 ch->pending_request = 0;
586 if (ch->enable)
587 return;
588 }
589
590 /* Don't deactive the channel if it is synchronized and the DMA request is
591 active */
592 if (ch->sync && (s->drq & (1 << ch->sync)) && ch->enable)
593 return;
594
595 if (ch->active) {
596 ch->active = 0;
597 ch->status &= ~SYNC;
598 s->run_count --;
599 }
600
601 if (!s->run_count)
602 qemu_del_timer(s->tm);
603 }
604
605 static void omap_dma_enable_channel(struct omap_dma_s *s,
606 struct omap_dma_channel_s *ch)
607 {
608 if (!ch->enable) {
609 ch->enable = 1;
610 ch->waiting_end_prog = 0;
611 omap_dma_channel_load(s, ch);
612 if ((!ch->sync) || (s->drq & (1 << ch->sync)))
613 omap_dma_activate_channel(s, ch);
614 }
615 }
616
617 static void omap_dma_disable_channel(struct omap_dma_s *s,
618 struct omap_dma_channel_s *ch)
619 {
620 if (ch->enable) {
621 ch->enable = 0;
622 /* Discard any pending request */
623 ch->pending_request = 0;
624 omap_dma_deactivate_channel(s, ch);
625 }
626 }
627
628 static void omap_dma_channel_end_prog(struct omap_dma_s *s,
629 struct omap_dma_channel_s *ch)
630 {
631 if (ch->waiting_end_prog) {
632 ch->waiting_end_prog = 0;
633 if (!ch->sync || ch->pending_request) {
634 ch->pending_request = 0;
635 omap_dma_activate_channel(s, ch);
636 }
637 }
638 }
639
640 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
641 {
642 s->omap_3_1_mapping_disabled = 0;
643 s->chans = 9;
644 }
645
646 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
647 {
648 s->omap_3_1_mapping_disabled = 1;
649 s->chans = 16;
650 }
651
652 static void omap_dma_process_request(struct omap_dma_s *s, int request)
653 {
654 int channel;
655 int drop_event = 0;
656 struct omap_dma_channel_s *ch = s->ch;
657
658 for (channel = 0; channel < s->chans; channel ++, ch ++) {
659 if (ch->enable && ch->sync == request) {
660 if (!ch->active)
661 omap_dma_activate_channel(s, ch);
662 else if (!ch->pending_request)
663 ch->pending_request = 1;
664 else {
665 /* Request collision */
666 /* Second request received while processing other request */
667 ch->status |= EVENT_DROP_INTR;
668 drop_event = 1;
669 }
670 }
671 }
672
673 if (drop_event)
674 omap_dma_interrupts_update(s);
675 }
676
677 static void omap_dma_channel_run(struct omap_dma_s *s)
678 {
679 int n = s->chans;
680 uint16_t status;
681 uint8_t value[4];
682 struct omap_dma_port_if_s *src_p, *dest_p;
683 struct omap_dma_reg_set_s *a;
684 struct omap_dma_channel_s *ch;
685
686 for (ch = s->ch; n; n --, ch ++) {
687 if (!ch->active)
688 continue;
689
690 a = &ch->active_set;
691
692 src_p = &s->mpu->port[ch->port[0]];
693 dest_p = &s->mpu->port[ch->port[1]];
694 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
695 (!dest_p->addr_valid(s->mpu, a->dest))) {
696 #if 0
697 /* Bus time-out */
698 if (ch->interrupts & TIMEOUT_INTR)
699 ch->status |= TIMEOUT_INTR;
700 omap_dma_deactivate_channel(s, ch);
701 continue;
702 #endif
703 printf("%s: Bus time-out in DMA%i operation\n",
704 __FUNCTION__, s->chans - n);
705 }
706
707 status = ch->status;
708 while (status == ch->status && ch->active) {
709 /* Transfer a single element */
710 /* FIXME: check the endianness */
711 if (!ch->constant_fill)
712 cpu_physical_memory_read(a->src, value, ch->data_type);
713 else
714 *(uint32_t *) value = ch->color;
715
716 if (!ch->transparent_copy ||
717 *(uint32_t *) value != ch->color)
718 cpu_physical_memory_write(a->dest, value, ch->data_type);
719
720 a->src += a->elem_delta[0];
721 a->dest += a->elem_delta[1];
722 a->element ++;
723
724 /* If the channel is element synchronized, deactivate it */
725 if (ch->sync && !ch->fs && !ch->bs)
726 omap_dma_deactivate_channel(s, ch);
727
728 /* If it is the last frame, set the LAST_FRAME interrupt */
729 if (a->element == 1 && a->frame == a->frames - 1)
730 if (ch->interrupts & LAST_FRAME_INTR)
731 ch->status |= LAST_FRAME_INTR;
732
733 /* If the half of the frame was reached, set the HALF_FRAME
734 interrupt */
735 if (a->element == (a->elements >> 1))
736 if (ch->interrupts & HALF_FRAME_INTR)
737 ch->status |= HALF_FRAME_INTR;
738
739 if (a->element == a->elements) {
740 /* End of Frame */
741 a->element = 0;
742 a->src += a->frame_delta[0];
743 a->dest += a->frame_delta[1];
744 a->frame ++;
745
746 /* If the channel is frame synchronized, deactivate it */
747 if (ch->sync && ch->fs)
748 omap_dma_deactivate_channel(s, ch);
749
750 /* If the channel is async, update cpc */
751 if (!ch->sync)
752 ch->cpc = a->dest & 0xffff;
753
754 /* Set the END_FRAME interrupt */
755 if (ch->interrupts & END_FRAME_INTR)
756 ch->status |= END_FRAME_INTR;
757
758 if (a->frame == a->frames) {
759 /* End of Block */
760 /* Disable the channel */
761
762 if (ch->omap_3_1_compatible_disable) {
763 omap_dma_disable_channel(s, ch);
764 if (ch->link_enabled)
765 omap_dma_enable_channel(s,
766 &s->ch[ch->link_next_ch]);
767 } else {
768 if (!ch->auto_init)
769 omap_dma_disable_channel(s, ch);
770 else if (ch->repeat || ch->end_prog)
771 omap_dma_channel_load(s, ch);
772 else {
773 ch->waiting_end_prog = 1;
774 omap_dma_deactivate_channel(s, ch);
775 }
776 }
777
778 if (ch->interrupts & END_BLOCK_INTR)
779 ch->status |= END_BLOCK_INTR;
780 }
781 }
782 }
783 }
784
785 omap_dma_interrupts_update(s);
786 if (s->run_count && s->delay)
787 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
788 }
789
790 static void omap_dma_reset(struct omap_dma_s *s)
791 {
792 int i;
793
794 qemu_del_timer(s->tm);
795 s->gcr = 0x0004;
796 s->drq = 0x00000000;
797 s->run_count = 0;
798 s->lcd_ch.src = emiff;
799 s->lcd_ch.condition = 0;
800 s->lcd_ch.interrupts = 0;
801 s->lcd_ch.dual = 0;
802 omap_dma_enable_3_1_mapping(s);
803 for (i = 0; i < s->chans; i ++) {
804 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
805 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
806 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
807 memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements));
808 memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames));
809 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
810 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
811 memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type));
812 memset(&s->ch[i].transparent_copy, 0,
813 sizeof(s->ch[i].transparent_copy));
814 memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill));
815 memset(&s->ch[i].color, 0, sizeof(s->ch[i].color));
816 memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog));
817 memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat));
818 memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init));
819 memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled));
820 memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch));
821 s->ch[i].interrupts = 0x0003;
822 memset(&s->ch[i].status, 0, sizeof(s->ch[i].status));
823 memset(&s->ch[i].active, 0, sizeof(s->ch[i].active));
824 memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable));
825 memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync));
826 memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request));
827 memset(&s->ch[i].waiting_end_prog, 0,
828 sizeof(s->ch[i].waiting_end_prog));
829 memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc));
830 memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs));
831 memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs));
832 memset(&s->ch[i].omap_3_1_compatible_disable, 0,
833 sizeof(s->ch[i].omap_3_1_compatible_disable));
834 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
835 memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority));
836 memset(&s->ch[i].interleave_disabled, 0,
837 sizeof(s->ch[i].interleave_disabled));
838 memset(&s->ch[i].type, 0, sizeof(s->ch[i].type));
839 }
840 }
841
842 static int omap_dma_ch_reg_read(struct omap_dma_s *s,
843 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
844 {
845 switch (reg) {
846 case 0x00: /* SYS_DMA_CSDP_CH0 */
847 *value = (ch->burst[1] << 14) |
848 (ch->pack[1] << 13) |
849 (ch->port[1] << 9) |
850 (ch->burst[0] << 7) |
851 (ch->pack[0] << 6) |
852 (ch->port[0] << 2) |
853 (ch->data_type >> 1);
854 break;
855
856 case 0x02: /* SYS_DMA_CCR_CH0 */
857 if (s->model == omap_dma_3_1)
858 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
859 else
860 *value = ch->omap_3_1_compatible_disable << 10;
861 *value |= (ch->mode[1] << 14) |
862 (ch->mode[0] << 12) |
863 (ch->end_prog << 11) |
864 (ch->repeat << 9) |
865 (ch->auto_init << 8) |
866 (ch->enable << 7) |
867 (ch->priority << 6) |
868 (ch->fs << 5) | ch->sync;
869 break;
870
871 case 0x04: /* SYS_DMA_CICR_CH0 */
872 *value = ch->interrupts;
873 break;
874
875 case 0x06: /* SYS_DMA_CSR_CH0 */
876 *value = ch->status;
877 ch->status &= SYNC;
878 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
879 *value |= (ch->sibling->status & 0x3f) << 6;
880 ch->sibling->status &= SYNC;
881 }
882 qemu_irq_lower(ch->irq);
883 break;
884
885 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
886 *value = ch->addr[0] & 0x0000ffff;
887 break;
888
889 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
890 *value = ch->addr[0] >> 16;
891 break;
892
893 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
894 *value = ch->addr[1] & 0x0000ffff;
895 break;
896
897 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
898 *value = ch->addr[1] >> 16;
899 break;
900
901 case 0x10: /* SYS_DMA_CEN_CH0 */
902 *value = ch->elements;
903 break;
904
905 case 0x12: /* SYS_DMA_CFN_CH0 */
906 *value = ch->frames;
907 break;
908
909 case 0x14: /* SYS_DMA_CFI_CH0 */
910 *value = ch->frame_index[0];
911 break;
912
913 case 0x16: /* SYS_DMA_CEI_CH0 */
914 *value = ch->element_index[0];
915 break;
916
917 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
918 if (ch->omap_3_1_compatible_disable)
919 *value = ch->active_set.src & 0xffff; /* CSAC */
920 else
921 *value = ch->cpc;
922 break;
923
924 case 0x1a: /* DMA_CDAC */
925 *value = ch->active_set.dest & 0xffff; /* CDAC */
926 break;
927
928 case 0x1c: /* DMA_CDEI */
929 *value = ch->element_index[1];
930 break;
931
932 case 0x1e: /* DMA_CDFI */
933 *value = ch->frame_index[1];
934 break;
935
936 case 0x20: /* DMA_COLOR_L */
937 *value = ch->color & 0xffff;
938 break;
939
940 case 0x22: /* DMA_COLOR_U */
941 *value = ch->color >> 16;
942 break;
943
944 case 0x24: /* DMA_CCR2 */
945 *value = (ch->bs << 2) |
946 (ch->transparent_copy << 1) |
947 ch->constant_fill;
948 break;
949
950 case 0x28: /* DMA_CLNK_CTRL */
951 *value = (ch->link_enabled << 15) |
952 (ch->link_next_ch & 0xf);
953 break;
954
955 case 0x2a: /* DMA_LCH_CTRL */
956 *value = (ch->interleave_disabled << 15) |
957 ch->type;
958 break;
959
960 default:
961 return 1;
962 }
963 return 0;
964 }
965
966 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
967 struct omap_dma_channel_s *ch, int reg, uint16_t value)
968 {
969 switch (reg) {
970 case 0x00: /* SYS_DMA_CSDP_CH0 */
971 ch->burst[1] = (value & 0xc000) >> 14;
972 ch->pack[1] = (value & 0x2000) >> 13;
973 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
974 ch->burst[0] = (value & 0x0180) >> 7;
975 ch->pack[0] = (value & 0x0040) >> 6;
976 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
977 ch->data_type = (1 << (value & 3));
978 if (ch->port[0] >= omap_dma_port_last)
979 printf("%s: invalid DMA port %i\n", __FUNCTION__,
980 ch->port[0]);
981 if (ch->port[1] >= omap_dma_port_last)
982 printf("%s: invalid DMA port %i\n", __FUNCTION__,
983 ch->port[1]);
984 if ((value & 3) == 3)
985 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
986 break;
987
988 case 0x02: /* SYS_DMA_CCR_CH0 */
989 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
990 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
991 ch->end_prog = (value & 0x0800) >> 11;
992 if (s->model > omap_dma_3_1)
993 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
994 ch->repeat = (value & 0x0200) >> 9;
995 ch->auto_init = (value & 0x0100) >> 8;
996 ch->priority = (value & 0x0040) >> 6;
997 ch->fs = (value & 0x0020) >> 5;
998 ch->sync = value & 0x001f;
999
1000 if (value & 0x0080)
1001 omap_dma_enable_channel(s, ch);
1002 else
1003 omap_dma_disable_channel(s, ch);
1004
1005 if (ch->end_prog)
1006 omap_dma_channel_end_prog(s, ch);
1007
1008 break;
1009
1010 case 0x04: /* SYS_DMA_CICR_CH0 */
1011 ch->interrupts = value;
1012 break;
1013
1014 case 0x06: /* SYS_DMA_CSR_CH0 */
1015 OMAP_RO_REG((target_phys_addr_t) reg);
1016 break;
1017
1018 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
1019 ch->addr[0] &= 0xffff0000;
1020 ch->addr[0] |= value;
1021 break;
1022
1023 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
1024 ch->addr[0] &= 0x0000ffff;
1025 ch->addr[0] |= (uint32_t) value << 16;
1026 break;
1027
1028 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
1029 ch->addr[1] &= 0xffff0000;
1030 ch->addr[1] |= value;
1031 break;
1032
1033 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
1034 ch->addr[1] &= 0x0000ffff;
1035 ch->addr[1] |= (uint32_t) value << 16;
1036 break;
1037
1038 case 0x10: /* SYS_DMA_CEN_CH0 */
1039 ch->elements = value;
1040 break;
1041
1042 case 0x12: /* SYS_DMA_CFN_CH0 */
1043 ch->frames = value;
1044 break;
1045
1046 case 0x14: /* SYS_DMA_CFI_CH0 */
1047 ch->frame_index[0] = (int16_t) value;
1048 break;
1049
1050 case 0x16: /* SYS_DMA_CEI_CH0 */
1051 ch->element_index[0] = (int16_t) value;
1052 break;
1053
1054 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
1055 OMAP_RO_REG((target_phys_addr_t) reg);
1056 break;
1057
1058 case 0x1c: /* DMA_CDEI */
1059 ch->element_index[1] = (int16_t) value;
1060 break;
1061
1062 case 0x1e: /* DMA_CDFI */
1063 ch->frame_index[1] = (int16_t) value;
1064 break;
1065
1066 case 0x20: /* DMA_COLOR_L */
1067 ch->color &= 0xffff0000;
1068 ch->color |= value;
1069 break;
1070
1071 case 0x22: /* DMA_COLOR_U */
1072 ch->color &= 0xffff;
1073 ch->color |= value << 16;
1074 break;
1075
1076 case 0x24: /* DMA_CCR2 */
1077 ch->bs = (value >> 2) & 0x1;
1078 ch->transparent_copy = (value >> 1) & 0x1;
1079 ch->constant_fill = value & 0x1;
1080 break;
1081
1082 case 0x28: /* DMA_CLNK_CTRL */
1083 ch->link_enabled = (value >> 15) & 0x1;
1084 if (value & (1 << 14)) { /* Stop_Lnk */
1085 ch->link_enabled = 0;
1086 omap_dma_disable_channel(s, ch);
1087 }
1088 ch->link_next_ch = value & 0x1f;
1089 break;
1090
1091 case 0x2a: /* DMA_LCH_CTRL */
1092 ch->interleave_disabled = (value >> 15) & 0x1;
1093 ch->type = value & 0xf;
1094 break;
1095
1096 default:
1097 return 1;
1098 }
1099 return 0;
1100 }
1101
1102 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1103 uint16_t value)
1104 {
1105 switch (offset) {
1106 case 0xbc0: /* DMA_LCD_CSDP */
1107 s->brust_f2 = (value >> 14) & 0x3;
1108 s->pack_f2 = (value >> 13) & 0x1;
1109 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1110 s->brust_f1 = (value >> 7) & 0x3;
1111 s->pack_f1 = (value >> 6) & 0x1;
1112 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1113 break;
1114
1115 case 0xbc2: /* DMA_LCD_CCR */
1116 s->mode_f2 = (value >> 14) & 0x3;
1117 s->mode_f1 = (value >> 12) & 0x3;
1118 s->end_prog = (value >> 11) & 0x1;
1119 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1120 s->repeat = (value >> 9) & 0x1;
1121 s->auto_init = (value >> 8) & 0x1;
1122 s->running = (value >> 7) & 0x1;
1123 s->priority = (value >> 6) & 0x1;
1124 s->bs = (value >> 4) & 0x1;
1125 break;
1126
1127 case 0xbc4: /* DMA_LCD_CTRL */
1128 s->dst = (value >> 8) & 0x1;
1129 s->src = ((value >> 6) & 0x3) << 1;
1130 s->condition = 0;
1131 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1132 s->interrupts = (value >> 1) & 1;
1133 s->dual = value & 1;
1134 break;
1135
1136 case 0xbc8: /* TOP_B1_L */
1137 s->src_f1_top &= 0xffff0000;
1138 s->src_f1_top |= 0x0000ffff & value;
1139 break;
1140
1141 case 0xbca: /* TOP_B1_U */
1142 s->src_f1_top &= 0x0000ffff;
1143 s->src_f1_top |= value << 16;
1144 break;
1145
1146 case 0xbcc: /* BOT_B1_L */
1147 s->src_f1_bottom &= 0xffff0000;
1148 s->src_f1_bottom |= 0x0000ffff & value;
1149 break;
1150
1151 case 0xbce: /* BOT_B1_U */
1152 s->src_f1_bottom &= 0x0000ffff;
1153 s->src_f1_bottom |= (uint32_t) value << 16;
1154 break;
1155
1156 case 0xbd0: /* TOP_B2_L */
1157 s->src_f2_top &= 0xffff0000;
1158 s->src_f2_top |= 0x0000ffff & value;
1159 break;
1160
1161 case 0xbd2: /* TOP_B2_U */
1162 s->src_f2_top &= 0x0000ffff;
1163 s->src_f2_top |= (uint32_t) value << 16;
1164 break;
1165
1166 case 0xbd4: /* BOT_B2_L */
1167 s->src_f2_bottom &= 0xffff0000;
1168 s->src_f2_bottom |= 0x0000ffff & value;
1169 break;
1170
1171 case 0xbd6: /* BOT_B2_U */
1172 s->src_f2_bottom &= 0x0000ffff;
1173 s->src_f2_bottom |= (uint32_t) value << 16;
1174 break;
1175
1176 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1177 s->element_index_f1 = value;
1178 break;
1179
1180 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1181 s->frame_index_f1 &= 0xffff0000;
1182 s->frame_index_f1 |= 0x0000ffff & value;
1183 break;
1184
1185 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1186 s->frame_index_f1 &= 0x0000ffff;
1187 s->frame_index_f1 |= (uint32_t) value << 16;
1188 break;
1189
1190 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1191 s->element_index_f2 = value;
1192 break;
1193
1194 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1195 s->frame_index_f2 &= 0xffff0000;
1196 s->frame_index_f2 |= 0x0000ffff & value;
1197 break;
1198
1199 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1200 s->frame_index_f2 &= 0x0000ffff;
1201 s->frame_index_f2 |= (uint32_t) value << 16;
1202 break;
1203
1204 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1205 s->elements_f1 = value;
1206 break;
1207
1208 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1209 s->frames_f1 = value;
1210 break;
1211
1212 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1213 s->elements_f2 = value;
1214 break;
1215
1216 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1217 s->frames_f2 = value;
1218 break;
1219
1220 case 0xbea: /* DMA_LCD_LCH_CTRL */
1221 s->lch_type = value & 0xf;
1222 break;
1223
1224 default:
1225 return 1;
1226 }
1227 return 0;
1228 }
1229
1230 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1231 uint16_t *ret)
1232 {
1233 switch (offset) {
1234 case 0xbc0: /* DMA_LCD_CSDP */
1235 *ret = (s->brust_f2 << 14) |
1236 (s->pack_f2 << 13) |
1237 ((s->data_type_f2 >> 1) << 11) |
1238 (s->brust_f1 << 7) |
1239 (s->pack_f1 << 6) |
1240 ((s->data_type_f1 >> 1) << 0);
1241 break;
1242
1243 case 0xbc2: /* DMA_LCD_CCR */
1244 *ret = (s->mode_f2 << 14) |
1245 (s->mode_f1 << 12) |
1246 (s->end_prog << 11) |
1247 (s->omap_3_1_compatible_disable << 10) |
1248 (s->repeat << 9) |
1249 (s->auto_init << 8) |
1250 (s->running << 7) |
1251 (s->priority << 6) |
1252 (s->bs << 4);
1253 break;
1254
1255 case 0xbc4: /* DMA_LCD_CTRL */
1256 qemu_irq_lower(s->irq);
1257 *ret = (s->dst << 8) |
1258 ((s->src & 0x6) << 5) |
1259 (s->condition << 3) |
1260 (s->interrupts << 1) |
1261 s->dual;
1262 break;
1263
1264 case 0xbc8: /* TOP_B1_L */
1265 *ret = s->src_f1_top & 0xffff;
1266 break;
1267
1268 case 0xbca: /* TOP_B1_U */
1269 *ret = s->src_f1_top >> 16;
1270 break;
1271
1272 case 0xbcc: /* BOT_B1_L */
1273 *ret = s->src_f1_bottom & 0xffff;
1274 break;
1275
1276 case 0xbce: /* BOT_B1_U */
1277 *ret = s->src_f1_bottom >> 16;
1278 break;
1279
1280 case 0xbd0: /* TOP_B2_L */
1281 *ret = s->src_f2_top & 0xffff;
1282 break;
1283
1284 case 0xbd2: /* TOP_B2_U */
1285 *ret = s->src_f2_top >> 16;
1286 break;
1287
1288 case 0xbd4: /* BOT_B2_L */
1289 *ret = s->src_f2_bottom & 0xffff;
1290 break;
1291
1292 case 0xbd6: /* BOT_B2_U */
1293 *ret = s->src_f2_bottom >> 16;
1294 break;
1295
1296 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1297 *ret = s->element_index_f1;
1298 break;
1299
1300 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1301 *ret = s->frame_index_f1 & 0xffff;
1302 break;
1303
1304 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1305 *ret = s->frame_index_f1 >> 16;
1306 break;
1307
1308 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1309 *ret = s->element_index_f2;
1310 break;
1311
1312 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1313 *ret = s->frame_index_f2 & 0xffff;
1314 break;
1315
1316 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1317 *ret = s->frame_index_f2 >> 16;
1318 break;
1319
1320 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1321 *ret = s->elements_f1;
1322 break;
1323
1324 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1325 *ret = s->frames_f1;
1326 break;
1327
1328 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1329 *ret = s->elements_f2;
1330 break;
1331
1332 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1333 *ret = s->frames_f2;
1334 break;
1335
1336 case 0xbea: /* DMA_LCD_LCH_CTRL */
1337 *ret = s->lch_type;
1338 break;
1339
1340 default:
1341 return 1;
1342 }
1343 return 0;
1344 }
1345
1346 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1347 uint16_t value)
1348 {
1349 switch (offset) {
1350 case 0x300: /* SYS_DMA_LCD_CTRL */
1351 s->src = (value & 0x40) ? imif : emiff;
1352 s->condition = 0;
1353 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1354 s->interrupts = (value >> 1) & 1;
1355 s->dual = value & 1;
1356 break;
1357
1358 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1359 s->src_f1_top &= 0xffff0000;
1360 s->src_f1_top |= 0x0000ffff & value;
1361 break;
1362
1363 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1364 s->src_f1_top &= 0x0000ffff;
1365 s->src_f1_top |= value << 16;
1366 break;
1367
1368 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1369 s->src_f1_bottom &= 0xffff0000;
1370 s->src_f1_bottom |= 0x0000ffff & value;
1371 break;
1372
1373 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1374 s->src_f1_bottom &= 0x0000ffff;
1375 s->src_f1_bottom |= value << 16;
1376 break;
1377
1378 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1379 s->src_f2_top &= 0xffff0000;
1380 s->src_f2_top |= 0x0000ffff & value;
1381 break;
1382
1383 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1384 s->src_f2_top &= 0x0000ffff;
1385 s->src_f2_top |= value << 16;
1386 break;
1387
1388 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1389 s->src_f2_bottom &= 0xffff0000;
1390 s->src_f2_bottom |= 0x0000ffff & value;
1391 break;
1392
1393 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1394 s->src_f2_bottom &= 0x0000ffff;
1395 s->src_f2_bottom |= value << 16;
1396 break;
1397
1398 default:
1399 return 1;
1400 }
1401 return 0;
1402 }
1403
1404 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1405 uint16_t *ret)
1406 {
1407 int i;
1408
1409 switch (offset) {
1410 case 0x300: /* SYS_DMA_LCD_CTRL */
1411 i = s->condition;
1412 s->condition = 0;
1413 qemu_irq_lower(s->irq);
1414 *ret = ((s->src == imif) << 6) | (i << 3) |
1415 (s->interrupts << 1) | s->dual;
1416 break;
1417
1418 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1419 *ret = s->src_f1_top & 0xffff;
1420 break;
1421
1422 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1423 *ret = s->src_f1_top >> 16;
1424 break;
1425
1426 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1427 *ret = s->src_f1_bottom & 0xffff;
1428 break;
1429
1430 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1431 *ret = s->src_f1_bottom >> 16;
1432 break;
1433
1434 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1435 *ret = s->src_f2_top & 0xffff;
1436 break;
1437
1438 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1439 *ret = s->src_f2_top >> 16;
1440 break;
1441
1442 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1443 *ret = s->src_f2_bottom & 0xffff;
1444 break;
1445
1446 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1447 *ret = s->src_f2_bottom >> 16;
1448 break;
1449
1450 default:
1451 return 1;
1452 }
1453 return 0;
1454 }
1455
1456 static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1457 {
1458 switch (offset) {
1459 case 0x400: /* SYS_DMA_GCR */
1460 s->gcr = value;
1461 break;
1462
1463 case 0x404: /* DMA_GSCR */
1464 if (value & 0x8)
1465 omap_dma_disable_3_1_mapping(s);
1466 else
1467 omap_dma_enable_3_1_mapping(s);
1468 break;
1469
1470 case 0x408: /* DMA_GRST */
1471 if (value & 0x1)
1472 omap_dma_reset(s);
1473 break;
1474
1475 default:
1476 return 1;
1477 }
1478 return 0;
1479 }
1480
1481 static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1482 uint16_t *ret)
1483 {
1484 switch (offset) {
1485 case 0x400: /* SYS_DMA_GCR */
1486 *ret = s->gcr;
1487 break;
1488
1489 case 0x404: /* DMA_GSCR */
1490 *ret = s->omap_3_1_mapping_disabled << 3;
1491 break;
1492
1493 case 0x408: /* DMA_GRST */
1494 *ret = 0;
1495 break;
1496
1497 case 0x442: /* DMA_HW_ID */
1498 case 0x444: /* DMA_PCh2_ID */
1499 case 0x446: /* DMA_PCh0_ID */
1500 case 0x448: /* DMA_PCh1_ID */
1501 case 0x44a: /* DMA_PChG_ID */
1502 case 0x44c: /* DMA_PChD_ID */
1503 *ret = 1;
1504 break;
1505
1506 case 0x44e: /* DMA_CAPS_0_U */
1507 *ret = (1 << 3) | /* Constant Fill Capacity */
1508 (1 << 2); /* Transparent BLT Capacity */
1509 break;
1510
1511 case 0x450: /* DMA_CAPS_0_L */
1512 case 0x452: /* DMA_CAPS_1_U */
1513 *ret = 0;
1514 break;
1515
1516 case 0x454: /* DMA_CAPS_1_L */
1517 *ret = (1 << 1); /* 1-bit palletized capability */
1518 break;
1519
1520 case 0x456: /* DMA_CAPS_2 */
1521 *ret = (1 << 8) | /* SSDIC */
1522 (1 << 7) | /* DDIAC */
1523 (1 << 6) | /* DSIAC */
1524 (1 << 5) | /* DPIAC */
1525 (1 << 4) | /* DCAC */
1526 (1 << 3) | /* SDIAC */
1527 (1 << 2) | /* SSIAC */
1528 (1 << 1) | /* SPIAC */
1529 1; /* SCAC */
1530 break;
1531
1532 case 0x458: /* DMA_CAPS_3 */
1533 *ret = (1 << 5) | /* CCC */
1534 (1 << 4) | /* IC */
1535 (1 << 3) | /* ARC */
1536 (1 << 2) | /* AEC */
1537 (1 << 1) | /* FSC */
1538 1; /* ESC */
1539 break;
1540
1541 case 0x45a: /* DMA_CAPS_4 */
1542 *ret = (1 << 6) | /* SSC */
1543 (1 << 5) | /* BIC */
1544 (1 << 4) | /* LFIC */
1545 (1 << 3) | /* FIC */
1546 (1 << 2) | /* HFIC */
1547 (1 << 1) | /* EDIC */
1548 1; /* TOIC */
1549 break;
1550
1551 case 0x460: /* DMA_PCh2_SR */
1552 case 0x480: /* DMA_PCh0_SR */
1553 case 0x482: /* DMA_PCh1_SR */
1554 case 0x4c0: /* DMA_PChD_SR_0 */
1555 printf("%s: Physical Channel Status Registers not implemented.\n",
1556 __FUNCTION__);
1557 *ret = 0xff;
1558 break;
1559
1560 default:
1561 return 1;
1562 }
1563 return 0;
1564 }
1565
1566 static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
1567 {
1568 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1569 int reg, ch, offset = addr - s->base;
1570 uint16_t ret;
1571
1572 switch (offset) {
1573 case 0x300 ... 0x3fe:
1574 if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1575 if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
1576 break;
1577 return ret;
1578 }
1579 /* Fall through. */
1580 case 0x000 ... 0x2fe:
1581 reg = offset & 0x3f;
1582 ch = (offset >> 6) & 0x0f;
1583 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1584 break;
1585 return ret;
1586
1587 case 0x404 ... 0x4fe:
1588 if (s->model == omap_dma_3_1)
1589 break;
1590 /* Fall through. */
1591 case 0x400:
1592 if (omap_dma_sys_read(s, offset, &ret))
1593 break;
1594 return ret;
1595
1596 case 0xb00 ... 0xbfe:
1597 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1598 if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
1599 break;
1600 return ret;
1601 }
1602 break;
1603 }
1604
1605 OMAP_BAD_REG(addr);
1606 return 0;
1607 }
1608
1609 static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1610 uint32_t value)
1611 {
1612 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1613 int reg, ch, offset = addr - s->base;
1614
1615 switch (offset) {
1616 case 0x300 ... 0x3fe:
1617 if (s->model == omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1618 if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
1619 break;
1620 return;
1621 }
1622 /* Fall through. */
1623 case 0x000 ... 0x2fe:
1624 reg = offset & 0x3f;
1625 ch = (offset >> 6) & 0x0f;
1626 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1627 break;
1628 return;
1629
1630 case 0x404 ... 0x4fe:
1631 if (s->model == omap_dma_3_1)
1632 break;
1633 case 0x400:
1634 /* Fall through. */
1635 if (omap_dma_sys_write(s, offset, value))
1636 break;
1637 return;
1638
1639 case 0xb00 ... 0xbfe:
1640 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1641 if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
1642 break;
1643 return;
1644 }
1645 break;
1646 }
1647
1648 OMAP_BAD_REG(addr);
1649 }
1650
1651 static CPUReadMemoryFunc *omap_dma_readfn[] = {
1652 omap_badwidth_read16,
1653 omap_dma_read,
1654 omap_badwidth_read16,
1655 };
1656
1657 static CPUWriteMemoryFunc *omap_dma_writefn[] = {
1658 omap_badwidth_write16,
1659 omap_dma_write,
1660 omap_badwidth_write16,
1661 };
1662
1663 static void omap_dma_request(void *opaque, int drq, int req)
1664 {
1665 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1666 /* The request pins are level triggered. */
1667 if (req) {
1668 if (~s->drq & (1 << drq)) {
1669 s->drq |= 1 << drq;
1670 omap_dma_process_request(s, drq);
1671 }
1672 } else
1673 s->drq &= ~(1 << drq);
1674 }
1675
1676 static void omap_dma_clk_update(void *opaque, int line, int on)
1677 {
1678 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1679
1680 if (on) {
1681 /* TODO: make a clever calculation */
1682 s->delay = ticks_per_sec >> 8;
1683 if (s->run_count)
1684 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
1685 } else {
1686 s->delay = 0;
1687 qemu_del_timer(s->tm);
1688 }
1689 }
1690
1691 struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1692 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1693 enum omap_dma_model model)
1694 {
1695 int iomemtype, num_irqs, memsize, i;
1696 struct omap_dma_s *s = (struct omap_dma_s *)
1697 qemu_mallocz(sizeof(struct omap_dma_s));
1698
1699 if (model == omap_dma_3_1) {
1700 num_irqs = 6;
1701 memsize = 0x800;
1702 } else {
1703 num_irqs = 16;
1704 memsize = 0xc00;
1705 }
1706 s->base = base;
1707 s->model = model;
1708 s->mpu = mpu;
1709 s->clk = clk;
1710 s->lcd_ch.irq = lcd_irq;
1711 s->lcd_ch.mpu = mpu;
1712 while (num_irqs --)
1713 s->ch[num_irqs].irq = irqs[num_irqs];
1714 for (i = 0; i < 3; i ++) {
1715 s->ch[i].sibling = &s->ch[i + 6];
1716 s->ch[i + 6].sibling = &s->ch[i];
1717 }
1718 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
1719 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1720 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1721 omap_dma_reset(s);
1722 omap_dma_clk_update(s, 0, 1);
1723
1724 iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
1725 omap_dma_writefn, s);
1726 cpu_register_physical_memory(s->base, memsize, iomemtype);
1727
1728 return s;
1729 }
1730
1731 /* DMA ports */
1732 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
1733 target_phys_addr_t addr)
1734 {
1735 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
1736 }
1737
1738 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
1739 target_phys_addr_t addr)
1740 {
1741 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
1742 }
1743
1744 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
1745 target_phys_addr_t addr)
1746 {
1747 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
1748 }
1749
1750 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
1751 target_phys_addr_t addr)
1752 {
1753 return addr >= 0xfffb0000 && addr < 0xffff0000;
1754 }
1755
1756 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
1757 target_phys_addr_t addr)
1758 {
1759 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
1760 }
1761
1762 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
1763 target_phys_addr_t addr)
1764 {
1765 return addr >= 0xe1010000 && addr < 0xe1020004;
1766 }
1767
1768 /* MPU OS timers */
1769 struct omap_mpu_timer_s {
1770 qemu_irq irq;
1771 omap_clk clk;
1772 target_phys_addr_t base;
1773 uint32_t val;
1774 int64_t time;
1775 QEMUTimer *timer;
1776 int64_t rate;
1777 int it_ena;
1778
1779 int enable;
1780 int ptv;
1781 int ar;
1782 int st;
1783 uint32_t reset_val;
1784 };
1785
1786 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
1787 {
1788 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
1789
1790 if (timer->st && timer->enable && timer->rate)
1791 return timer->val - muldiv64(distance >> (timer->ptv + 1),
1792 timer->rate, ticks_per_sec);
1793 else
1794 return timer->val;
1795 }
1796
1797 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
1798 {
1799 timer->val = omap_timer_read(timer);
1800 timer->time = qemu_get_clock(vm_clock);
1801 }
1802
1803 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
1804 {
1805 int64_t expires;
1806
1807 if (timer->enable && timer->st && timer->rate) {
1808 timer->val = timer->reset_val; /* Should skip this on clk enable */
1809 expires = muldiv64(timer->val << (timer->ptv + 1),
1810 ticks_per_sec, timer->rate);
1811
1812 /* If timer expiry would be sooner than in about 1 ms and
1813 * auto-reload isn't set, then fire immediately. This is a hack
1814 * to make systems like PalmOS run in acceptable time. PalmOS
1815 * sets the interval to a very low value and polls the status bit
1816 * in a busy loop when it wants to sleep just a couple of CPU
1817 * ticks. */
1818 if (expires > (ticks_per_sec >> 10) || timer->ar)
1819 qemu_mod_timer(timer->timer, timer->time + expires);
1820 else {
1821 timer->val = 0;
1822 timer->st = 0;
1823 if (timer->it_ena)
1824 /* Edge-triggered irq */
1825 qemu_irq_pulse(timer->irq);
1826 }
1827 } else
1828 qemu_del_timer(timer->timer);
1829 }
1830
1831 static void omap_timer_tick(void *opaque)
1832 {
1833 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
1834 omap_timer_sync(timer);
1835
1836 if (!timer->ar) {
1837 timer->val = 0;
1838 timer->st = 0;
1839 }
1840
1841 if (timer->it_ena)
1842 /* Edge-triggered irq */
1843 qemu_irq_pulse(timer->irq);
1844 omap_timer_update(timer);
1845 }
1846
1847 static void omap_timer_clk_update(void *opaque, int line, int on)
1848 {
1849 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
1850
1851 omap_timer_sync(timer);
1852 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
1853 omap_timer_update(timer);
1854 }
1855
1856 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
1857 {
1858 omap_clk_adduser(timer->clk,
1859 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
1860 timer->rate = omap_clk_getrate(timer->clk);
1861 }
1862
1863 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
1864 {
1865 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
1866 int offset = addr - s->base;
1867
1868 switch (offset) {
1869 case 0x00: /* CNTL_TIMER */
1870 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
1871
1872 case 0x04: /* LOAD_TIM */
1873 break;
1874
1875 case 0x08: /* READ_TIM */
1876 return omap_timer_read(s);
1877 }
1878
1879 OMAP_BAD_REG(addr);
1880 return 0;
1881 }
1882
1883 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
1884 uint32_t value)
1885 {
1886 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
1887 int offset = addr - s->base;
1888
1889 switch (offset) {
1890 case 0x00: /* CNTL_TIMER */
1891 omap_timer_sync(s);
1892 s->enable = (value >> 5) & 1;
1893 s->ptv = (value >> 2) & 7;
1894 s->ar = (value >> 1) & 1;
1895 s->st = value & 1;
1896 omap_timer_update(s);
1897 return;
1898
1899 case 0x04: /* LOAD_TIM */
1900 s->reset_val = value;
1901 return;
1902
1903 case 0x08: /* READ_TIM */
1904 OMAP_RO_REG(addr);
1905 break;
1906
1907 default:
1908 OMAP_BAD_REG(addr);
1909 }
1910 }
1911
1912 static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
1913 omap_badwidth_read32,
1914 omap_badwidth_read32,
1915 omap_mpu_timer_read,
1916 };
1917
1918 static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
1919 omap_badwidth_write32,
1920 omap_badwidth_write32,
1921 omap_mpu_timer_write,
1922 };
1923
1924 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
1925 {
1926 qemu_del_timer(s->timer);
1927 s->enable = 0;
1928 s->reset_val = 31337;
1929 s->val = 0;
1930 s->ptv = 0;
1931 s->ar = 0;
1932 s->st = 0;
1933 s->it_ena = 1;
1934 }
1935
1936 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
1937 qemu_irq irq, omap_clk clk)
1938 {
1939 int iomemtype;
1940 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
1941 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
1942
1943 s->irq = irq;
1944 s->clk = clk;
1945 s->base = base;
1946 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
1947 omap_mpu_timer_reset(s);
1948 omap_timer_clk_setup(s);
1949
1950 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
1951 omap_mpu_timer_writefn, s);
1952 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1953
1954 return s;
1955 }
1956
1957 /* Watchdog timer */
1958 struct omap_watchdog_timer_s {
1959 struct omap_mpu_timer_s timer;
1960 uint8_t last_wr;
1961 int mode;
1962 int free;
1963 int reset;
1964 };
1965
1966 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
1967 {
1968 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
1969 int offset = addr - s->timer.base;
1970
1971 switch (offset) {
1972 case 0x00: /* CNTL_TIMER */
1973 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
1974 (s->timer.st << 7) | (s->free << 1);
1975
1976 case 0x04: /* READ_TIMER */
1977 return omap_timer_read(&s->timer);
1978
1979 case 0x08: /* TIMER_MODE */
1980 return s->mode << 15;
1981 }
1982
1983 OMAP_BAD_REG(addr);
1984 return 0;
1985 }
1986
1987 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
1988 uint32_t value)
1989 {
1990 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
1991 int offset = addr - s->timer.base;
1992
1993 switch (offset) {
1994 case 0x00: /* CNTL_TIMER */
1995 omap_timer_sync(&s->timer);
1996 s->timer.ptv = (value >> 9) & 7;
1997 s->timer.ar = (value >> 8) & 1;
1998 s->timer.st = (value >> 7) & 1;
1999 s->free = (value >> 1) & 1;
2000 omap_timer_update(&s->timer);
2001 break;
2002
2003 case 0x04: /* LOAD_TIMER */
2004 s->timer.reset_val = value & 0xffff;
2005 break;
2006
2007 case 0x08: /* TIMER_MODE */
2008 if (!s->mode && ((value >> 15) & 1))
2009 omap_clk_get(s->timer.clk);
2010 s->mode |= (value >> 15) & 1;
2011 if (s->last_wr == 0xf5) {
2012 if ((value & 0xff) == 0xa0) {
2013 if (s->mode) {
2014 s->mode = 0;
2015 omap_clk_put(s->timer.clk);
2016 }
2017 } else {
2018 /* XXX: on T|E hardware somehow this has no effect,
2019 * on Zire 71 it works as specified. */
2020 s->reset = 1;
2021 qemu_system_reset_request();
2022 }
2023 }
2024 s->last_wr = value & 0xff;
2025 break;
2026
2027 default:
2028 OMAP_BAD_REG(addr);
2029 }
2030 }
2031
2032 static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
2033 omap_badwidth_read16,
2034 omap_wd_timer_read,
2035 omap_badwidth_read16,
2036 };
2037
2038 static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
2039 omap_badwidth_write16,
2040 omap_wd_timer_write,
2041 omap_badwidth_write16,
2042 };
2043
2044 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
2045 {
2046 qemu_del_timer(s->timer.timer);
2047 if (!s->mode)
2048 omap_clk_get(s->timer.clk);
2049 s->mode = 1;
2050 s->free = 1;
2051 s->reset = 0;
2052 s->timer.enable = 1;
2053 s->timer.it_ena = 1;
2054 s->timer.reset_val = 0xffff;
2055 s->timer.val = 0;
2056 s->timer.st = 0;
2057 s->timer.ptv = 0;
2058 s->timer.ar = 0;
2059 omap_timer_update(&s->timer);
2060 }
2061
2062 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
2063 qemu_irq irq, omap_clk clk)
2064 {
2065 int iomemtype;
2066 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
2067 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
2068
2069 s->timer.irq = irq;
2070 s->timer.clk = clk;
2071 s->timer.base = base;
2072 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
2073 omap_wd_timer_reset(s);
2074 omap_timer_clk_setup(&s->timer);
2075
2076 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
2077 omap_wd_timer_writefn, s);
2078 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
2079
2080 return s;
2081 }
2082
2083 /* 32-kHz timer */
2084 struct omap_32khz_timer_s {
2085 struct omap_mpu_timer_s timer;
2086 };
2087
2088 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
2089 {
2090 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
2091 int offset = addr & OMAP_MPUI_REG_MASK;
2092
2093 switch (offset) {
2094 case 0x00: /* TVR */
2095 return s->timer.reset_val;
2096
2097 case 0x04: /* TCR */
2098 return omap_timer_read(&s->timer);
2099
2100 case 0x08: /* CR */
2101 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
2102
2103 default:
2104 break;
2105 }
2106 OMAP_BAD_REG(addr);
2107 return 0;
2108 }
2109
2110 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
2111 uint32_t value)
2112 {
2113 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
2114 int offset = addr & OMAP_MPUI_REG_MASK;
2115
2116 switch (offset) {
2117 case 0x00: /* TVR */
2118 s->timer.reset_val = value & 0x00ffffff;
2119 break;
2120
2121 case 0x04: /* TCR */
2122 OMAP_RO_REG(addr);
2123 break;
2124
2125 case 0x08: /* CR */
2126 s->timer.ar = (value >> 3) & 1;
2127 s->timer.it_ena = (value >> 2) & 1;
2128 if (s->timer.st != (value & 1) || (value & 2)) {
2129 omap_timer_sync(&s->timer);
2130 s->timer.enable = value & 1;
2131 s->timer.st = value & 1;
2132 omap_timer_update(&s->timer);
2133 }
2134 break;
2135
2136 default:
2137 OMAP_BAD_REG(addr);
2138 }
2139 }
2140
2141 static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
2142 omap_badwidth_read32,
2143 omap_badwidth_read32,
2144 omap_os_timer_read,
2145 };
2146
2147 static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
2148 omap_badwidth_write32,
2149 omap_badwidth_write32,
2150 omap_os_timer_write,
2151 };
2152
2153 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
2154 {
2155 qemu_del_timer(s->timer.timer);
2156 s->timer.enable = 0;
2157 s->timer.it_ena = 0;
2158 s->timer.reset_val = 0x00ffffff;
2159 s->timer.val = 0;
2160 s->timer.st = 0;
2161 s->timer.ptv = 0;
2162 s->timer.ar = 1;
2163 }
2164
2165 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
2166 qemu_irq irq, omap_clk clk)
2167 {
2168 int iomemtype;
2169 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
2170 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
2171
2172 s->timer.irq = irq;
2173 s->timer.clk = clk;
2174 s->timer.base = base;
2175 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
2176 omap_os_timer_reset(s);
2177 omap_timer_clk_setup(&s->timer);
2178
2179 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
2180 omap_os_timer_writefn, s);
2181 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
2182
2183 return s;
2184 }
2185
2186 /* Ultra Low-Power Device Module */
2187 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
2188 {
2189 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2190 int offset = addr - s->ulpd_pm_base;
2191 uint16_t ret;
2192
2193 switch (offset) {
2194 case 0x14: /* IT_STATUS */
2195 ret = s->ulpd_pm_regs[offset >> 2];
2196 s->ulpd_pm_regs[offset >> 2] = 0;
2197 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
2198 return ret;
2199
2200 case 0x18: /* Reserved */
2201 case 0x1c: /* Reserved */
2202 case 0x20: /* Reserved */
2203 case 0x28: /* Reserved */
2204 case 0x2c: /* Reserved */
2205 OMAP_BAD_REG(addr);
2206 case 0x00: /* COUNTER_32_LSB */
2207 case 0x04: /* COUNTER_32_MSB */
2208 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
2209 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
2210 case 0x10: /* GAUGING_CTRL */
2211 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
2212 case 0x30: /* CLOCK_CTRL */
2213 case 0x34: /* SOFT_REQ */
2214 case 0x38: /* COUNTER_32_FIQ */
2215 case 0x3c: /* DPLL_CTRL */
2216 case 0x40: /* STATUS_REQ */
2217 /* XXX: check clk::usecount state for every clock */
2218 case 0x48: /* LOCL_TIME */
2219 case 0x4c: /* APLL_CTRL */
2220 case 0x50: /* POWER_CTRL */
2221 return s->ulpd_pm_regs[offset >> 2];
2222 }
2223
2224 OMAP_BAD_REG(addr);
2225 return 0;
2226 }
2227
2228 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
2229 uint16_t diff, uint16_t value)
2230 {
2231 if (diff & (1 << 4)) /* USB_MCLK_EN */
2232 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
2233 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
2234 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
2235 }
2236
2237 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
2238 uint16_t diff, uint16_t value)
2239 {
2240 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
2241 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
2242 if (diff & (1 << 1)) /* SOFT_COM_REQ */
2243 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
2244 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
2245 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
2246 if (diff & (1 << 3)) /* SOFT_USB_REQ */
2247 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
2248 }
2249
2250 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
2251 uint32_t value)
2252 {
2253 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2254 int offset = addr - s->ulpd_pm_base;
2255 int64_t now, ticks;
2256 int div, mult;
2257 static const int bypass_div[4] = { 1, 2, 4, 4 };
2258 uint16_t diff;
2259
2260 switch (offset) {
2261 case 0x00: /* COUNTER_32_LSB */
2262 case 0x04: /* COUNTER_32_MSB */
2263 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
2264 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
2265 case 0x14: /* IT_STATUS */
2266 case 0x40: /* STATUS_REQ */
2267 OMAP_RO_REG(addr);
2268 break;
2269
2270 case 0x10: /* GAUGING_CTRL */
2271 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
2272 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
2273 now = qemu_get_clock(vm_clock);
2274
2275 if (value & 1)
2276 s->ulpd_gauge_start = now;
2277 else {
2278 now -= s->ulpd_gauge_start;
2279
2280 /* 32-kHz ticks */
2281 ticks = muldiv64(now, 32768, ticks_per_sec);
2282 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
2283 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
2284 if (ticks >> 32) /* OVERFLOW_32K */
2285 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
2286
2287 /* High frequency ticks */
2288 ticks = muldiv64(now, 12000000, ticks_per_sec);
2289 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
2290 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
2291 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
2292 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
2293
2294 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
2295 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
2296 }
2297 }
2298 s->ulpd_pm_regs[offset >> 2] = value;
2299 break;
2300
2301 case 0x18: /* Reserved */
2302 case 0x1c: /* Reserved */
2303 case 0x20: /* Reserved */
2304 case 0x28: /* Reserved */
2305 case 0x2c: /* Reserved */
2306 OMAP_BAD_REG(addr);
2307 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
2308 case 0x38: /* COUNTER_32_FIQ */
2309 case 0x48: /* LOCL_TIME */
2310 case 0x50: /* POWER_CTRL */
2311 s->ulpd_pm_regs[offset >> 2] = value;
2312 break;
2313
2314 case 0x30: /* CLOCK_CTRL */
2315 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
2316 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
2317 omap_ulpd_clk_update(s, diff, value);
2318 break;
2319
2320 case 0x34: /* SOFT_REQ */
2321 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
2322 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
2323 omap_ulpd_req_update(s, diff, value);
2324 break;
2325
2326 case 0x3c: /* DPLL_CTRL */
2327 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
2328 * omitted altogether, probably a typo. */
2329 /* This register has identical semantics with DPLL(1:3) control
2330 * registers, see omap_dpll_write() */
2331 diff = s->ulpd_pm_regs[offset >> 2] & value;
2332 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
2333 if (diff & (0x3ff << 2)) {
2334 if (value & (1 << 4)) { /* PLL_ENABLE */
2335 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
2336 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
2337 } else {
2338 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
2339 mult = 1;
2340 }
2341 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
2342 }
2343
2344 /* Enter the desired mode. */
2345 s->ulpd_pm_regs[offset >> 2] =
2346 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
2347 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
2348
2349 /* Act as if the lock is restored. */
2350 s->ulpd_pm_regs[offset >> 2] |= 2;
2351 break;
2352
2353 case 0x4c: /* APLL_CTRL */
2354 diff = s->ulpd_pm_regs[offset >> 2] & value;
2355 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
2356 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
2357 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
2358 (value & (1 << 0)) ? "apll" : "dpll4"));
2359 break;
2360
2361 default:
2362 OMAP_BAD_REG(addr);
2363 }
2364 }
2365
2366 static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
2367 omap_badwidth_read16,
2368 omap_ulpd_pm_read,
2369 omap_badwidth_read16,
2370 };
2371
2372 static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
2373 omap_badwidth_write16,
2374 omap_ulpd_pm_write,
2375 omap_badwidth_write16,
2376 };
2377
2378 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
2379 {
2380 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
2381 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
2382 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
2383 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
2384 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
2385 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
2386 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
2387 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
2388 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
2389 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
2390 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
2391 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
2392 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
2393 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
2394 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
2395 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
2396 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
2397 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
2398 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
2399 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
2400 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
2401 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
2402 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
2403 }
2404
2405 static void omap_ulpd_pm_init(target_phys_addr_t base,
2406 struct omap_mpu_state_s *mpu)
2407 {
2408 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
2409 omap_ulpd_pm_writefn, mpu);
2410
2411 mpu->ulpd_pm_base = base;
2412 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
2413 omap_ulpd_pm_reset(mpu);
2414 }
2415
2416 /* OMAP Pin Configuration */
2417 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
2418 {
2419 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2420 int offset = addr - s->pin_cfg_base;
2421
2422 switch (offset) {
2423 case 0x00: /* FUNC_MUX_CTRL_0 */
2424 case 0x04: /* FUNC_MUX_CTRL_1 */
2425 case 0x08: /* FUNC_MUX_CTRL_2 */
2426 return s->func_mux_ctrl[offset >> 2];
2427
2428 case 0x0c: /* COMP_MODE_CTRL_0 */
2429 return s->comp_mode_ctrl[0];
2430
2431 case 0x10: /* FUNC_MUX_CTRL_3 */
2432 case 0x14: /* FUNC_MUX_CTRL_4 */
2433 case 0x18: /* FUNC_MUX_CTRL_5 */
2434 case 0x1c: /* FUNC_MUX_CTRL_6 */
2435 case 0x20: /* FUNC_MUX_CTRL_7 */
2436 case 0x24: /* FUNC_MUX_CTRL_8 */
2437 case 0x28: /* FUNC_MUX_CTRL_9 */
2438 case 0x2c: /* FUNC_MUX_CTRL_A */
2439 case 0x30: /* FUNC_MUX_CTRL_B */
2440 case 0x34: /* FUNC_MUX_CTRL_C */
2441 case 0x38: /* FUNC_MUX_CTRL_D */
2442 return s->func_mux_ctrl[(offset >> 2) - 1];
2443
2444 case 0x40: /* PULL_DWN_CTRL_0 */
2445 case 0x44: /* PULL_DWN_CTRL_1 */
2446 case 0x48: /* PULL_DWN_CTRL_2 */
2447 case 0x4c: /* PULL_DWN_CTRL_3 */
2448 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
2449
2450 case 0x50: /* GATE_INH_CTRL_0 */
2451 return s->gate_inh_ctrl[0];
2452
2453 case 0x60: /* VOLTAGE_CTRL_0 */
2454 return s->voltage_ctrl[0];
2455
2456 case 0x70: /* TEST_DBG_CTRL_0 */
2457 return s->test_dbg_ctrl[0];
2458
2459 case 0x80: /* MOD_CONF_CTRL_0 */
2460 return s->mod_conf_ctrl[0];
2461 }
2462
2463 OMAP_BAD_REG(addr);
2464 return 0;
2465 }
2466
2467 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
2468 uint32_t diff, uint32_t value)
2469 {
2470 if (s->compat1509) {
2471 if (diff & (1 << 9)) /* BLUETOOTH */
2472 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
2473 (~value >> 9) & 1);
2474 if (diff & (1 << 7)) /* USB.CLKO */
2475 omap_clk_onoff(omap_findclk(s, "usb.clko"),
2476 (value >> 7) & 1);
2477 }
2478 }
2479
2480 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
2481 uint32_t diff, uint32_t value)
2482 {
2483 if (s->compat1509) {
2484 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
2485 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
2486 (value >> 31) & 1);
2487 if (diff & (1 << 1)) /* CLK32K */
2488 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
2489 (~value >> 1) & 1);
2490 }
2491 }
2492
2493 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
2494 uint32_t diff, uint32_t value)
2495 {
2496 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
2497 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
2498 omap_findclk(s, ((value >> 31) & 1) ?
2499 "ck_48m" : "armper_ck"));
2500 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
2501 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
2502 omap_findclk(s, ((value >> 30) & 1) ?
2503 "ck_48m" : "armper_ck"));
2504 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
2505 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
2506 omap_findclk(s, ((value >> 29) & 1) ?
2507 "ck_48m" : "armper_ck"));
2508 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
2509 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
2510 omap_findclk(s, ((value >> 23) & 1) ?
2511 "ck_48m" : "armper_ck"));
2512 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
2513 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
2514 omap_findclk(s, ((value >> 12) & 1) ?
2515 "ck_48m" : "armper_ck"));
2516 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
2517 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
2518 }
2519
2520 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
2521 uint32_t value)
2522 {
2523 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2524 int offset = addr - s->pin_cfg_base;
2525 uint32_t diff;
2526
2527 switch (offset) {
2528 case 0x00: /* FUNC_MUX_CTRL_0 */
2529 diff = s->func_mux_ctrl[offset >> 2] ^ value;
2530 s->func_mux_ctrl[offset >> 2] = value;
2531 omap_pin_funcmux0_update(s, diff, value);
2532 return;
2533
2534 case 0x04: /* FUNC_MUX_CTRL_1 */
2535 diff = s->func_mux_ctrl[offset >> 2] ^ value;
2536 s->func_mux_ctrl[offset >> 2] = value;
2537 omap_pin_funcmux1_update(s, diff, value);
2538 return;
2539
2540 case 0x08: /* FUNC_MUX_CTRL_2 */
2541 s->func_mux_ctrl[offset >> 2] = value;
2542 return;
2543
2544 case 0x0c: /* COMP_MODE_CTRL_0 */
2545 s->comp_mode_ctrl[0] = value;
2546 s->compat1509 = (value != 0x0000eaef);
2547 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
2548 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
2549 return;
2550
2551 case 0x10: /* FUNC_MUX_CTRL_3 */
2552 case 0x14: /* FUNC_MUX_CTRL_4 */
2553 case 0x18: /* FUNC_MUX_CTRL_5 */
2554 case 0x1c: /* FUNC_MUX_CTRL_6 */
2555 case 0x20: /* FUNC_MUX_CTRL_7 */
2556 case 0x24: /* FUNC_MUX_CTRL_8 */
2557 case 0x28: /* FUNC_MUX_CTRL_9 */
2558 case 0x2c: /* FUNC_MUX_CTRL_A */
2559 case 0x30: /* FUNC_MUX_CTRL_B */
2560 case 0x34: /* FUNC_MUX_CTRL_C */
2561 case 0x38: /* FUNC_MUX_CTRL_D */
2562 s->func_mux_ctrl[(offset >> 2) - 1] = value;
2563 return;
2564
2565 case 0x40: /* PULL_DWN_CTRL_0 */
2566 case 0x44: /* PULL_DWN_CTRL_1 */
2567 case 0x48: /* PULL_DWN_CTRL_2 */
2568 case 0x4c: /* PULL_DWN_CTRL_3 */
2569 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
2570 return;
2571
2572 case 0x50: /* GATE_INH_CTRL_0 */
2573 s->gate_inh_ctrl[0] = value;
2574 return;
2575
2576 case 0x60: /* VOLTAGE_CTRL_0 */
2577 s->voltage_ctrl[0] = value;
2578 return;
2579
2580 case 0x70: /* TEST_DBG_CTRL_0 */
2581 s->test_dbg_ctrl[0] = value;
2582 return;
2583
2584 case 0x80: /* MOD_CONF_CTRL_0 */
2585 diff = s->mod_conf_ctrl[0] ^ value;
2586 s->mod_conf_ctrl[0] = value;
2587 omap_pin_modconf1_update(s, diff, value);
2588 return;
2589
2590 default:
2591 OMAP_BAD_REG(addr);
2592 }
2593 }
2594
2595 static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
2596 omap_badwidth_read32,
2597 omap_badwidth_read32,
2598 omap_pin_cfg_read,
2599 };
2600
2601 static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
2602 omap_badwidth_write32,
2603 omap_badwidth_write32,
2604 omap_pin_cfg_write,
2605 };
2606
2607 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
2608 {
2609 /* Start in Compatibility Mode. */
2610 mpu->compat1509 = 1;
2611 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
2612 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
2613 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
2614 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
2615 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
2616 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
2617 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
2618 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
2619 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
2620 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
2621 }
2622
2623 static void omap_pin_cfg_init(target_phys_addr_t base,
2624 struct omap_mpu_state_s *mpu)
2625 {
2626 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
2627 omap_pin_cfg_writefn, mpu);
2628
2629 mpu->pin_cfg_base = base;
2630 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
2631 omap_pin_cfg_reset(mpu);
2632 }
2633
2634 /* Device Identification, Die Identification */
2635 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
2636 {
2637 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2638
2639 switch (addr) {
2640 case 0xfffe1800: /* DIE_ID_LSB */
2641 return 0xc9581f0e;
2642 case 0xfffe1804: /* DIE_ID_MSB */
2643 return 0xa8858bfa;
2644
2645 case 0xfffe2000: /* PRODUCT_ID_LSB */
2646 return 0x00aaaafc;
2647 case 0xfffe2004: /* PRODUCT_ID_MSB */
2648 return 0xcafeb574;
2649
2650 case 0xfffed400: /* JTAG_ID_LSB */
2651 switch (s->mpu_model) {
2652 case omap310:
2653 return 0x03310315;
2654 case omap1510:
2655 return 0x03310115;
2656 }
2657 break;
2658
2659 case 0xfffed404: /* JTAG_ID_MSB */
2660 switch (s->mpu_model) {
2661 case omap310:
2662 return 0xfb57402f;
2663 case omap1510:
2664 return 0xfb47002f;
2665 }
2666 break;
2667 }
2668
2669 OMAP_BAD_REG(addr);
2670 return 0;
2671 }
2672
2673 static void omap_id_write(void *opaque, target_phys_addr_t addr,
2674 uint32_t value)
2675 {
2676 OMAP_BAD_REG(addr);
2677 }
2678
2679 static CPUReadMemoryFunc *omap_id_readfn[] = {
2680 omap_badwidth_read32,
2681 omap_badwidth_read32,
2682 omap_id_read,
2683 };
2684
2685 static CPUWriteMemoryFunc *omap_id_writefn[] = {
2686 omap_badwidth_write32,
2687 omap_badwidth_write32,
2688 omap_id_write,
2689 };
2690
2691 static void omap_id_init(struct omap_mpu_state_s *mpu)
2692 {
2693 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
2694 omap_id_writefn, mpu);
2695 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
2696 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
2697 if (!cpu_is_omap15xx(mpu))
2698 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
2699 }
2700
2701 /* MPUI Control (Dummy) */
2702 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
2703 {
2704 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2705 int offset = addr - s->mpui_base;
2706
2707 switch (offset) {
2708 case 0x00: /* CTRL */
2709 return s->mpui_ctrl;
2710 case 0x04: /* DEBUG_ADDR */
2711 return 0x01ffffff;
2712 case 0x08: /* DEBUG_DATA */
2713 return 0xffffffff;
2714 case 0x0c: /* DEBUG_FLAG */
2715 return 0x00000800;
2716 case 0x10: /* STATUS */
2717 return 0x00000000;
2718
2719 /* Not in OMAP310 */
2720 case 0x14: /* DSP_STATUS */
2721 case 0x18: /* DSP_BOOT_CONFIG */
2722 return 0x00000000;
2723 case 0x1c: /* DSP_MPUI_CONFIG */
2724 return 0x0000ffff;
2725 }
2726
2727 OMAP_BAD_REG(addr);
2728 return 0;
2729 }
2730
2731 static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
2732 uint32_t value)
2733 {
2734 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2735 int offset = addr - s->mpui_base;
2736
2737 switch (offset) {
2738 case 0x00: /* CTRL */
2739 s->mpui_ctrl = value & 0x007fffff;
2740 break;
2741
2742 case 0x04: /* DEBUG_ADDR */
2743 case 0x08: /* DEBUG_DATA */
2744 case 0x0c: /* DEBUG_FLAG */
2745 case 0x10: /* STATUS */
2746 /* Not in OMAP310 */
2747 case 0x14: /* DSP_STATUS */
2748 OMAP_RO_REG(addr);
2749 case 0x18: /* DSP_BOOT_CONFIG */
2750 case 0x1c: /* DSP_MPUI_CONFIG */
2751 break;
2752
2753 default:
2754 OMAP_BAD_REG(addr);
2755 }
2756 }
2757
2758 static CPUReadMemoryFunc *omap_mpui_readfn[] = {
2759 omap_badwidth_read32,
2760 omap_badwidth_read32,
2761 omap_mpui_read,
2762 };
2763
2764 static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
2765 omap_badwidth_write32,
2766 omap_badwidth_write32,
2767 omap_mpui_write,
2768 };
2769
2770 static void omap_mpui_reset(struct omap_mpu_state_s *s)
2771 {
2772 s->mpui_ctrl = 0x0003ff1b;
2773 }
2774
2775 static void omap_mpui_init(target_phys_addr_t base,
2776 struct omap_mpu_state_s *mpu)
2777 {
2778 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
2779 omap_mpui_writefn, mpu);
2780
2781 mpu->mpui_base = base;
2782 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
2783
2784 omap_mpui_reset(mpu);
2785 }
2786
2787 /* TIPB Bridges */
2788 struct omap_tipb_bridge_s {
2789 target_phys_addr_t base;
2790 qemu_irq abort;
2791
2792 int width_intr;
2793 uint16_t control;
2794 uint16_t alloc;
2795 uint16_t buffer;
2796 uint16_t enh_control;
2797 };
2798
2799 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
2800 {
2801 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
2802 int offset = addr - s->base;
2803
2804 switch (offset) {
2805 case 0x00: /* TIPB_CNTL */
2806 return s->control;
2807 case 0x04: /* TIPB_BUS_ALLOC */
2808 return s->alloc;
2809 case 0x08: /* MPU_TIPB_CNTL */
2810 return s->buffer;
2811 case 0x0c: /* ENHANCED_TIPB_CNTL */
2812 return s->enh_control;
2813 case 0x10: /* ADDRESS_DBG */
2814 case 0x14: /* DATA_DEBUG_LOW */
2815 case 0x18: /* DATA_DEBUG_HIGH */
2816 return 0xffff;
2817 case 0x1c: /* DEBUG_CNTR_SIG */
2818 return 0x00f8;
2819 }
2820
2821 OMAP_BAD_REG(addr);
2822 return 0;
2823 }
2824
2825 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
2826 uint32_t value)
2827 {
2828 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
2829 int offset = addr - s->base;
2830
2831 switch (offset) {
2832 case 0x00: /* TIPB_CNTL */
2833 s->control = value & 0xffff;
2834 break;
2835
2836 case 0x04: /* TIPB_BUS_ALLOC */
2837 s->alloc = value & 0x003f;
2838 break;
2839
2840 case 0x08: /* MPU_TIPB_CNTL */
2841 s->buffer = value & 0x0003;
2842 break;
2843
2844 case 0x0c: /* ENHANCED_TIPB_CNTL */
2845 s->width_intr = !(value & 2);
2846 s->enh_control = value & 0x000f;
2847 break;
2848
2849 case 0x10: /* ADDRESS_DBG */
2850 case 0x14: /* DATA_DEBUG_LOW */
2851 case 0x18: /* DATA_DEBUG_HIGH */
2852 case 0x1c: /* DEBUG_CNTR_SIG */
2853 OMAP_RO_REG(addr);
2854 break;
2855
2856 default:
2857 OMAP_BAD_REG(addr);
2858 }
2859 }
2860
2861 static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
2862 omap_badwidth_read16,
2863 omap_tipb_bridge_read,
2864 omap_tipb_bridge_read,
2865 };
2866
2867 static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
2868 omap_badwidth_write16,
2869 omap_tipb_bridge_write,
2870 omap_tipb_bridge_write,
2871 };
2872
2873 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
2874 {
2875 s->control = 0xffff;
2876 s->alloc = 0x0009;
2877 s->buffer = 0x0000;
2878 s->enh_control = 0x000f;
2879 }
2880
2881 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
2882 qemu_irq abort_irq, omap_clk clk)
2883 {
2884 int iomemtype;
2885 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
2886 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
2887
2888 s->abort = abort_irq;
2889 s->base = base;
2890 omap_tipb_bridge_reset(s);
2891
2892 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
2893 omap_tipb_bridge_writefn, s);
2894 cpu_register_physical_memory(s->base, 0x100, iomemtype);
2895
2896 return s;
2897 }
2898
2899 /* Dummy Traffic Controller's Memory Interface */
2900 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
2901 {
2902 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2903 int offset = addr - s->tcmi_base;
2904 uint32_t ret;
2905
2906 switch (offset) {
2907 case 0x00: /* IMIF_PRIO */
2908 case 0x04: /* EMIFS_PRIO */
2909 case 0x08: /* EMIFF_PRIO */
2910 case 0x0c: /* EMIFS_CONFIG */
2911 case 0x10: /* EMIFS_CS0_CONFIG */
2912 case 0x14: /* EMIFS_CS1_CONFIG */
2913 case 0x18: /* EMIFS_CS2_CONFIG */
2914 case 0x1c: /* EMIFS_CS3_CONFIG */
2915 case 0x24: /* EMIFF_MRS */
2916 case 0x28: /* TIMEOUT1 */
2917 case 0x2c: /* TIMEOUT2 */
2918 case 0x30: /* TIMEOUT3 */
2919 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
2920 case 0x40: /* EMIFS_CFG_DYN_WAIT */
2921 return s->tcmi_regs[offset >> 2];
2922
2923 case 0x20: /* EMIFF_SDRAM_CONFIG */
2924 ret = s->tcmi_regs[offset >> 2];
2925 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
2926 /* XXX: We can try using the VGA_DIRTY flag for this */
2927 return ret;
2928 }
2929
2930 OMAP_BAD_REG(addr);
2931 return 0;
2932 }
2933
2934 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
2935 uint32_t value)
2936 {
2937 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2938 int offset = addr - s->tcmi_base;
2939
2940 switch (offset) {
2941 case 0x00: /* IMIF_PRIO */
2942 case 0x04: /* EMIFS_PRIO */
2943 case 0x08: /* EMIFF_PRIO */
2944 case 0x10: /* EMIFS_CS0_CONFIG */
2945 case 0x14: /* EMIFS_CS1_CONFIG */
2946 case 0x18: /* EMIFS_CS2_CONFIG */
2947 case 0x1c: /* EMIFS_CS3_CONFIG */
2948 case 0x20: /* EMIFF_SDRAM_CONFIG */
2949 case 0x24: /* EMIFF_MRS */
2950 case 0x28: /* TIMEOUT1 */
2951 case 0x2c: /* TIMEOUT2 */
2952 case 0x30: /* TIMEOUT3 */
2953 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
2954 case 0x40: /* EMIFS_CFG_DYN_WAIT */
2955 s->tcmi_regs[offset >> 2] = value;
2956 break;
2957 case 0x0c: /* EMIFS_CONFIG */
2958 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
2959 break;
2960
2961 default:
2962 OMAP_BAD_REG(addr);
2963 }
2964 }
2965
2966 static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
2967 omap_badwidth_read32,
2968 omap_badwidth_read32,
2969 omap_tcmi_read,
2970 };
2971
2972 static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
2973 omap_badwidth_write32,
2974 omap_badwidth_write32,
2975 omap_tcmi_write,
2976 };
2977
2978 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
2979 {
2980 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
2981 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
2982 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
2983 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
2984 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
2985 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
2986 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
2987 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
2988 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
2989 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
2990 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
2991 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
2992 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
2993 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
2994 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
2995 }
2996
2997 static void omap_tcmi_init(target_phys_addr_t base,
2998 struct omap_mpu_state_s *mpu)
2999 {
3000 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
3001 omap_tcmi_writefn, mpu);
3002
3003 mpu->tcmi_base = base;
3004 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
3005 omap_tcmi_reset(mpu);
3006 }
3007
3008 /* Digital phase-locked loops control */
3009 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
3010 {
3011 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
3012 int offset = addr - s->base;
3013
3014 if (offset == 0x00) /* CTL_REG */
3015 return s->mode;
3016
3017 OMAP_BAD_REG(addr);
3018 return 0;
3019 }
3020
3021 static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
3022 uint32_t value)
3023 {
3024 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
3025 uint16_t diff;
3026 int offset = addr - s->base;
3027 static const int bypass_div[4] = { 1, 2, 4, 4 };
3028 int div, mult;
3029
3030 if (offset == 0x00) { /* CTL_REG */
3031 /* See omap_ulpd_pm_write() too */
3032 diff = s->mode & value;
3033 s->mode = value & 0x2fff;
3034 if (diff & (0x3ff << 2)) {
3035 if (value & (1 << 4)) { /* PLL_ENABLE */
3036 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
3037 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
3038 } else {
3039 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
3040 mult = 1;
3041 }
3042 omap_clk_setrate(s->dpll, div, mult);
3043 }
3044
3045 /* Enter the desired mode. */
3046 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
3047
3048 /* Act as if the lock is restored. */
3049 s->mode |= 2;
3050 } else {
3051 OMAP_BAD_REG(addr);
3052 }
3053 }
3054
3055 static CPUReadMemoryFunc *omap_dpll_readfn[] = {
3056 omap_badwidth_read16,
3057 omap_dpll_read,
3058 omap_badwidth_read16,
3059 };
3060
3061 static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
3062 omap_badwidth_write16,
3063 omap_dpll_write,
3064 omap_badwidth_write16,
3065 };
3066
3067 static void omap_dpll_reset(struct dpll_ctl_s *s)
3068 {
3069 s->mode = 0x2002;
3070 omap_clk_setrate(s->dpll, 1, 1);
3071 }
3072
3073 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
3074 omap_clk clk)
3075 {
3076 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
3077 omap_dpll_writefn, s);
3078
3079 s->base = base;
3080 s->dpll = clk;
3081 omap_dpll_reset(s);
3082
3083 cpu_register_physical_memory(s->base, 0x100, iomemtype);
3084 }
3085
3086 /* UARTs */
3087 struct omap_uart_s {
3088 SerialState *serial; /* TODO */
3089 };
3090
3091 static void omap_uart_reset(struct omap_uart_s *s)
3092 {
3093 }
3094
3095 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
3096 qemu_irq irq, omap_clk clk, CharDriverState *chr)
3097 {
3098 struct omap_uart_s *s = (struct omap_uart_s *)
3099 qemu_mallocz(sizeof(struct omap_uart_s));
3100 if (chr)
3101 s->serial = serial_mm_init(base, 2, irq, chr, 1);
3102 return s;
3103 }
3104
3105 /* MPU Clock/Reset/Power Mode Control */
3106 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
3107 {
3108 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3109 int offset = addr - s->clkm.mpu_base;
3110
3111 switch (offset) {
3112 case 0x00: /* ARM_CKCTL */
3113 return s->clkm.arm_ckctl;
3114
3115 case 0x04: /* ARM_IDLECT1 */
3116 return s->clkm.arm_idlect1;
3117
3118 case 0x08: /* ARM_IDLECT2 */
3119 return s->clkm.arm_idlect2;
3120
3121 case 0x0c: /* ARM_EWUPCT */
3122 return s->clkm.arm_ewupct;
3123
3124 case 0x10: /* ARM_RSTCT1 */
3125 return s->clkm.arm_rstct1;
3126
3127 case 0x14: /* ARM_RSTCT2 */
3128 return s->clkm.arm_rstct2;
3129
3130 case 0x18: /* ARM_SYSST */
3131 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
3132
3133 case 0x1c: /* ARM_CKOUT1 */
3134 return s->clkm.arm_ckout1;
3135
3136 case 0x20: /* ARM_CKOUT2 */
3137 break;
3138 }
3139
3140 OMAP_BAD_REG(addr);
3141 return 0;
3142 }
3143
3144 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
3145 uint16_t diff, uint16_t value)
3146 {
3147 omap_clk clk;
3148
3149 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
3150 if (value & (1 << 14))
3151 /* Reserved */;
3152 else {
3153 clk = omap_findclk(s, "arminth_ck");
3154 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
3155 }
3156 }
3157 if (diff & (1 << 12)) { /* ARM_TIMXO */
3158 clk = omap_findclk(s, "armtim_ck");
3159 if (value & (1 << 12))
3160 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
3161 else
3162 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
3163 }
3164 /* XXX: en_dspck */
3165 if (diff & (3 << 10)) { /* DSPMMUDIV */
3166 clk = omap_findclk(s, "dspmmu_ck");
3167 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
3168 }
3169 if (diff & (3 << 8)) { /* TCDIV */
3170 clk = omap_findclk(s, "tc_ck");
3171 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
3172 }
3173 if (diff & (3 << 6)) { /* DSPDIV */
3174 clk = omap_findclk(s, "dsp_ck");
3175 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
3176 }
3177 if (diff & (3 << 4)) { /* ARMDIV */
3178 clk = omap_findclk(s, "arm_ck");
3179 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
3180 }
3181 if (diff & (3 << 2)) { /* LCDDIV */
3182 clk = omap_findclk(s, "lcd_ck");
3183 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
3184 }
3185 if (diff & (3 << 0)) { /* PERDIV */
3186 clk = omap_findclk(s, "armper_ck");
3187 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
3188 }
3189 }
3190
3191 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
3192 uint16_t diff, uint16_t value)
3193 {
3194 omap_clk clk;
3195
3196 if (value & (1 << 11)) /* SETARM_IDLE */
3197 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
3198 if (!(value & (1 << 10))) /* WKUP_MODE */
3199 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
3200
3201 #define SET_CANIDLE(clock, bit) \
3202 if (diff & (1 << bit)) { \
3203 clk = omap_findclk(s, clock); \
3204 omap_clk_canidle(clk, (value >> bit) & 1); \
3205 }
3206 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
3207 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
3208 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
3209 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
3210 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
3211 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
3212 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
3213 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
3214 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
3215 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
3216 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
3217 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
3218 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
3219 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
3220 }
3221
3222 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
3223 uint16_t diff, uint16_t value)
3224 {
3225 omap_clk clk;
3226
3227 #define SET_ONOFF(clock, bit) \
3228 if (diff & (1 << bit)) { \
3229 clk = omap_findclk(s, clock); \
3230 omap_clk_onoff(clk, (value >> bit) & 1); \
3231 }
3232 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
3233 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
3234 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
3235 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
3236 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
3237 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
3238 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
3239 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
3240 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
3241 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
3242 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
3243 }
3244
3245 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
3246 uint16_t diff, uint16_t value)
3247 {
3248 omap_clk clk;
3249
3250 if (diff & (3 << 4)) { /* TCLKOUT */
3251 clk = omap_findclk(s, "tclk_out");
3252 switch ((value >> 4) & 3) {
3253 case 1:
3254 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
3255 omap_clk_onoff(clk, 1);
3256 break;
3257 case 2:
3258 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
3259 omap_clk_onoff(clk, 1);
3260 break;
3261 default:
3262 omap_clk_onoff(clk, 0);
3263 }
3264 }
3265 if (diff & (3 << 2)) { /* DCLKOUT */
3266 clk = omap_findclk(s, "dclk_out");
3267 switch ((value >> 2) & 3) {
3268 case 0:
3269 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
3270 break;
3271 case 1:
3272 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
3273 break;
3274 case 2:
3275 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
3276 break;
3277 case 3:
3278 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
3279 break;
3280 }
3281 }
3282 if (diff & (3 << 0)) { /* ACLKOUT */
3283 clk = omap_findclk(s, "aclk_out");
3284 switch ((value >> 0) & 3) {
3285 case 1:
3286 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
3287 omap_clk_onoff(clk, 1);
3288 break;
3289 case 2:
3290 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
3291 omap_clk_onoff(clk, 1);
3292 break;
3293 case 3:
3294 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
3295 omap_clk_onoff(clk, 1);
3296 break;
3297 default:
3298 omap_clk_onoff(clk, 0);
3299 }
3300 }
3301 }
3302
3303 static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
3304 uint32_t value)
3305 {
3306 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3307 int offset = addr - s->clkm.mpu_base;
3308 uint16_t diff;
3309 omap_clk clk;
3310 static const char *clkschemename[8] = {
3311 "fully synchronous", "fully asynchronous", "synchronous scalable",
3312 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
3313 };
3314
3315 switch (offset) {
3316 case 0x00: /* ARM_CKCTL */
3317 diff = s->clkm.arm_ckctl ^ value;
3318 s->clkm.arm_ckctl = value & 0x7fff;
3319 omap_clkm_ckctl_update(s, diff, value);
3320 return;
3321
3322 case 0x04: /* ARM_IDLECT1 */
3323 diff = s->clkm.arm_idlect1 ^ value;
3324 s->clkm.arm_idlect1 = value & 0x0fff;
3325 omap_clkm_idlect1_update(s, diff, value);
3326 return;
3327
3328 case 0x08: /* ARM_IDLECT2 */
3329 diff = s->clkm.arm_idlect2 ^ value;
3330 s->clkm.arm_idlect2 = value & 0x07ff;
3331 omap_clkm_idlect2_update(s, diff, value);
3332 return;
3333
3334 case 0x0c: /* ARM_EWUPCT */
3335 diff = s->clkm.arm_ewupct ^ value;
3336 s->clkm.arm_ewupct = value & 0x003f;
3337 return;
3338
3339 case 0x10: /* ARM_RSTCT1 */
3340 diff = s->clkm.arm_rstct1 ^ value;
3341 s->clkm.arm_rstct1 = value & 0x0007;
3342 if (value & 9) {
3343 qemu_system_reset_request();
3344 s->clkm.cold_start = 0xa;
3345 }
3346 if (diff & ~value & 4) { /* DSP_RST */
3347 omap_mpui_reset(s);
3348 omap_tipb_bridge_reset(s->private_tipb);
3349 omap_tipb_bridge_reset(s->public_tipb);
3350 }
3351 if (diff & 2) { /* DSP_EN */
3352 clk = omap_findclk(s, "dsp_ck");
3353 omap_clk_canidle(clk, (~value >> 1) & 1);
3354 }
3355 return;
3356
3357 case 0x14: /* ARM_RSTCT2 */
3358 s->clkm.arm_rstct2 = value & 0x0001;
3359 return;
3360
3361 case 0x18: /* ARM_SYSST */
3362 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
3363 s->clkm.clocking_scheme = (value >> 11) & 7;
3364 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
3365 clkschemename[s->clkm.clocking_scheme]);
3366 }
3367 s->clkm.cold_start &= value & 0x3f;
3368 return;
3369
3370 case 0x1c: /* ARM_CKOUT1 */
3371 diff = s->clkm.arm_ckout1 ^ value;
3372 s->clkm.arm_ckout1 = value & 0x003f;
3373 omap_clkm_ckout1_update(s, diff, value);
3374 return;
3375
3376 case 0x20: /* ARM_CKOUT2 */
3377 default:
3378 OMAP_BAD_REG(addr);
3379 }
3380 }
3381
3382 static CPUReadMemoryFunc *omap_clkm_readfn[] = {
3383 omap_badwidth_read16,
3384 omap_clkm_read,
3385 omap_badwidth_read16,
3386 };
3387
3388 static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
3389 omap_badwidth_write16,
3390 omap_clkm_write,
3391 omap_badwidth_write16,
3392 };
3393
3394 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
3395 {
3396 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3397 int offset = addr - s->clkm.dsp_base;
3398
3399 switch (offset) {
3400 case 0x04: /* DSP_IDLECT1 */
3401 return s->clkm.dsp_idlect1;
3402
3403 case 0x08: /* DSP_IDLECT2 */
3404 return s->clkm.dsp_idlect2;
3405
3406 case 0x14: /* DSP_RSTCT2 */
3407 return s->clkm.dsp_rstct2;
3408
3409 case 0x18: /* DSP_SYSST */
3410 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
3411 (s->env->halted << 6); /* Quite useless... */
3412 }
3413
3414 OMAP_BAD_REG(addr);
3415 return 0;
3416 }
3417
3418 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
3419 uint16_t diff, uint16_t value)
3420 {
3421 omap_clk clk;
3422
3423 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
3424 }
3425
3426 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
3427 uint16_t diff, uint16_t value)
3428 {
3429 omap_clk clk;
3430
3431 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
3432 }
3433
3434 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
3435 uint32_t value)
3436 {
3437 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3438 int offset = addr - s->clkm.dsp_base;
3439 uint16_t diff;
3440
3441 switch (offset) {
3442 case 0x04: /* DSP_IDLECT1 */
3443 diff = s->clkm.dsp_idlect1 ^ value;
3444 s->clkm.dsp_idlect1 = value & 0x01f7;
3445 omap_clkdsp_idlect1_update(s, diff, value);
3446 break;
3447
3448 case 0x08: /* DSP_IDLECT2 */
3449 s->clkm.dsp_idlect2 = value & 0x0037;
3450 diff = s->clkm.dsp_idlect1 ^ value;
3451 omap_clkdsp_idlect2_update(s, diff, value);
3452 break;
3453
3454 case 0x14: /* DSP_RSTCT2 */
3455 s->clkm.dsp_rstct2 = value & 0x0001;
3456 break;
3457
3458 case 0x18: /* DSP_SYSST */
3459 s->clkm.cold_start &= value & 0x3f;
3460 break;
3461
3462 default:
3463 OMAP_BAD_REG(addr);
3464 }
3465 }
3466
3467 static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
3468 omap_badwidth_read16,
3469 omap_clkdsp_read,
3470 omap_badwidth_read16,
3471 };
3472
3473 static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
3474 omap_badwidth_write16,
3475 omap_clkdsp_write,
3476 omap_badwidth_write16,
3477 };
3478
3479 static void omap_clkm_reset(struct omap_mpu_state_s *s)
3480 {
3481 if (s->wdt && s->wdt->reset)
3482 s->clkm.cold_start = 0x6;
3483 s->clkm.clocking_scheme = 0;
3484 omap_clkm_ckctl_update(s, ~0, 0x3000);
3485 s->clkm.arm_ckctl = 0x3000;
3486 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
3487 s->clkm.arm_idlect1 = 0x0400;
3488 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
3489 s->clkm.arm_idlect2 = 0x0100;
3490 s->clkm.arm_ewupct = 0x003f;
3491 s->clkm.arm_rstct1 = 0x0000;
3492 s->clkm.arm_rstct2 = 0x0000;
3493 s->clkm.arm_ckout1 = 0x0015;
3494 s->clkm.dpll1_mode = 0x2002;
3495 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
3496 s->clkm.dsp_idlect1 = 0x0040;
3497 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
3498 s->clkm.dsp_idlect2 = 0x0000;
3499 s->clkm.dsp_rstct2 = 0x0000;
3500 }
3501
3502 static void omap_clkm_init(target_phys_addr_t mpu_base,
3503 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
3504 {
3505 int iomemtype[2] = {
3506 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
3507 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
3508 };
3509
3510 s->clkm.mpu_base = mpu_base;
3511 s->clkm.dsp_base = dsp_base;
3512 s->clkm.arm_idlect1 = 0x03ff;
3513 s->clkm.arm_idlect2 = 0x0100;
3514 s->clkm.dsp_idlect1 = 0x0002;
3515 omap_clkm_reset(s);
3516 s->clkm.cold_start = 0x3a;
3517
3518 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
3519 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
3520 }
3521
3522 /* MPU I/O */
3523 struct omap_mpuio_s {
3524 target_phys_addr_t base;
3525 qemu_irq irq;
3526 qemu_irq kbd_irq;
3527 qemu_irq *in;
3528 qemu_irq handler[16];
3529 qemu_irq wakeup;
3530
3531 uint16_t inputs;
3532 uint16_t outputs;
3533 uint16_t dir;
3534 uint16_t edge;
3535 uint16_t mask;
3536 uint16_t ints;
3537
3538 uint16_t debounce;
3539 uint16_t latch;
3540 uint8_t event;
3541
3542 uint8_t buttons[5];
3543 uint8_t row_latch;
3544 uint8_t cols;
3545 int kbd_mask;
3546 int clk;
3547 };
3548
3549 static void omap_mpuio_set(void *opaque, int line, int level)
3550 {
3551 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
3552 uint16_t prev = s->inputs;
3553
3554 if (level)
3555 s->inputs |= 1 << line;
3556 else
3557 s->inputs &= ~(1 << line);
3558
3559 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
3560 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
3561 s->ints |= 1 << line;
3562 qemu_irq_raise(s->irq);
3563 /* TODO: wakeup */
3564 }
3565 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
3566 (s->event >> 1) == line) /* PIN_SELECT */
3567 s->latch = s->inputs;
3568 }
3569 }
3570
3571 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
3572 {
3573 int i;
3574 uint8_t *row, rows = 0, cols = ~s->cols;
3575
3576 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
3577 if (*row & cols)
3578 rows |= i;
3579
3580 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
3581 s->row_latch = ~rows;
3582 }
3583
3584 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
3585 {
3586 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
3587 int offset = addr & OMAP_MPUI_REG_MASK;
3588 uint16_t ret;
3589
3590 switch (offset) {
3591 case 0x00: /* INPUT_LATCH */
3592 return s->inputs;
3593
3594 case 0x04: /* OUTPUT_REG */
3595 return s->outputs;
3596
3597 case 0x08: /* IO_CNTL */
3598 return s->dir;
3599
3600 case 0x10: /* KBR_LATCH */
3601 return s->row_latch;
3602
3603 case 0x14: /* KBC_REG */
3604 return s->cols;
3605
3606 case 0x18: /* GPIO_EVENT_MODE_REG */
3607 return s->event;
3608
3609 case 0x1c: /* GPIO_INT_EDGE_REG */
3610 return s->edge;
3611
3612 case 0x20: /* KBD_INT */
3613 return (~s->row_latch & 0x1f) && !s->kbd_mask;
3614
3615 case 0x24: /* GPIO_INT */
3616 ret = s->ints;
3617 s->ints &= s->mask;
3618 if (ret)
3619 qemu_irq_lower(s->irq);
3620 return ret;
3621
3622 case 0x28: /* KBD_MASKIT */
3623 return s->kbd_mask;
3624
3625 case 0x2c: /* GPIO_MASKIT */
3626 return s->mask;
3627
3628 case 0x30: /* GPIO_DEBOUNCING_REG */
3629 return s->debounce;
3630
3631 case 0x34: /* GPIO_LATCH_REG */
3632 return s->latch;
3633 }
3634
3635 OMAP_BAD_REG(addr);
3636 return 0;
3637 }
3638
3639 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
3640 uint32_t value)
3641 {
3642 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
3643 int offset = addr & OMAP_MPUI_REG_MASK;
3644 uint16_t diff;
3645 int ln;
3646
3647 switch (offset) {
3648 case 0x04: /* OUTPUT_REG */
3649 diff = (s->outputs ^ value) & ~s->dir;
3650 s->outputs = value;
3651 while ((ln = ffs(diff))) {
3652 ln --;
3653 if (s->handler[ln])
3654 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
3655 diff &= ~(1 << ln);
3656 }
3657 break;
3658
3659 case 0x08: /* IO_CNTL */
3660 diff = s->outputs & (s->dir ^ value);
3661 s->dir = value;
3662
3663 value = s->outputs & ~s->dir;
3664 while ((ln = ffs(diff))) {
3665 ln --;
3666 if (s->handler[ln])
3667 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
3668 diff &= ~(1 << ln);
3669 }
3670 break;
3671
3672 case 0x14: /* KBC_REG */
3673 s->cols = value;
3674 omap_mpuio_kbd_update(s);
3675 break;
3676
3677 case 0x18: /* GPIO_EVENT_MODE_REG */
3678 s->event = value & 0x1f;
3679 break;
3680
3681 case 0x1c: /* GPIO_INT_EDGE_REG */
3682 s->edge = value;
3683 break;
3684
3685 case 0x28: /* KBD_MASKIT */
3686 s->kbd_mask = value & 1;
3687 omap_mpuio_kbd_update(s);
3688 break;
3689
3690 case 0x2c: /* GPIO_MASKIT */
3691 s->mask = value;
3692 break;
3693
3694 case 0x30: /* GPIO_DEBOUNCING_REG */
3695 s->debounce = value & 0x1ff;
3696 break;
3697
3698 case 0x00: /* INPUT_LATCH */
3699 case 0x10: /* KBR_LATCH */
3700 case 0x20: /* KBD_INT */
3701 case 0x24: /* GPIO_INT */
3702 case 0x34: /* GPIO_LATCH_REG */
3703 OMAP_RO_REG(addr);
3704 return;
3705
3706 default:
3707 OMAP_BAD_REG(addr);
3708 return;
3709 }
3710 }
3711
3712 static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
3713 omap_badwidth_read16,
3714 omap_mpuio_read,
3715 omap_badwidth_read16,
3716 };
3717
3718 static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
3719 omap_badwidth_write16,
3720 omap_mpuio_write,
3721 omap_badwidth_write16,
3722 };
3723
3724 static void omap_mpuio_reset(struct omap_mpuio_s *s)
3725 {
3726 s->inputs = 0;
3727 s->outputs = 0;
3728 s->dir = ~0;
3729 s->event = 0;
3730 s->edge = 0;
3731 s->kbd_mask = 0;
3732 s->mask = 0;
3733 s->debounce = 0;
3734 s->latch = 0;
3735 s->ints = 0;
3736 s->row_latch = 0x1f;
3737 s->clk = 1;
3738 }
3739
3740 static void omap_mpuio_onoff(void *opaque, int line, int on)
3741 {
3742 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
3743
3744 s->clk = on;
3745 if (on)
3746 omap_mpuio_kbd_update(s);
3747 }
3748
3749 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
3750 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
3751 omap_clk clk)
3752 {
3753 int iomemtype;
3754 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
3755 qemu_mallocz(sizeof(struct omap_mpuio_s));
3756
3757 s->base = base;
3758 s->irq = gpio_int;
3759 s->kbd_irq = kbd_int;
3760 s->wakeup = wakeup;
3761 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
3762 omap_mpuio_reset(s);
3763
3764 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
3765 omap_mpuio_writefn, s);
3766 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3767
3768 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
3769
3770 return s;
3771 }
3772
3773 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
3774 {
3775 return s->in;
3776 }
3777
3778 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
3779 {
3780 if (line >= 16 || line < 0)
3781 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
3782 s->handler[line] = handler;
3783 }
3784
3785 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
3786 {
3787 if (row >= 5 || row < 0)
3788 cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
3789 __FUNCTION__, col, row);
3790
3791 if (down)
3792 s->buttons[row] |= 1 << col;
3793 else
3794 s->buttons[row] &= ~(1 << col);
3795
3796 omap_mpuio_kbd_update(s);
3797 }
3798
3799 /* General-Purpose I/O */
3800 struct omap_gpio_s {
3801 target_phys_addr_t base;
3802 qemu_irq irq;
3803 qemu_irq *in;
3804 qemu_irq handler[16];
3805
3806 uint16_t inputs;
3807 uint16_t outputs;
3808 uint16_t dir;
3809 uint16_t edge;
3810 uint16_t mask;
3811 uint16_t ints;
3812 uint16_t pins;
3813 };
3814
3815 static void omap_gpio_set(void *opaque, int line, int level)
3816 {
3817 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3818 uint16_t prev = s->inputs;
3819
3820 if (level)
3821 s->inputs |= 1 << line;
3822 else
3823 s->inputs &= ~(1 << line);
3824
3825 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
3826 (1 << line) & s->dir & ~s->mask) {
3827 s->ints |= 1 << line;
3828 qemu_irq_raise(s->irq);
3829 }
3830 }
3831
3832 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
3833 {
3834 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3835 int offset = addr & OMAP_MPUI_REG_MASK;
3836
3837 switch (offset) {
3838 case 0x00: /* DATA_INPUT */
3839 return s->inputs & s->pins;
3840
3841 case 0x04: /* DATA_OUTPUT */
3842 return s->outputs;
3843
3844 case 0x08: /* DIRECTION_CONTROL */
3845 return s->dir;
3846
3847 case 0x0c: /* INTERRUPT_CONTROL */
3848 return s->edge;
3849
3850 case 0x10: /* INTERRUPT_MASK */
3851 return s->mask;
3852
3853 case 0x14: /* INTERRUPT_STATUS */
3854 return s->ints;
3855
3856 case 0x18: /* PIN_CONTROL (not in OMAP310) */
3857 OMAP_BAD_REG(addr);
3858 return s->pins;
3859 }
3860
3861 OMAP_BAD_REG(addr);
3862 return 0;
3863 }
3864
3865 static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
3866 uint32_t value)
3867 {
3868 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3869 int offset = addr & OMAP_MPUI_REG_MASK;
3870 uint16_t diff;
3871 int ln;
3872
3873 switch (offset) {
3874 case 0x00: /* DATA_INPUT */
3875 OMAP_RO_REG(addr);
3876 return;
3877
3878 case 0x04: /* DATA_OUTPUT */
3879 diff = (s->outputs ^ value) & ~s->dir;
3880 s->outputs = value;
3881 while ((ln = ffs(diff))) {
3882 ln --;
3883 if (s->handler[ln])
3884 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
3885 diff &= ~(1 << ln);
3886 }
3887 break;
3888
3889 case 0x08: /* DIRECTION_CONTROL */
3890 diff = s->outputs & (s->dir ^ value);
3891 s->dir = value;
3892
3893 value = s->outputs & ~s->dir;
3894 while ((ln = ffs(diff))) {
3895 ln --;
3896 if (s->handler[ln])
3897 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
3898 diff &= ~(1 << ln);
3899 }
3900 break;
3901
3902 case 0x0c: /* INTERRUPT_CONTROL */
3903 s->edge = value;
3904 break;
3905
3906 case 0x10: /* INTERRUPT_MASK */
3907 s->mask = value;
3908 break;
3909
3910 case 0x14: /* INTERRUPT_STATUS */
3911 s->ints &= ~value;
3912 if (!s->ints)
3913 qemu_irq_lower(s->irq);
3914 break;
3915
3916 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
3917 OMAP_BAD_REG(addr);
3918 s->pins = value;
3919 break;
3920
3921 default:
3922 OMAP_BAD_REG(addr);
3923 return;
3924 }
3925 }
3926
3927 /* *Some* sources say the memory region is 32-bit. */
3928 static CPUReadMemoryFunc *omap_gpio_readfn[] = {
3929 omap_badwidth_read16,
3930 omap_gpio_read,
3931 omap_badwidth_read16,
3932 };
3933
3934 static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
3935 omap_badwidth_write16,
3936 omap_gpio_write,
3937 omap_badwidth_write16,
3938 };
3939
3940 static void omap_gpio_reset(struct omap_gpio_s *s)
3941 {
3942 s->inputs = 0;
3943 s->outputs = ~0;
3944 s->dir = ~0;
3945 s->edge = ~0;
3946 s->mask = ~0;
3947 s->ints = 0;
3948 s->pins = ~0;
3949 }
3950
3951 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
3952 qemu_irq irq, omap_clk clk)
3953 {
3954 int iomemtype;
3955 struct omap_gpio_s *s = (struct omap_gpio_s *)
3956 qemu_mallocz(sizeof(struct omap_gpio_s));
3957
3958 s->base = base;
3959 s->irq = irq;
3960 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
3961 omap_gpio_reset(s);
3962
3963 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
3964 omap_gpio_writefn, s);
3965 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3966
3967 return s;
3968 }
3969
3970 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
3971 {
3972 return s->in;
3973 }
3974
3975 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
3976 {
3977 if (line >= 16 || line < 0)
3978 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
3979 s->handler[line] = handler;
3980 }
3981
3982 /* MicroWire Interface */
3983 struct omap_uwire_s {
3984 target_phys_addr_t base;
3985 qemu_irq txirq;
3986 qemu_irq rxirq;
3987 qemu_irq txdrq;
3988
3989 uint16_t txbuf;
3990 uint16_t rxbuf;
3991 uint16_t control;
3992 uint16_t setup[5];
3993
3994 struct uwire_slave_s *chip[4];
3995 };
3996
3997 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3998 {
3999 int chipselect = (s->control >> 10) & 3; /* INDEX */
4000 struct uwire_slave_s *slave = s->chip[chipselect];
4001
4002 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
4003 if (s->control & (1 << 12)) /* CS_CMD */
4004 if (slave && slave->send)
4005 slave->send(slave->opaque,
4006 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
4007 s->control &= ~(1 << 14); /* CSRB */
4008 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
4009 * a DRQ. When is the level IRQ supposed to be reset? */
4010 }
4011
4012 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
4013 if (s->control & (1 << 12)) /* CS_CMD */
4014 if (slave && slave->receive)
4015 s->rxbuf = slave->receive(slave->opaque);
4016 s->control |= 1 << 15; /* RDRB */
4017 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
4018 * a DRQ. When is the level IRQ supposed to be reset? */
4019 }
4020 }
4021
4022 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
4023 {
4024 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
4025 int offset = addr & OMAP_MPUI_REG_MASK;
4026
4027 switch (offset) {
4028 case 0x00: /* RDR */
4029 s->control &= ~(1 << 15); /* RDRB */
4030 return s->rxbuf;
4031
4032 case 0x04: /* CSR */
4033 return s->control;
4034
4035 case 0x08: /* SR1 */
4036 return s->setup[0];
4037 case 0x0c: /* SR2 */
4038 return s->setup[1];
4039 case 0x10: /* SR3 */
4040 return s->setup[2];
4041 case 0x14: /* SR4 */
4042 return s->setup[3];
4043 case 0x18: /* SR5 */
4044 return s->setup[4];
4045 }
4046
4047 OMAP_BAD_REG(addr);
4048 return 0;
4049 }
4050
4051 static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
4052 uint32_t value)
4053 {
4054 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
4055 int offset = addr & OMAP_MPUI_REG_MASK;
4056
4057 switch (offset) {
4058 case 0x00: /* TDR */
4059 s->txbuf = value; /* TD */
4060 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
4061 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
4062 (s->control & (1 << 12)))) { /* CS_CMD */
4063 s->control |= 1 << 14; /* CSRB */
4064 omap_uwire_transfer_start(s);
4065 }
4066 break;
4067
4068 case 0x04: /* CSR */
4069 s->control = value & 0x1fff;
4070 if (value & (1 << 13)) /* START */
4071 omap_uwire_transfer_start(s);
4072 break;
4073
4074 case 0x08: /* SR1 */
4075 s->setup[0] = value & 0x003f;
4076 break;
4077
4078 case 0x0c: /* SR2 */
4079 s->setup[1] = value & 0x0fc0;
4080 break;
4081
4082 case 0x10: /* SR3 */
4083 s->setup[2] = value & 0x0003;
4084 break;
4085
4086 case 0x14: /* SR4 */
4087 s->setup[3] = value & 0x0001;
4088 break;
4089
4090 case 0x18: /* SR5 */
4091 s->setup[4] = value & 0x000f;
4092 break;
4093
4094 default:
4095 OMAP_BAD_REG(addr);
4096 return;
4097 }
4098 }
4099
4100 static CPUReadMemoryFunc *omap_uwire_readfn[] = {
4101 omap_badwidth_read16,
4102 omap_uwire_read,
4103 omap_badwidth_read16,
4104 };
4105
4106 static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
4107 omap_badwidth_write16,
4108 omap_uwire_write,
4109 omap_badwidth_write16,
4110 };
4111
4112 static void omap_uwire_reset(struct omap_uwire_s *s)
4113 {
4114 s->control = 0;
4115 s->setup[0] = 0;
4116 s->setup[1] = 0;
4117 s->setup[2] = 0;
4118 s->setup[3] = 0;
4119 s->setup[4] = 0;
4120 }
4121
4122 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
4123 qemu_irq *irq, qemu_irq dma, omap_clk clk)
4124 {
4125 int iomemtype;
4126 struct omap_uwire_s *s = (struct omap_uwire_s *)
4127 qemu_mallocz(sizeof(struct omap_uwire_s));
4128
4129 s->base = base;
4130 s->txirq = irq[0];
4131 s->rxirq = irq[1];
4132 s->txdrq = dma;
4133 omap_uwire_reset(s);
4134
4135 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
4136 omap_uwire_writefn, s);
4137 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4138
4139 return s;
4140 }
4141
4142 void omap_uwire_attach(struct omap_uwire_s *s,
4143 struct uwire_slave_s *slave, int chipselect)
4144 {
4145 if (chipselect < 0 || chipselect > 3)
4146 cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", __FUNCTION__,
4147 chipselect);
4148
4149 s->chip[chipselect] = slave;
4150 }
4151
4152 /* Pseudonoise Pulse-Width Light Modulator */
4153 static void omap_pwl_update(struct omap_mpu_state_s *s)
4154 {
4155 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
4156
4157 if (output != s->pwl.output) {
4158 s->pwl.output = output;
4159 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
4160 }
4161 }
4162
4163 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
4164 {
4165 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
4166 int offset = addr & OMAP_MPUI_REG_MASK;
4167
4168 switch (offset) {
4169 case 0x00: /* PWL_LEVEL */
4170 return s->pwl.level;
4171 case 0x04: /* PWL_CTRL */
4172 return s->pwl.enable;
4173 }
4174 OMAP_BAD_REG(addr);
4175 return 0;
4176 }
4177
4178 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
4179 uint32_t value)
4180 {
4181 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
4182 int offset = addr & OMAP_MPUI_REG_MASK;
4183
4184 switch (offset) {
4185 case 0x00: /* PWL_LEVEL */
4186 s->pwl.level = value;
4187 omap_pwl_update(s);
4188 break;
4189 case 0x04: /* PWL_CTRL */
4190 s->pwl.enable = value & 1;
4191 omap_pwl_update(s);
4192 break;
4193 default:
4194 OMAP_BAD_REG(addr);
4195 return;
4196 }
4197 }
4198
4199 static CPUReadMemoryFunc *omap_pwl_readfn[] = {
4200 omap_pwl_read,
4201 omap_badwidth_read8,
4202 omap_badwidth_read8,
4203 };
4204
4205 static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
4206 omap_pwl_write,
4207 omap_badwidth_write8,
4208 omap_badwidth_write8,
4209 };
4210
4211 static void omap_pwl_reset(struct omap_mpu_state_s *s)
4212 {
4213 s->pwl.output = 0;
4214 s->pwl.level = 0;
4215 s->pwl.enable = 0;
4216 s->pwl.clk = 1;
4217 omap_pwl_update(s);
4218 }
4219
4220 static void omap_pwl_clk_update(void *opaque, int line, int on)
4221 {
4222 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
4223
4224 s->pwl.clk = on;
4225 omap_pwl_update(s);
4226 }
4227
4228 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
4229 omap_clk clk)
4230 {
4231 int iomemtype;
4232
4233 omap_pwl_reset(s);
4234
4235 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
4236 omap_pwl_writefn, s);
4237 cpu_register_physical_memory(base, 0x800, iomemtype);
4238
4239 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
4240 }
4241
4242 /* Pulse-Width Tone module */
4243 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
4244 {
4245 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
4246 int offset = addr & OMAP_MPUI_REG_MASK;
4247
4248 switch (offset) {
4249 case 0x00: /* FRC */
4250 return s->pwt.frc;
4251 case 0x04: /* VCR */
4252 return s->pwt.vrc;
4253 case 0x08: /* GCR */
4254 return s->pwt.gcr;
4255 }
4256 OMAP_BAD_REG(addr);
4257 return 0;
4258 }
4259
4260 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
4261 uint32_t value)
4262 {
4263 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
4264 int offset = addr & OMAP_MPUI_REG_MASK;
4265
4266 switch (offset) {
4267 case 0x00: /* FRC */
4268 s->pwt.frc = value & 0x3f;
4269 break;
4270 case 0x04: /* VRC */
4271 if ((value ^ s->pwt.vrc) & 1) {
4272 if (value & 1)
4273 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
4274 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
4275 ((omap_clk_getrate(s->pwt.clk) >> 3) /
4276 /* Pre-multiplexer divider */
4277 ((s->pwt.gcr & 2) ? 1 : 154) /
4278 /* Octave multiplexer */
4279 (2 << (value & 3)) *
4280 /* 101/107 divider */
4281 ((value & (1 << 2)) ? 101 : 107) *
4282 /* 49/55 divider */
4283 ((value & (1 << 3)) ? 49 : 55) *
4284 /* 50/63 divider */
4285 ((value & (1 << 4)) ? 50 : 63) *
4286 /* 80/127 divider */
4287 ((value & (1 << 5)) ? 80 : 127) /
4288 (107 * 55 * 63 * 127)));
4289 else
4290 printf("%s: silence!\n", __FUNCTION__);
4291 }
4292 s->pwt.vrc = value & 0x7f;
4293 break;
4294 case 0x08: /* GCR */
4295 s->pwt.gcr = value & 3;
4296 break;
4297 default:
4298 OMAP_BAD_REG(addr);
4299 return;
4300 }
4301 }
4302
4303 static CPUReadMemoryFunc *omap_pwt_readfn[] = {
4304 omap_pwt_read,
4305 omap_badwidth_read8,
4306 omap_badwidth_read8,
4307 };
4308
4309 static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
4310 omap_pwt_write,
4311 omap_badwidth_write8,
4312 omap_badwidth_write8,
4313 };
4314
4315 static void omap_pwt_reset(struct omap_mpu_state_s *s)
4316 {
4317 s->pwt.frc = 0;
4318 s->pwt.vrc = 0;
4319 s->pwt.gcr = 0;
4320 }
4321
4322 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
4323 omap_clk clk)
4324 {
4325 int iomemtype;
4326
4327 s->pwt.clk = clk;
4328 omap_pwt_reset(s);
4329
4330 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
4331 omap_pwt_writefn, s);
4332 cpu_register_physical_memory(base, 0x800, iomemtype);
4333 }
4334
4335 /* Real-time Clock module */
4336 struct omap_rtc_s {
4337 target_phys_addr_t base;
4338 qemu_irq irq;
4339 qemu_irq alarm;
4340 QEMUTimer *clk;
4341
4342 uint8_t interrupts;
4343 uint8_t status;
4344 int16_t comp_reg;
4345 int running;
4346 int pm_am;
4347 int auto_comp;
4348 int round;
4349 struct tm alarm_tm;
4350 time_t alarm_ti;
4351
4352 struct tm current_tm;
4353 time_t ti;
4354 uint64_t tick;
4355 };
4356
4357 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
4358 {
4359 /* s->alarm is level-triggered */
4360 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
4361 }
4362
4363 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
4364 {
4365 s->alarm_ti = mktime(&s->alarm_tm);
4366 if (s->alarm_ti == -1)
4367 printf("%s: conversion failed\n", __FUNCTION__);
4368 }
4369
4370 static inline uint8_t omap_rtc_bcd(int num)
4371 {
4372 return ((num / 10) << 4) | (num % 10);
4373 }
4374
4375 static inline int omap_rtc_bin(uint8_t num)
4376 {
4377 return (num & 15) + 10 * (num >> 4);
4378 }
4379
4380 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
4381 {
4382 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
4383 int offset = addr & OMAP_MPUI_REG_MASK;
4384 uint8_t i;
4385
4386 switch (offset) {
4387 case 0x00: /* SECONDS_REG */
4388 return omap_rtc_bcd(s->current_tm.tm_sec);
4389
4390 case 0x04: /* MINUTES_REG */
4391 return omap_rtc_bcd(s->current_tm.tm_min);
4392
4393 case 0x08: /* HOURS_REG */
4394 if (s->pm_am)
4395 return ((s->current_tm.tm_hour > 11) << 7) |
4396 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
4397 else
4398 return omap_rtc_bcd(s->current_tm.tm_hour);
4399
4400 case 0x0c: /* DAYS_REG */
4401 return omap_rtc_bcd(s->current_tm.tm_mday);
4402
4403 case 0x10: /* MONTHS_REG */
4404 return omap_rtc_bcd(s->current_tm.tm_mon + 1);
4405
4406 case 0x14: /* YEARS_REG */
4407 return omap_rtc_bcd(s->current_tm.tm_year % 100);
4408
4409 case 0x18: /* WEEK_REG */
4410 return s->current_tm.tm_wday;
4411
4412 case 0x20: /* ALARM_SECONDS_REG */
4413 return omap_rtc_bcd(s->alarm_tm.tm_sec);
4414
4415 case 0x24: /* ALARM_MINUTES_REG */
4416 return omap_rtc_bcd(s->alarm_tm.tm_min);
4417
4418 case 0x28: /* ALARM_HOURS_REG */
4419 if (s->pm_am)
4420 return ((s->alarm_tm.tm_hour > 11) << 7) |
4421 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
4422 else
4423 return omap_rtc_bcd(s->alarm_tm.tm_hour);
4424
4425 case 0x2c: /* ALARM_DAYS_REG */
4426 return omap_rtc_bcd(s->alarm_tm.tm_mday);
4427
4428 case 0x30: /* ALARM_MONTHS_REG */
4429 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1);
4430
4431 case 0x34: /* ALARM_YEARS_REG */
4432 return omap_rtc_bcd(s->alarm_tm.tm_year % 100);
4433
4434 case 0x40: /* RTC_CTRL_REG */
4435 return (s->pm_am << 3) | (s->auto_comp << 2) |
4436 (s->round << 1) | s->running;
4437
4438 case 0x44: /* RTC_STATUS_REG */
4439 i = s->status;
4440 s->status &= ~0x3d;
4441 return i;
4442
4443 case 0x48: /* RTC_INTERRUPTS_REG */
4444 return s->interrupts;
4445
4446 case 0x4c: /* RTC_COMP_LSB_REG */
4447 return ((uint16_t) s->comp_reg) & 0xff;
4448
4449 case 0x50: /* RTC_COMP_MSB_REG */
4450 return ((uint16_t) s->comp_reg) >> 8;
4451 }
4452
4453 OMAP_BAD_REG(addr);
4454 return 0;
4455 }
4456
4457 static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
4458 uint32_t value)
4459 {
4460 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
4461 int offset = addr & OMAP_MPUI_REG_MASK;
4462 struct tm new_tm;
4463 time_t ti[2];
4464
4465 switch (offset) {
4466 case 0x00: /* SECONDS_REG */
4467 #if ALMDEBUG
4468 printf("RTC SEC_REG <-- %02x\n", value);
4469 #endif
4470 s->ti -= s->current_tm.tm_sec;
4471 s->ti += omap_rtc_bin(value);
4472 return;
4473
4474 case 0x04: /* MINUTES_REG */
4475 #if ALMDEBUG
4476 printf("RTC MIN_REG <-- %02x\n", value);
4477 #endif
4478 s->ti -= s->current_tm.tm_min * 60;
4479 s->ti += omap_rtc_bin(value) * 60;
4480 return;
4481
4482 case 0x08: /* HOURS_REG */
4483 #if ALMDEBUG
4484 printf("RTC HRS_REG <-- %02x\n", value);
4485 #endif
4486 s->ti -= s->current_tm.tm_hour * 3600;
4487 if (s->pm_am) {
4488 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600;
4489 s->ti += ((value >> 7) & 1) * 43200;
4490 } else
4491 s->ti += omap_rtc_bin(value & 0x3f) * 3600;
4492 return;
4493
4494 case 0x0c: /* DAYS_REG */
4495 #if ALMDEBUG
4496 printf("RTC DAY_REG <-- %02x\n", value);
4497 #endif
4498 s->ti -= s->current_tm.tm_mday * 86400;
4499 s->ti += omap_rtc_bin(value) * 86400;
4500 return;
4501
4502 case 0x10: /* MONTHS_REG */
4503 #if ALMDEBUG
4504 printf("RTC MTH_REG <-- %02x\n", value);
4505 #endif
4506 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
4507 new_tm.tm_mon = omap_rtc_bin(value);
4508 ti[0] = mktime(&s->current_tm);
4509 ti[1] = mktime(&new_tm);
4510
4511 if (ti[0] != -1 && ti[1] != -1) {
4512 s->ti -= ti[0];
4513 s->ti += ti[1];
4514 } else {
4515 /* A less accurate version */
4516 s->ti -= s->current_tm.tm_mon * 2592000;
4517 s->ti += omap_rtc_bin(value) * 2592000;
4518 }
4519 return;
4520
4521 case 0x14: /* YEARS_REG */
4522 #if ALMDEBUG
4523 printf("RTC YRS_REG <-- %02x\n", value);
4524 #endif
4525 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
4526 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
4527 ti[0] = mktime(&s->current_tm);
4528 ti[1] = mktime(&new_tm);
4529
4530 if (ti[0] != -1 && ti[1] != -1) {
4531 s->ti -= ti[0];
4532 s->ti += ti[1];
4533 } else {
4534 /* A less accurate version */
4535 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
4536 s->ti += omap_rtc_bin(value) * 31536000;
4537 }
4538 return;
4539
4540 case 0x18: /* WEEK_REG */
4541 return; /* Ignored */
4542
4543 case 0x20: /* ALARM_SECONDS_REG */
4544 #if ALMDEBUG
4545 printf("ALM SEC_REG <-- %02x\n", value);
4546 #endif
4547 s->alarm_tm.tm_sec = omap_rtc_bin(value);
4548 omap_rtc_alarm_update(s);
4549 return;
4550
4551 case 0x24: /* ALARM_MINUTES_REG */
4552 #if ALMDEBUG
4553 printf("ALM MIN_REG <-- %02x\n", value);
4554 #endif
4555 s->alarm_tm.tm_min = omap_rtc_bin(value);
4556 omap_rtc_alarm_update(s);
4557 return;
4558
4559 case 0x28: /* ALARM_HOURS_REG */
4560 #if ALMDEBUG
4561 printf("ALM HRS_REG <-- %02x\n", value);
4562 #endif
4563 if (s->pm_am)
4564 s->alarm_tm.tm_hour =
4565 ((omap_rtc_bin(value & 0x3f)) % 12) +
4566 ((value >> 7) & 1) * 12;
4567 else
4568 s->alarm_tm.tm_hour = omap_rtc_bin(value);
4569 omap_rtc_alarm_update(s);
4570 return;
4571
4572 case 0x2c: /* ALARM_DAYS_REG */
4573 #if ALMDEBUG
4574 printf("ALM DAY_REG <-- %02x\n", value);
4575 #endif
4576 s->alarm_tm.tm_mday = omap_rtc_bin(value);
4577 omap_rtc_alarm_update(s);
4578 return;
4579
4580 case 0x30: /* ALARM_MONTHS_REG */
4581 #if ALMDEBUG
4582 printf("ALM MON_REG <-- %02x\n", value);
4583 #endif
4584 s->alarm_tm.tm_mon = omap_rtc_bin(value);
4585 omap_rtc_alarm_update(s);
4586 return;
4587
4588 case 0x34: /* ALARM_YEARS_REG */
4589 #if ALMDEBUG
4590 printf("ALM YRS_REG <-- %02x\n", value);
4591 #endif
4592 s->alarm_tm.tm_year = omap_rtc_bin(value);
4593 omap_rtc_alarm_update(s);
4594 return;
4595
4596 case 0x40: /* RTC_CTRL_REG */
4597 #if ALMDEBUG
4598 printf("RTC CONTROL <-- %02x\n", value);
4599 #endif
4600 s->pm_am = (value >> 3) & 1;
4601 s->auto_comp = (value >> 2) & 1;
4602 s->round = (value >> 1) & 1;
4603 s->running = value & 1;
4604 s->status &= 0xfd;
4605 s->status |= s->running << 1;
4606 return;
4607
4608 case 0x44: /* RTC_STATUS_REG */
4609 #if ALMDEBUG
4610 printf("RTC STATUSL <-- %02x\n", value);
4611 #endif
4612 s->status &= ~((value & 0xc0) ^ 0x80);
4613 omap_rtc_interrupts_update(s);
4614 return;
4615
4616 case 0x48: /* RTC_INTERRUPTS_REG */
4617 #if ALMDEBUG
4618 printf("RTC INTRS <-- %02x\n", value);
4619 #endif
4620 s->interrupts = value;
4621 return;
4622
4623 case 0x4c: /* RTC_COMP_LSB_REG */
4624 #if ALMDEBUG
4625 printf("RTC COMPLSB <-- %02x\n", value);
4626 #endif
4627 s->comp_reg &= 0xff00;
4628 s->comp_reg |= 0x00ff & value;
4629 return;
4630
4631 case 0x50: /* RTC_COMP_MSB_REG */
4632 #if ALMDEBUG
4633 printf("RTC COMPMSB <-- %02x\n", value);
4634 #endif
4635 s->comp_reg &= 0x00ff;
4636 s->comp_reg |= 0xff00 & (value << 8);
4637 return;
4638
4639 default:
4640 OMAP_BAD_REG(addr);
4641 return;
4642 }
4643 }
4644
4645 static CPUReadMemoryFunc *omap_rtc_readfn[] = {
4646 omap_rtc_read,
4647 omap_badwidth_read8,
4648 omap_badwidth_read8,
4649 };
4650
4651 static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
4652 omap_rtc_write,
4653 omap_badwidth_write8,
4654 omap_badwidth_write8,
4655 };
4656
4657 static void omap_rtc_tick(void *opaque)
4658 {
4659 struct omap_rtc_s *s = opaque;
4660
4661 if (s->round) {
4662 /* Round to nearest full minute. */
4663 if (s->current_tm.tm_sec < 30)
4664 s->ti -= s->current_tm.tm_sec;
4665 else
4666 s->ti += 60 - s->current_tm.tm_sec;
4667
4668 s->round = 0;
4669 }
4670
4671 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
4672
4673 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
4674 s->status |= 0x40;
4675 omap_rtc_interrupts_update(s);
4676 }
4677
4678 if (s->interrupts & 0x04)
4679 switch (s->interrupts & 3) {
4680 case 0:
4681 s->status |= 0x04;
4682 qemu_irq_pulse(s->irq);
4683 break;
4684 case 1:
4685 if (s->current_tm.tm_sec)
4686 break;
4687 s->status |= 0x08;
4688 qemu_irq_pulse(s->irq);
4689 break;
4690 case 2:
4691 if (s->current_tm.tm_sec || s->current_tm.tm_min)
4692 break;
4693 s->status |= 0x10;
4694 qemu_irq_pulse(s->irq);
4695 break;
4696 case 3:
4697 if (s->current_tm.tm_sec ||
4698 s->current_tm.tm_min || s->current_tm.tm_hour)
4699 break;
4700 s->status |= 0x20;
4701 qemu_irq_pulse(s->irq);
4702 break;
4703 }
4704
4705 /* Move on */
4706 if (s->running)
4707 s->ti ++;
4708 s->tick += 1000;
4709
4710 /*
4711 * Every full hour add a rough approximation of the compensation
4712 * register to the 32kHz Timer (which drives the RTC) value.
4713 */
4714 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
4715 s->tick += s->comp_reg * 1000 / 32768;
4716
4717 qemu_mod_timer(s->clk, s->tick);
4718 }
4719
4720 static void omap_rtc_reset(struct omap_rtc_s *s)
4721 {
4722 struct tm tm;
4723
4724 s->interrupts = 0;
4725 s->comp_reg = 0;
4726 s->running = 0;
4727 s->pm_am = 0;
4728 s->auto_comp = 0;
4729 s->round = 0;
4730 s->tick = qemu_get_clock(rt_clock);
4731 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
4732 s->alarm_tm.tm_mday = 0x01;
4733 s->status = 1 << 7;
4734 qemu_get_timedate(&tm, 0);
4735 s->ti = mktime(&tm);
4736
4737 omap_rtc_alarm_update(s);
4738 omap_rtc_tick(s);
4739 }
4740
4741 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
4742 qemu_irq *irq, omap_clk clk)
4743 {
4744 int iomemtype;
4745 struct omap_rtc_s *s = (struct omap_rtc_s *)
4746 qemu_mallocz(sizeof(struct omap_rtc_s));
4747
4748 s->base = base;
4749 s->irq = irq[0];
4750 s->alarm = irq[1];
4751 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
4752
4753 omap_rtc_reset(s);
4754
4755 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
4756 omap_rtc_writefn, s);
4757 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4758
4759 return s;
4760 }
4761
4762 /* Multi-channel Buffered Serial Port interfaces */
4763 struct omap_mcbsp_s {
4764 target_phys_addr_t base;
4765 qemu_irq txirq;
4766 qemu_irq rxirq;
4767 qemu_irq txdrq;
4768 qemu_irq rxdrq;
4769
4770 uint16_t spcr[2];
4771 uint16_t rcr[2];
4772 uint16_t xcr[2];
4773 uint16_t srgr[2];
4774 uint16_t mcr[2];
4775 uint16_t pcr;
4776 uint16_t rcer[8];
4777 uint16_t xcer[8];
4778 int tx_rate;
4779 int rx_rate;
4780 int tx_req;
4781 int rx_req;
4782
4783 struct i2s_codec_s *codec;
4784 QEMUTimer *source_timer;
4785 QEMUTimer *sink_timer;
4786 };
4787
4788 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
4789 {
4790 int irq;
4791
4792 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
4793 case 0:
4794 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
4795 break;
4796 case 3:
4797 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
4798 break;
4799 default:
4800 irq = 0;
4801 break;
4802 }
4803
4804 if (irq)
4805 qemu_irq_pulse(s->rxirq);
4806
4807 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
4808 case 0:
4809 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
4810 break;
4811 case 3:
4812 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
4813 break;
4814 default:
4815 irq = 0;
4816 break;
4817 }
4818
4819 if (irq)
4820 qemu_irq_pulse(s->txirq);
4821 }
4822
4823 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
4824 {
4825 if ((s->spcr[0] >> 1) & 1) /* RRDY */
4826 s->spcr[0] |= 1 << 2; /* RFULL */
4827 s->spcr[0] |= 1 << 1; /* RRDY */
4828 qemu_irq_raise(s->rxdrq);
4829 omap_mcbsp_intr_update(s);
4830 }
4831
4832 static void omap_mcbsp_source_tick(void *opaque)
4833 {
4834 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4835 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
4836
4837 if (!s->rx_rate)
4838 return;
4839 if (s->rx_req)
4840 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
4841
4842 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
4843
4844 omap_mcbsp_rx_newdata(s);
4845 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
4846 }
4847
4848 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
4849 {
4850 if (!s->codec || !s->codec->rts)
4851 omap_mcbsp_source_tick(s);
4852 else if (s->codec->in.len) {
4853 s->rx_req = s->codec->in.len;
4854 omap_mcbsp_rx_newdata(s);
4855 }
4856 }
4857
4858 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
4859 {
4860 qemu_del_timer(s->source_timer);
4861 }
4862
4863 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
4864 {
4865 s->spcr[0] &= ~(1 << 1); /* RRDY */
4866 qemu_irq_lower(s->rxdrq);
4867 omap_mcbsp_intr_update(s);
4868 }
4869
4870 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
4871 {
4872 s->spcr[1] |= 1 << 1; /* XRDY */
4873 qemu_irq_raise(s->txdrq);
4874 omap_mcbsp_intr_update(s);
4875 }
4876
4877 static void omap_mcbsp_sink_tick(void *opaque)
4878 {
4879 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4880 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
4881
4882 if (!s->tx_rate)
4883 return;
4884 if (s->tx_req)
4885 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
4886
4887 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
4888
4889 omap_mcbsp_tx_newdata(s);
4890 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
4891 }
4892
4893 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
4894 {
4895 if (!s->codec || !s->codec->cts)
4896 omap_mcbsp_sink_tick(s);
4897 else if (s->codec->out.size) {
4898 s->tx_req = s->codec->out.size;
4899 omap_mcbsp_tx_newdata(s);
4900 }
4901 }
4902
4903 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
4904 {
4905 s->spcr[1] &= ~(1 << 1); /* XRDY */
4906 qemu_irq_lower(s->txdrq);
4907 omap_mcbsp_intr_update(s);
4908 if (s->codec && s->codec->cts)
4909 s->codec->tx_swallow(s->codec->opaque);
4910 }
4911
4912 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
4913 {
4914 s->tx_req = 0;
4915 omap_mcbsp_tx_done(s);
4916 qemu_del_timer(s->sink_timer);
4917 }
4918
4919 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
4920 {
4921 int prev_rx_rate, prev_tx_rate;
4922 int rx_rate = 0, tx_rate = 0;
4923 int cpu_rate = 1500000; /* XXX */
4924
4925 /* TODO: check CLKSTP bit */
4926 if (s->spcr[1] & (1 << 6)) { /* GRST */
4927 if (s->spcr[0] & (1 << 0)) { /* RRST */
4928 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
4929 (s->pcr & (1 << 8))) { /* CLKRM */
4930 if (~s->pcr & (1 << 7)) /* SCLKME */
4931 rx_rate = cpu_rate /
4932 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
4933 } else
4934 if (s->codec)
4935 rx_rate = s->codec->rx_rate;
4936 }
4937
4938 if (s->spcr[1] & (1 << 0)) { /* XRST */
4939 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
4940 (s->pcr & (1 << 9))) { /* CLKXM */
4941 if (~s->pcr & (1 << 7)) /* SCLKME */
4942 tx_rate = cpu_rate /
4943 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
4944 } else
4945 if (s->codec)
4946 tx_rate = s->codec->tx_rate;
4947 }
4948 }
4949 prev_tx_rate = s->tx_rate;
4950 prev_rx_rate = s->rx_rate;
4951 s->tx_rate = tx_rate;
4952 s->rx_rate = rx_rate;
4953
4954 if (s->codec)
4955 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
4956
4957 if (!prev_tx_rate && tx_rate)
4958 omap_mcbsp_tx_start(s);
4959 else if (s->tx_rate && !tx_rate)
4960 omap_mcbsp_tx_stop(s);
4961
4962 if (!prev_rx_rate && rx_rate)
4963 omap_mcbsp_rx_start(s);
4964 else if (prev_tx_rate && !tx_rate)
4965 omap_mcbsp_rx_stop(s);
4966 }
4967
4968 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
4969 {
4970 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4971 int offset = addr & OMAP_MPUI_REG_MASK;
4972 uint16_t ret;
4973
4974 switch (offset) {
4975 case 0x00: /* DRR2 */
4976 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
4977 return 0x0000;
4978 /* Fall through. */
4979 case 0x02: /* DRR1 */
4980 if (s->rx_req < 2) {
4981 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
4982 omap_mcbsp_rx_done(s);
4983 } else {
4984 s->tx_req -= 2;
4985 if (s->codec && s->codec->in.len >= 2) {
4986 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
4987 ret |= s->codec->in.fifo[s->codec->in.start ++];
4988 s->codec->in.len -= 2;
4989 } else
4990 ret = 0x0000;
4991 if (!s->tx_req)
4992 omap_mcbsp_rx_done(s);
4993 return ret;
4994 }
4995 return 0x0000;
4996
4997 case 0x04: /* DXR2 */
4998 case 0x06: /* DXR1 */
4999 return 0x0000;
5000
5001 case 0x08: /* SPCR2 */
5002 return s->spcr[1];
5003 case 0x0a: /* SPCR1 */
5004 return s->spcr[0];
5005 case 0x0c: /* RCR2 */
5006 return s->rcr[1];
5007 case 0x0e: /* RCR1 */
5008 return s->rcr[0];
5009 case 0x10: /* XCR2 */
5010 return s->xcr[1];
5011 case 0x12: /* XCR1 */
5012 return s->xcr[0];
5013 case 0x14: /* SRGR2 */
5014 return s->srgr[1];
5015 case 0x16: /* SRGR1 */
5016 return s->srgr[0];
5017 case 0x18: /* MCR2 */
5018 return s->mcr[1];
5019 case 0x1a: /* MCR1 */
5020 return s->mcr[0];
5021 case 0x1c: /* RCERA */
5022 return s->rcer[0];
5023 case 0x1e: /* RCERB */
5024 return s->rcer[1];
5025 case 0x20: /* XCERA */
5026 return s->xcer[0];
5027 case 0x22: /* XCERB */
5028 return s->xcer[1];
5029 case 0x24: /* PCR0 */
5030 return s->pcr;
5031 case 0x26: /* RCERC */
5032 return s->rcer[2];
5033 case 0x28: /* RCERD */
5034 return s->rcer[3];
5035 case 0x2a: /* XCERC */
5036 return s->xcer[2];
5037 case 0x2c: /* XCERD */
5038 return s->xcer[3];
5039 case 0x2e: /* RCERE */
5040 return s->rcer[4];
5041 case 0x30: /* RCERF */
5042 return s->rcer[5];
5043 case 0x32: /* XCERE */
5044 return s->xcer[4];
5045 case 0x34: /* XCERF */
5046 return s->xcer[5];
5047 case 0x36: /* RCERG */
5048 return s->rcer[6];
5049 case 0x38: /* RCERH */
5050 return s->rcer[7];
5051 case 0x3a: /* XCERG */
5052 return s->xcer[6];
5053 case 0x3c: /* XCERH */
5054 return s->xcer[7];
5055 }
5056
5057 OMAP_BAD_REG(addr);
5058 return 0;
5059 }
5060
5061 static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
5062 uint32_t value)
5063 {
5064 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
5065 int offset = addr & OMAP_MPUI_REG_MASK;
5066
5067 switch (offset) {
5068 case 0x00: /* DRR2 */
5069 case 0x02: /* DRR1 */
5070 OMAP_RO_REG(addr);
5071 return;
5072
5073 case 0x04: /* DXR2 */
5074 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
5075 return;
5076 /* Fall through. */
5077 case 0x06: /* DXR1 */
5078 if (s->tx_req > 1) {
5079 s->tx_req -= 2;
5080 if (s->codec && s->codec->cts) {
5081 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
5082 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
5083 }
5084 if (s->tx_req < 2)
5085 omap_mcbsp_tx_done(s);
5086 } else
5087 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
5088 return;
5089
5090 case 0x08: /* SPCR2 */
5091 s->spcr[1] &= 0x0002;
5092 s->spcr[1] |= 0x03f9 & value;
5093 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
5094 if (~value & 1) /* XRST */
5095 s->spcr[1] &= ~6;
5096 omap_mcbsp_req_update(s);
5097 return;
5098 case 0x0a: /* SPCR1 */
5099 s->spcr[0] &= 0x0006;
5100 s->spcr[0] |= 0xf8f9 & value;
5101 if (value & (1 << 15)) /* DLB */
5102 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
5103 if (~value & 1) { /* RRST */
5104 s->spcr[0] &= ~6;
5105 s->rx_req = 0;
5106 omap_mcbsp_rx_done(s);
5107 }
5108 omap_mcbsp_req_update(s);
5109 return;
5110
5111 case 0x0c: /* RCR2 */
5112 s->rcr[1] = value & 0xffff;
5113 return;
5114 case 0x0e: /* RCR1 */
5115 s->rcr[0] = value & 0x7fe0;
5116 return;
5117 case 0x10: /* XCR2 */
5118 s->xcr[1] = value & 0xffff;
5119 return;
5120 case 0x12: /* XCR1 */
5121 s->xcr[0] = value & 0x7fe0;
5122 return;
5123 case 0x14: /* SRGR2 */
5124 s->srgr[1] = value & 0xffff;
5125 omap_mcbsp_req_update(s);
5126 return;
5127 case 0x16: /* SRGR1 */
5128 s->srgr[0] = value & 0xffff;
5129 omap_mcbsp_req_update(s);
5130 return;
5131 case 0x18: /* MCR2 */
5132 s->mcr[1] = value & 0x03e3;
5133 if (value & 3) /* XMCM */
5134 printf("%s: Tx channel selection mode enable attempt\n",
5135 __FUNCTION__);
5136 return;
5137 case 0x1a: /* MCR1 */
5138 s->mcr[0] = value & 0x03e1;
5139 if (value & 1) /* RMCM */
5140 printf("%s: Rx channel selection mode enable attempt\n",
5141 __FUNCTION__);
5142 return;
5143 case 0x1c: /* RCERA */
5144 s->rcer[0] = value & 0xffff;
5145 return;
5146 case 0x1e: /* RCERB */
5147 s->rcer[1] = value & 0xffff;
5148 return;
5149 case 0x20: /* XCERA */
5150 s->xcer[0] = value & 0xffff;
5151 return;
5152 case 0x22: /* XCERB */
5153 s->xcer[1] = value & 0xffff;
5154 return;
5155 case 0x24: /* PCR0 */
5156 s->pcr = value & 0x7faf;
5157 return;
5158 case 0x26: /* RCERC */
5159 s->rcer[2] = value & 0xffff;
5160 return;
5161 case 0x28: /* RCERD */
5162 s->rcer[3] = value & 0xffff;
5163 return;
5164 case 0x2a: /* XCERC */
5165 s->xcer[2] = value & 0xffff;
5166 return;
5167 case 0x2c: /* XCERD */
5168 s->xcer[3] = value & 0xffff;
5169 return;
5170 case 0x2e: /* RCERE */
5171 s->rcer[4] = value & 0xffff;
5172 return;
5173 case 0x30: /* RCERF */
5174 s->rcer[5] = value & 0xffff;
5175 return;
5176 case 0x32: /* XCERE */
5177 s->xcer[4] = value & 0xffff;
5178 return;
5179 case 0x34: /* XCERF */
5180 s->xcer[5] = value & 0xffff;
5181 return;
5182 case 0x36: /* RCERG */
5183 s->rcer[6] = value & 0xffff;
5184 return;
5185 case 0x38: /* RCERH */
5186 s->rcer[7] = value & 0xffff;
5187 return;
5188 case 0x3a: /* XCERG */
5189 s->xcer[6] = value & 0xffff;
5190 return;
5191 case 0x3c: /* XCERH */
5192 s->xcer[7] = value & 0xffff;
5193 return;
5194 }
5195
5196 OMAP_BAD_REG(addr);
5197 }
5198
5199 static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
5200 uint32_t value)
5201 {
5202 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
5203 int offset = addr & OMAP_MPUI_REG_MASK;
5204
5205 if (offset == 0x04) { /* DXR */
5206 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
5207 return;
5208 if (s->tx_req > 3) {
5209 s->tx_req -= 4;
5210 if (s->codec && s->codec->cts) {
5211 s->codec->out.fifo[s->codec->out.len ++] =
5212 (value >> 24) & 0xff;
5213 s->codec->out.fifo[s->codec->out.len ++] =
5214 (value >> 16) & 0xff;
5215 s->codec->out.fifo[s->codec->out.len ++] =
5216 (value >> 8) & 0xff;
5217 s->codec->out.fifo[s->codec->out.len ++] =
5218 (value >> 0) & 0xff;
5219 }
5220 if (s->tx_req < 4)
5221 omap_mcbsp_tx_done(s);
5222 } else
5223 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
5224 return;
5225 }
5226
5227 omap_badwidth_write16(opaque, addr, value);
5228 }
5229
5230 static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
5231 omap_badwidth_read16,
5232 omap_mcbsp_read,
5233 omap_badwidth_read16,
5234 };
5235
5236 static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
5237 omap_badwidth_write16,
5238 omap_mcbsp_writeh,
5239 omap_mcbsp_writew,
5240 };
5241
5242 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
5243 {
5244 memset(&s->spcr, 0, sizeof(s->spcr));
5245 memset(&s->rcr, 0, sizeof(s->rcr));
5246 memset(&s->xcr, 0, sizeof(s->xcr));
5247 s->srgr[0] = 0x0001;
5248 s->srgr[1] = 0x2000;
5249 memset(&s->mcr, 0, sizeof(s->mcr));
5250 memset(&s->pcr, 0, sizeof(s->pcr));
5251 memset(&s->rcer, 0, sizeof(s->rcer));
5252 memset(&s->xcer, 0, sizeof(s->xcer));
5253 s->tx_req = 0;
5254 s->rx_req = 0;
5255 s->tx_rate = 0;
5256 s->rx_rate = 0;
5257 qemu_del_timer(s->source_timer);
5258 qemu_del_timer(s->sink_timer);
5259 }
5260
5261 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
5262 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
5263 {
5264 int iomemtype;
5265 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
5266 qemu_mallocz(sizeof(struct omap_mcbsp_s));
5267
5268 s->base = base;
5269 s->txirq = irq[0];
5270 s->rxirq = irq[1];
5271 s->txdrq = dma[0];
5272 s->rxdrq = dma[1];
5273 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
5274 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
5275 omap_mcbsp_reset(s);
5276
5277 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
5278 omap_mcbsp_writefn, s);
5279 cpu_register_physical_memory(s->base, 0x800, iomemtype);
5280
5281 return s;
5282 }
5283
5284 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
5285 {
5286 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
5287
5288 if (s->rx_rate) {
5289 s->rx_req = s->codec->in.len;
5290 omap_mcbsp_rx_newdata(s);
5291 }
5292 }
5293
5294 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
5295 {
5296 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
5297
5298 if (s->tx_rate) {
5299 s->tx_req = s->codec->out.size;
5300 omap_mcbsp_tx_newdata(s);
5301 }
5302 }
5303
5304 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
5305 {
5306 s->codec = slave;
5307 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
5308 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
5309 }
5310
5311 /* LED Pulse Generators */
5312 struct omap_lpg_s {
5313 target_phys_addr_t base;
5314 QEMUTimer *tm;
5315
5316 uint8_t control;
5317 uint8_t power;
5318 int64_t on;
5319 int64_t period;
5320 int clk;
5321 int cycle;
5322 };
5323
5324 static void omap_lpg_tick(void *opaque)
5325 {
5326 struct omap_lpg_s *s = opaque;
5327
5328 if (s->cycle)
5329 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
5330 else
5331 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
5332
5333 s->cycle = !s->cycle;
5334 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
5335 }
5336
5337 static void omap_lpg_update(struct omap_lpg_s *s)
5338 {
5339 int64_t on, period = 1, ticks = 1000;
5340 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
5341
5342 if (~s->control & (1 << 6)) /* LPGRES */
5343 on = 0;
5344 else if (s->control & (1 << 7)) /* PERM_ON */
5345 on = period;
5346 else {
5347 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
5348 256 / 32);
5349 on = (s->clk && s->power) ? muldiv64(ticks,
5350 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
5351 }
5352
5353 qemu_del_timer(s->tm);
5354 if (on == period && s->on < s->period)
5355 printf("%s: LED is on\n", __FUNCTION__);
5356 else if (on == 0 && s->on)
5357 printf("%s: LED is off\n", __FUNCTION__);
5358 else if (on && (on != s->on || period != s->period)) {
5359 s->cycle = 0;
5360 s->on = on;
5361 s->period = period;
5362 omap_lpg_tick(s);
5363 return;
5364 }
5365
5366 s->on = on;
5367 s->period = period;
5368 }
5369
5370 static void omap_lpg_reset(struct omap_lpg_s *s)
5371 {
5372 s->control = 0x00;
5373 s->power = 0x00;
5374 s->clk = 1;
5375 omap_lpg_update(s);
5376 }
5377
5378 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
5379 {
5380 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
5381 int offset = addr & OMAP_MPUI_REG_MASK;
5382
5383 switch (offset) {
5384 case 0x00: /* LCR */
5385 return s->control;
5386
5387 case 0x04: /* PMR */
5388 return s->power;
5389 }
5390
5391 OMAP_BAD_REG(addr);
5392 return 0;
5393 }
5394
5395 static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
5396 uint32_t value)
5397 {
5398 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
5399 int offset = addr & OMAP_MPUI_REG_MASK;
5400
5401 switch (offset) {
5402 case 0x00: /* LCR */
5403 if (~value & (1 << 6)) /* LPGRES */
5404 omap_lpg_reset(s);
5405 s->control = value & 0xff;
5406 omap_lpg_update(s);
5407 return;
5408
5409 case 0x04: /* PMR */
5410 s->power = value & 0x01;
5411 omap_lpg_update(s);
5412 return;
5413
5414 default:
5415 OMAP_BAD_REG(addr);
5416 return;
5417 }
5418 }
5419
5420 static CPUReadMemoryFunc *omap_lpg_readfn[] = {
5421 omap_lpg_read,
5422 omap_badwidth_read8,
5423 omap_badwidth_read8,
5424 };
5425
5426 static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
5427 omap_lpg_write,
5428 omap_badwidth_write8,
5429 omap_badwidth_write8,
5430 };
5431
5432 static void omap_lpg_clk_update(void *opaque, int line, int on)
5433 {
5434 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
5435
5436 s->clk = on;
5437 omap_lpg_update(s);
5438 }
5439
5440 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
5441 {
5442 int iomemtype;
5443 struct omap_lpg_s *s = (struct omap_lpg_s *)
5444 qemu_mallocz(sizeof(struct omap_lpg_s));
5445
5446 s->base = base;
5447 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
5448
5449 omap_lpg_reset(s);
5450
5451 iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
5452 omap_lpg_writefn, s);
5453 cpu_register_physical_memory(s->base, 0x800, iomemtype);
5454
5455 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
5456
5457 return s;
5458 }
5459
5460 /* MPUI Peripheral Bridge configuration */
5461 static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
5462 {
5463 if (addr == OMAP_MPUI_BASE) /* CMR */
5464 return 0xfe4d;
5465
5466 OMAP_BAD_REG(addr);
5467 return 0;
5468 }
5469
5470 static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
5471 omap_badwidth_read16,
5472 omap_mpui_io_read,
5473 omap_badwidth_read16,
5474 };
5475
5476 static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
5477 omap_badwidth_write16,
5478 omap_badwidth_write16,
5479 omap_badwidth_write16,
5480 };
5481
5482 static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
5483 {
5484 int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
5485 omap_mpui_io_writefn, mpu);
5486 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
5487 }
5488
5489 /* General chip reset */
5490 static void omap_mpu_reset(void *opaque)
5491 {
5492 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
5493
5494 omap_inth_reset(mpu->ih[0]);
5495 omap_inth_reset(mpu->ih[1]);
5496 omap_dma_reset(mpu->dma);
5497 omap_mpu_timer_reset(mpu->timer[0]);
5498 omap_mpu_timer_reset(mpu->timer[1]);
5499 omap_mpu_timer_reset(mpu->timer[2]);
5500 omap_wd_timer_reset(mpu->wdt);
5501 omap_os_timer_reset(mpu->os_timer);
5502 omap_lcdc_reset(mpu->lcd);
5503 omap_ulpd_pm_reset(mpu);
5504 omap_pin_cfg_reset(mpu);
5505 omap_mpui_reset(mpu);
5506 omap_tipb_bridge_reset(mpu->private_tipb);
5507 omap_tipb_bridge_reset(mpu->public_tipb);
5508 omap_dpll_reset(&mpu->dpll[0]);
5509 omap_dpll_reset(&mpu->dpll[1]);
5510 omap_dpll_reset(&mpu->dpll[2]);
5511 omap_uart_reset(mpu->uart[0]);
5512 omap_uart_reset(mpu->uart[1]);
5513 omap_uart_reset(mpu->uart[2]);
5514 omap_mmc_reset(mpu->mmc);
5515 omap_mpuio_reset(mpu->mpuio);
5516 omap_gpio_reset(mpu->gpio);
5517 omap_uwire_reset(mpu->microwire);
5518 omap_pwl_reset(mpu);
5519 omap_pwt_reset(mpu);
5520 omap_i2c_reset(mpu->i2c);
5521 omap_rtc_reset(mpu->rtc);
5522 omap_mcbsp_reset(mpu->mcbsp1);
5523 omap_mcbsp_reset(mpu->mcbsp2);
5524 omap_mcbsp_reset(mpu->mcbsp3);
5525 omap_lpg_reset(mpu->led[0]);
5526 omap_lpg_reset(mpu->led[1]);
5527 omap_clkm_reset(mpu);
5528 cpu_reset(mpu->env);
5529 }
5530
5531 static const struct omap_map_s {
5532 target_phys_addr_t phys_dsp;
5533 target_phys_addr_t phys_mpu;
5534 uint32_t size;
5535 const char *name;
5536 } omap15xx_dsp_mm[] = {
5537 /* Strobe 0 */
5538 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
5539 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
5540 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
5541 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
5542 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
5543 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
5544 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
5545 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
5546 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
5547 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
5548 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
5549 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
5550 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
5551 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
5552 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
5553 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
5554 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
5555 /* Strobe 1 */
5556 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
5557
5558 { 0 }
5559 };
5560
5561 static void omap_setup_dsp_mapping(const struct omap_map_s *map)
5562 {
5563 int io;
5564
5565 for (; map->phys_dsp; map ++) {
5566 io = cpu_get_physical_page_desc(map->phys_mpu);
5567
5568 cpu_register_physical_memory(map->phys_dsp, map->size, io);
5569 }
5570 }
5571
5572 static void omap_mpu_wakeup(void *opaque, int irq, int req)
5573 {
5574 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
5575
5576 if (mpu->env->halted)
5577 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
5578 }
5579
5580 struct dma_irq_map {
5581 int ih;
5582 int intr;
5583 };
5584
5585 static const struct dma_irq_map omap_dma_irq_map[] = {
5586 { 0, OMAP_INT_DMA_CH0_6 },
5587 { 0, OMAP_INT_DMA_CH1_7 },
5588 { 0, OMAP_INT_DMA_CH2_8 },
5589 { 0, OMAP_INT_DMA_CH3 },
5590 { 0, OMAP_INT_DMA_CH4 },
5591 { 0, OMAP_INT_DMA_CH5 },
5592 { 1, OMAP_INT_1610_DMA_CH6 },
5593 { 1, OMAP_INT_1610_DMA_CH7 },
5594 { 1, OMAP_INT_1610_DMA_CH8 },
5595 { 1, OMAP_INT_1610_DMA_CH9 },
5596 { 1, OMAP_INT_1610_DMA_CH10 },
5597 { 1, OMAP_INT_1610_DMA_CH11 },
5598 { 1, OMAP_INT_1610_DMA_CH12 },
5599 { 1, OMAP_INT_1610_DMA_CH13 },
5600 { 1, OMAP_INT_1610_DMA_CH14 },
5601 { 1, OMAP_INT_1610_DMA_CH15 }
5602 };
5603
5604 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
5605 DisplayState *ds, const char *core)
5606 {
5607 int i;
5608 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
5609 qemu_mallocz(sizeof(struct omap_mpu_state_s));
5610 ram_addr_t imif_base, emiff_base;
5611 qemu_irq *cpu_irq;
5612 qemu_irq dma_irqs[6];
5613 int sdindex;
5614
5615 if (!core)
5616 core = "ti925t";
5617
5618 /* Core */
5619 s->mpu_model = omap310;
5620 s->env = cpu_init(core);
5621 if (!s->env) {
5622 fprintf(stderr, "Unable to find CPU definition\n");
5623 exit(1);
5624 }
5625 s->sdram_size = sdram_size;
5626 s->sram_size = OMAP15XX_SRAM_SIZE;
5627
5628 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
5629
5630 /* Clocks */
5631 omap_clk_init(s);
5632
5633 /* Memory-mapped stuff */
5634 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
5635 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
5636 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
5637 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
5638
5639 omap_clkm_init(0xfffece00, 0xe1008000, s);
5640
5641 cpu_irq = arm_pic_init_cpu(s->env);
5642 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1,
5643 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
5644 omap_findclk(s, "arminth_ck"));
5645 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1,
5646 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
5647 omap_findclk(s, "arminth_ck"));
5648 s->irq[0] = s->ih[0]->pins;
5649 s->irq[1] = s->ih[1]->pins;
5650
5651 for (i = 0; i < 6; i ++)
5652 dma_irqs[i] = s->irq[omap_dma_irq_map[i].ih][omap_dma_irq_map[i].intr];
5653 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
5654 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
5655
5656 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
5657 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
5658 s->port[imif ].addr_valid = omap_validate_imif_addr;
5659 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
5660 s->port[local ].addr_valid = omap_validate_local_addr;
5661 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
5662
5663 s->timer[0] = omap_mpu_timer_init(0xfffec500,
5664 s->irq[0][OMAP_INT_TIMER1],
5665 omap_findclk(s, "mputim_ck"));
5666 s->timer[1] = omap_mpu_timer_init(0xfffec600,
5667 s->irq[0][OMAP_INT_TIMER2],
5668 omap_findclk(s, "mputim_ck"));
5669 s->timer[2] = omap_mpu_timer_init(0xfffec700,
5670 s->irq[0][OMAP_INT_TIMER3],
5671 omap_findclk(s, "mputim_ck"));
5672
5673 s->wdt = omap_wd_timer_init(0xfffec800,
5674 s->irq[0][OMAP_INT_WD_TIMER],
5675 omap_findclk(s, "armwdt_ck"));
5676
5677 s->os_timer = omap_os_timer_init(0xfffb9000,
5678 s->irq[1][OMAP_INT_OS_TIMER],
5679 omap_findclk(s, "clk32-kHz"));
5680
5681 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
5682 &s->dma->lcd_ch, ds, imif_base, emiff_base,
5683 omap_findclk(s, "lcd_ck"));
5684
5685 omap_ulpd_pm_init(0xfffe0800, s);
5686 omap_pin_cfg_init(0xfffe1000, s);
5687 omap_id_init(s);
5688
5689 omap_mpui_init(0xfffec900, s);
5690
5691 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
5692 s->irq[0][OMAP_INT_BRIDGE_PRIV],
5693 omap_findclk(s, "tipb_ck"));
5694 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
5695 s->irq[0][OMAP_INT_BRIDGE_PUB],
5696 omap_findclk(s, "tipb_ck"));
5697
5698 omap_tcmi_init(0xfffecc00, s);
5699
5700 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
5701 omap_findclk(s, "uart1_ck"),
5702 serial_hds[0]);
5703 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
5704 omap_findclk(s, "uart2_ck"),
5705 serial_hds[0] ? serial_hds[1] : 0);
5706 s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
5707 omap_findclk(s, "uart3_ck"),
5708 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
5709
5710 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
5711 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
5712 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
5713
5714 sdindex = drive_get_index(IF_SD, 0, 0);
5715 if (sdindex == -1) {
5716 fprintf(stderr, "qemu: missing SecureDigital device\n");
5717 exit(1);
5718 }
5719 s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
5720 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
5721 omap_findclk(s, "mmc_ck"));
5722
5723 s->mpuio = omap_mpuio_init(0xfffb5000,
5724 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
5725 s->wakeup, omap_findclk(s, "clk32-kHz"));
5726
5727 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
5728 omap_findclk(s, "arm_gpio_ck"));
5729
5730 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
5731 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
5732
5733 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
5734 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
5735
5736 s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
5737 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
5738
5739 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
5740 omap_findclk(s, "clk32-kHz"));
5741
5742 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
5743 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
5744 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
5745 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
5746 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
5747 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
5748
5749 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
5750 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
5751
5752 /* Register mappings not currenlty implemented:
5753 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
5754 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
5755 * USB W2FC fffb4000 - fffb47ff
5756 * Camera Interface fffb6800 - fffb6fff
5757 * USB Host fffba000 - fffba7ff
5758 * FAC fffba800 - fffbafff
5759 * HDQ/1-Wire fffbc000 - fffbc7ff
5760 * TIPB switches fffbc800 - fffbcfff
5761 * Mailbox fffcf000 - fffcf7ff
5762 * Local bus IF fffec100 - fffec1ff
5763 * Local bus MMU fffec200 - fffec2ff
5764 * DSP MMU fffed200 - fffed2ff
5765 */
5766
5767 omap_setup_dsp_mapping(omap15xx_dsp_mm);
5768 omap_setup_mpui_io(s);
5769
5770 qemu_register_reset(omap_mpu_reset, s);
5771
5772 return s;
5773 }
Patches shipped by Fedora