hw/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27 #include "qemu-timer.h"
  28
  29 #define D(x)
  30
  31 void etrax_ack_irq(CPUState *env, uint32_t mask);
  32
  33 #define R_TIME 0xb001e038
  34 #define RW_TMR0_DIV 0xb001e000
  35 #define R_TMR0_DATA 0xb001e004
  36 #define RW_TMR0_CTRL 0xb001e008
  37 #define RW_TMR1_DIV 0xb001e010
  38 #define R_TMR1_DATA 0xb001e014
  39 #define RW_TMR1_CTRL 0xb001e018
  40
  41 #define RW_INTR_MASK 0xb001e048
  42 #define RW_ACK_INTR 0xb001e04c
  43 #define R_INTR 0xb001e050
  44 #define R_MASKED_INTR 0xb001e054
  45
  46
  47 uint32_t rw_intr_mask;
  48 uint32_t rw_ack_intr;
  49 uint32_t r_intr;
  50
  51 struct fs_timer_t {
  52         QEMUBH *bh;
  53         unsigned int limit;
  54         int scale;
  55         ptimer_state *ptimer;
  56         CPUState *env;
  57         qemu_irq *irq;
  58         uint32_t mask;
  59         struct timeval last;
  60 };
  61
  62 static struct fs_timer_t timer[2];
  63
  64 static inline int timer_index(target_phys_addr_t addr)
  65 {
  66         int t = 0;
  67         if (addr >= 0xb005e000)
  68                 t = 1;
  69         return t;
  70 }
  71
  72 /* diff two timevals.  Return a single int in us. */
  73 int diff_timeval_us(struct timeval *a, struct timeval *b)
  74 {
  75         int diff;
  76
  77         /* assume these values are signed.  */
  78         diff = (a->tv_sec - b->tv_sec) * 1000 * 1000;
  79         diff += (a->tv_usec - b->tv_usec);
  80         return diff;
  81 }
  82
  83 static uint32_t timer_readb (void *opaque, target_phys_addr_t addr)
  84 {
  85         CPUState *env;
  86         uint32_t r = 0;
  87
  88         env = opaque;
  89         D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
  90         return r;
  91 }
  92 static uint32_t timer_readw (void *opaque, target_phys_addr_t addr)
  93 {
  94         CPUState *env;
  95         uint32_t r = 0;
  96
  97         env = opaque;
  98         D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
  99         return r;
 100 }
 101
 102 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
 103 {
 104         CPUState *env = opaque;
 105         uint32_t r = 0;
 106         int t = timer_index(addr);
 107
 108         switch (addr) {
 109         case R_TMR0_DATA:
 110                 break;
 111         case R_TMR1_DATA:
 112                 D(printf ("R_TMR1_DATA\n"));
 113                 break;
 114         case R_TIME:
 115         {
 116                 struct timeval now;
 117                 gettimeofday(&now, NULL);
 118                 if (!(timer[t].last.tv_sec == 0
 119                       && timer[t].last.tv_usec == 0)) {
 120                         r = diff_timeval_us(&now, &timer[t].last);
 121                         r *= 1000; /* convert to ns.  */
 122                         r++; /* make sure we increase for each call.  */
 123                 }
 124                 timer[t].last = now;
 125                 break;
 126         }
 127
 128         case RW_INTR_MASK:
 129                 r = rw_intr_mask;
 130                 break;
 131         case R_MASKED_INTR:
 132                 r = r_intr & rw_intr_mask;
 133                 break;
 134         default:
 135                 printf ("%s %x p=%x\n", __func__, addr, env->pc);
 136                 break;
 137         }
 138         return r;
 139 }
 140
 141 static void
 142 timer_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 143 {
 144         CPUState *env;
 145         env = opaque;
 146         D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
 147 }
 148 static void
 149 timer_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 150 {
 151         CPUState *env;
 152         env = opaque;
 153         D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
 154 }
 155
 156 static void write_ctrl(struct fs_timer_t *t, uint32_t v)
 157 {
 158         int op;
 159         int freq;
 160         int freq_hz;
 161
 162         op = v & 3;
 163         freq = v >> 2;
 164         freq_hz = 32000000;
 165
 166         switch (freq)
 167         {
 168         case 0:
 169         case 1:
 170                 printf ("extern or disabled timer clock?\n");
 171                 break;
 172         case 4: freq_hz =  29493000; break;
 173         case 5: freq_hz =  32000000; break;
 174         case 6: freq_hz =  32768000; break;
 175         case 7: freq_hz = 100000000; break;
 176         default:
 177                 abort();
 178                 break;
 179         }
 180
 181         printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit);
 182         t->scale = 0;
 183         if (t->limit > 2048)
 184         {
 185                 t->scale = 2048;
 186                 ptimer_set_period(t->ptimer, freq_hz / t->scale);
 187         }
 188
 189         printf ("op=%d\n", op);
 190         switch (op)
 191         {
 192                 case 0:
 193                         printf ("limit=%d %d\n", t->limit, t->limit/t->scale);
 194                         ptimer_set_limit(t->ptimer, t->limit / t->scale, 1);
 195                         break;
 196                 case 1:
 197                         ptimer_stop(t->ptimer);
 198                         break;
 199                 case 2:
 200                         ptimer_run(t->ptimer, 0);
 201                         break;
 202                 default:
 203                         abort();
 204                         break;
 205         }
 206 }
 207
 208 static void timer_ack_irq(struct fs_timer_t *t)
 209 {
 210         if (!(r_intr & t->mask & rw_intr_mask)) {
 211                 qemu_irq_lower(t->irq[0]);
 212                 etrax_ack_irq(t->env, 1 << 0x1b);
 213         }
 214 }
 215
 216 static void
 217 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 218 {
 219         CPUState *env = opaque;
 220         int t = timer_index(addr);
 221
 222         D(printf ("%s %x %x pc=%x\n",
 223                 __func__, addr, value, env->pc));
 224         switch (addr)
 225         {
 226                 case RW_TMR0_DIV:
 227                         D(printf ("RW_TMR0_DIV=%x\n", value));
 228                         timer[t].limit = value;
 229                         break;
 230                 case RW_TMR0_CTRL:
 231                         D(printf ("RW_TMR0_CTRL=%x\n", value));
 232                         write_ctrl(&timer[t], value);
 233                         break;
 234                 case RW_TMR1_DIV:
 235                         D(printf ("RW_TMR1_DIV=%x\n", value));
 236                         break;
 237                 case RW_TMR1_CTRL:
 238                         D(printf ("RW_TMR1_CTRL=%x\n", value));
 239                         break;
 240                 case RW_INTR_MASK:
 241                         D(printf ("RW_INTR_MASK=%x\n", value));
 242                         rw_intr_mask = value;
 243                         break;
 244                 case RW_ACK_INTR:
 245                         r_intr &= ~value;
 246                         timer_ack_irq(&timer[t]);
 247                         break;
 248                 default:
 249                         printf ("%s %x %x pc=%x\n",
 250                                 __func__, addr, value, env->pc);
 251                         break;
 252         }
 253 }
 254
 255 static CPUReadMemoryFunc *timer_read[] = {
 256     &timer_readb,
 257     &timer_readw,
 258     &timer_readl,
 259 };
 260
 261 static CPUWriteMemoryFunc *timer_write[] = {
 262     &timer_writeb,
 263     &timer_writew,
 264     &timer_writel,
 265 };
 266
 267 static void timer_irq(void *opaque)
 268 {
 269         struct fs_timer_t *t = opaque;
 270         r_intr |= t->mask;
 271         if (t->mask & rw_intr_mask) {
 272                 qemu_irq_raise(t->irq[0]);
 273         }
 274 }
 275
 276 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs)
 277 {
 278         int timer_regs;
 279
 280         timer[0].bh = qemu_bh_new(timer_irq, &timer[0]);
 281         timer[0].ptimer = ptimer_init(timer[0].bh);
 282         timer[0].irq = irqs + 0x1b;
 283         timer[0].mask = 1;
 284         timer[0].env = env;
 285
 286         timer[1].bh = qemu_bh_new(timer_irq, &timer[1]);
 287         timer[1].ptimer = ptimer_init(timer[1].bh);
 288         timer[1].irq = irqs + 0x1b;
 289         timer[1].mask = 1;
 290         timer[1].env = env;
 291
 292         timer_regs = cpu_register_io_memory(0, timer_read, timer_write, env);
 293         cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs);
 294         cpu_register_physical_memory (0xb005e000, 0x5c, timer_regs);
 295 }