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Pci hotplug GPE support
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blobe14ec356cd991fa698ea904e2ec8c53d02222337
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #ifndef _WIN32
35 #include <sys/mman.h>
36 #endif
37 #include "qemu-kvm.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
56
57 // ID
58 #define CIRRUS_ID_CLGD5422 (0x23<<2)
59 #define CIRRUS_ID_CLGD5426 (0x24<<2)
60 #define CIRRUS_ID_CLGD5424 (0x25<<2)
61 #define CIRRUS_ID_CLGD5428 (0x26<<2)
62 #define CIRRUS_ID_CLGD5430 (0x28<<2)
63 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
64 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
65 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
66
67 // sequencer 0x07
68 #define CIRRUS_SR7_BPP_VGA 0x00
69 #define CIRRUS_SR7_BPP_SVGA 0x01
70 #define CIRRUS_SR7_BPP_MASK 0x0e
71 #define CIRRUS_SR7_BPP_8 0x00
72 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
73 #define CIRRUS_SR7_BPP_24 0x04
74 #define CIRRUS_SR7_BPP_16 0x06
75 #define CIRRUS_SR7_BPP_32 0x08
76 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
77
78 // sequencer 0x0f
79 #define CIRRUS_MEMSIZE_512k 0x08
80 #define CIRRUS_MEMSIZE_1M 0x10
81 #define CIRRUS_MEMSIZE_2M 0x18
82 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
83
84 // sequencer 0x12
85 #define CIRRUS_CURSOR_SHOW 0x01
86 #define CIRRUS_CURSOR_HIDDENPEL 0x02
87 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
88
89 // sequencer 0x17
90 #define CIRRUS_BUSTYPE_VLBFAST 0x10
91 #define CIRRUS_BUSTYPE_PCI 0x20
92 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
93 #define CIRRUS_BUSTYPE_ISA 0x38
94 #define CIRRUS_MMIO_ENABLE 0x04
95 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
96 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
97
98 // control 0x0b
99 #define CIRRUS_BANKING_DUAL 0x01
100 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
101
102 // control 0x30
103 #define CIRRUS_BLTMODE_BACKWARDS 0x01
104 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
105 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
106 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
107 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
108 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
109 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
110 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
111 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
112 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
113 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
114
115 // control 0x31
116 #define CIRRUS_BLT_BUSY 0x01
117 #define CIRRUS_BLT_START 0x02
118 #define CIRRUS_BLT_RESET 0x04
119 #define CIRRUS_BLT_FIFOUSED 0x10
120 #define CIRRUS_BLT_AUTOSTART 0x80
121
122 // control 0x32
123 #define CIRRUS_ROP_0 0x00
124 #define CIRRUS_ROP_SRC_AND_DST 0x05
125 #define CIRRUS_ROP_NOP 0x06
126 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
127 #define CIRRUS_ROP_NOTDST 0x0b
128 #define CIRRUS_ROP_SRC 0x0d
129 #define CIRRUS_ROP_1 0x0e
130 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
131 #define CIRRUS_ROP_SRC_XOR_DST 0x59
132 #define CIRRUS_ROP_SRC_OR_DST 0x6d
133 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
134 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
135 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
136 #define CIRRUS_ROP_NOTSRC 0xd0
137 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
138 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
139
140 #define CIRRUS_ROP_NOP_INDEX 2
141 #define CIRRUS_ROP_SRC_INDEX 5
142
143 // control 0x33
144 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
145 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
146 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
147
148 // memory-mapped IO
149 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
150 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
151 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
152 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
153 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
154 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
155 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
156 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
157 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
158 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
159 #define CIRRUS_MMIO_BLTROP 0x1a // byte
160 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
161 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
162 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
163 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
164 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
165 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
166 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
169 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
170 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
171 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
172 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
173 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
174 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
175 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
176 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
177 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
178
179 // PCI 0x00: vendor, 0x02: device
180 #define PCI_VENDOR_CIRRUS 0x1013
181 #define PCI_DEVICE_CLGD5462 0x00d0
182 #define PCI_DEVICE_CLGD5465 0x00d6
183
184 // PCI 0x04: command(word), 0x06(word): status
185 #define PCI_COMMAND_IOACCESS 0x0001
186 #define PCI_COMMAND_MEMACCESS 0x0002
187 #define PCI_COMMAND_BUSMASTER 0x0004
188 #define PCI_COMMAND_SPECIALCYCLE 0x0008
189 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
190 #define PCI_COMMAND_PALETTESNOOPING 0x0020
191 #define PCI_COMMAND_PARITYDETECTION 0x0040
192 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
193 #define PCI_COMMAND_SERR 0x0100
194 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
195 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
196 #define PCI_CLASS_BASE_DISPLAY 0x03
197 // PCI 0x08, 0x00ff0000
198 #define PCI_CLASS_SUB_VGA 0x00
199 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
200 #define PCI_CLASS_HEADERTYPE_00h 0x00
201 // 0x10-0x3f (headertype 00h)
202 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
203 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
204 #define PCI_MAP_MEM 0x0
205 #define PCI_MAP_IO 0x1
206 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
207 #define PCI_MAP_IO_ADDR_MASK (~0x3)
208 #define PCI_MAP_MEMFLAGS_32BIT 0x0
209 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
210 #define PCI_MAP_MEMFLAGS_64BIT 0x4
211 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
212 // PCI 0x28: cardbus CIS pointer
213 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
214 // PCI 0x30: expansion ROM base address
215 #define PCI_ROMBIOS_ENABLED 0x1
216 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
217 // PCI 0x38: reserved
218 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
219
220 #define CIRRUS_PNPMMIO_SIZE 0x1000
221
222
223 /* I/O and memory hook */
224 #define CIRRUS_HOOK_NOT_HANDLED 0
225 #define CIRRUS_HOOK_HANDLED 1
226
227 struct CirrusVGAState;
228 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
229 uint8_t * dst, const uint8_t * src,
230 int dstpitch, int srcpitch,
231 int bltwidth, int bltheight);
232 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
233 uint8_t *dst, int dst_pitch, int width, int height);
234
235 typedef struct CirrusVGAState {
236 VGA_STATE_COMMON
237
238 int cirrus_linear_io_addr;
239 int cirrus_linear_bitblt_io_addr;
240 int cirrus_mmio_io_addr;
241 unsigned long cirrus_lfb_addr;
242 unsigned long cirrus_lfb_end;
243 uint32_t cirrus_addr_mask;
244 uint32_t linear_mmio_mask;
245 uint8_t cirrus_shadow_gr0;
246 uint8_t cirrus_shadow_gr1;
247 uint8_t cirrus_hidden_dac_lockindex;
248 uint8_t cirrus_hidden_dac_data;
249 uint32_t cirrus_bank_base[2];
250 uint32_t cirrus_bank_limit[2];
251 uint8_t cirrus_hidden_palette[48];
252 uint32_t hw_cursor_x;
253 uint32_t hw_cursor_y;
254 int cirrus_blt_pixelwidth;
255 int cirrus_blt_width;
256 int cirrus_blt_height;
257 int cirrus_blt_dstpitch;
258 int cirrus_blt_srcpitch;
259 uint32_t cirrus_blt_fgcol;
260 uint32_t cirrus_blt_bgcol;
261 uint32_t cirrus_blt_dstaddr;
262 uint32_t cirrus_blt_srcaddr;
263 uint8_t cirrus_blt_mode;
264 uint8_t cirrus_blt_modeext;
265 cirrus_bitblt_rop_t cirrus_rop;
266 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
267 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
268 uint8_t *cirrus_srcptr;
269 uint8_t *cirrus_srcptr_end;
270 uint32_t cirrus_srccounter;
271 /* hwcursor display state */
272 int last_hw_cursor_size;
273 int last_hw_cursor_x;
274 int last_hw_cursor_y;
275 int last_hw_cursor_y_start;
276 int last_hw_cursor_y_end;
277 int real_vram_size; /* XXX: suppress that */
278 CPUWriteMemoryFunc **cirrus_linear_write;
279 } CirrusVGAState;
280
281 typedef struct PCICirrusVGAState {
282 PCIDevice dev;
283 CirrusVGAState cirrus_vga;
284 } PCICirrusVGAState;
285
286 static uint8_t rop_to_index[256];
287
288 /***************************************
289 *
290 * prototypes.
291 *
292 ***************************************/
293
294
295 static void cirrus_bitblt_reset(CirrusVGAState *s);
296 static void cirrus_update_memory_access(CirrusVGAState *s);
297
298 /***************************************
299 *
300 * raster operations
301 *
302 ***************************************/
303
304 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
305 uint8_t *dst,const uint8_t *src,
306 int dstpitch,int srcpitch,
307 int bltwidth,int bltheight)
308 {
309 }
310
311 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
312 uint8_t *dst,
313 int dstpitch, int bltwidth,int bltheight)
314 {
315 }
316
317 #define ROP_NAME 0
318 #define ROP_OP(d, s) d = 0
319 #include "cirrus_vga_rop.h"
320
321 #define ROP_NAME src_and_dst
322 #define ROP_OP(d, s) d = (s) & (d)
323 #include "cirrus_vga_rop.h"
324
325 #define ROP_NAME src_and_notdst
326 #define ROP_OP(d, s) d = (s) & (~(d))
327 #include "cirrus_vga_rop.h"
328
329 #define ROP_NAME notdst
330 #define ROP_OP(d, s) d = ~(d)
331 #include "cirrus_vga_rop.h"
332
333 #define ROP_NAME src
334 #define ROP_OP(d, s) d = s
335 #include "cirrus_vga_rop.h"
336
337 #define ROP_NAME 1
338 #define ROP_OP(d, s) d = ~0
339 #include "cirrus_vga_rop.h"
340
341 #define ROP_NAME notsrc_and_dst
342 #define ROP_OP(d, s) d = (~(s)) & (d)
343 #include "cirrus_vga_rop.h"
344
345 #define ROP_NAME src_xor_dst
346 #define ROP_OP(d, s) d = (s) ^ (d)
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME src_or_dst
350 #define ROP_OP(d, s) d = (s) | (d)
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME notsrc_or_notdst
354 #define ROP_OP(d, s) d = (~(s)) | (~(d))
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME src_notxor_dst
358 #define ROP_OP(d, s) d = ~((s) ^ (d))
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME src_or_notdst
362 #define ROP_OP(d, s) d = (s) | (~(d))
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME notsrc
366 #define ROP_OP(d, s) d = (~(s))
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME notsrc_or_dst
370 #define ROP_OP(d, s) d = (~(s)) | (d)
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME notsrc_and_notdst
374 #define ROP_OP(d, s) d = (~(s)) & (~(d))
375 #include "cirrus_vga_rop.h"
376
377 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
378 cirrus_bitblt_rop_fwd_0,
379 cirrus_bitblt_rop_fwd_src_and_dst,
380 cirrus_bitblt_rop_nop,
381 cirrus_bitblt_rop_fwd_src_and_notdst,
382 cirrus_bitblt_rop_fwd_notdst,
383 cirrus_bitblt_rop_fwd_src,
384 cirrus_bitblt_rop_fwd_1,
385 cirrus_bitblt_rop_fwd_notsrc_and_dst,
386 cirrus_bitblt_rop_fwd_src_xor_dst,
387 cirrus_bitblt_rop_fwd_src_or_dst,
388 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
389 cirrus_bitblt_rop_fwd_src_notxor_dst,
390 cirrus_bitblt_rop_fwd_src_or_notdst,
391 cirrus_bitblt_rop_fwd_notsrc,
392 cirrus_bitblt_rop_fwd_notsrc_or_dst,
393 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
394 };
395
396 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
397 cirrus_bitblt_rop_bkwd_0,
398 cirrus_bitblt_rop_bkwd_src_and_dst,
399 cirrus_bitblt_rop_nop,
400 cirrus_bitblt_rop_bkwd_src_and_notdst,
401 cirrus_bitblt_rop_bkwd_notdst,
402 cirrus_bitblt_rop_bkwd_src,
403 cirrus_bitblt_rop_bkwd_1,
404 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
405 cirrus_bitblt_rop_bkwd_src_xor_dst,
406 cirrus_bitblt_rop_bkwd_src_or_dst,
407 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
408 cirrus_bitblt_rop_bkwd_src_notxor_dst,
409 cirrus_bitblt_rop_bkwd_src_or_notdst,
410 cirrus_bitblt_rop_bkwd_notsrc,
411 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
412 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
413 };
414
415 #define TRANSP_ROP(name) {\
416 name ## _8,\
417 name ## _16,\
418 }
419 #define TRANSP_NOP(func) {\
420 func,\
421 func,\
422 }
423
424 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
425 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
426 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
427 TRANSP_NOP(cirrus_bitblt_rop_nop),
428 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
441 };
442
443 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
444 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
445 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
446 TRANSP_NOP(cirrus_bitblt_rop_nop),
447 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
460 };
461
462 #define ROP2(name) {\
463 name ## _8,\
464 name ## _16,\
465 name ## _24,\
466 name ## _32,\
467 }
468
469 #define ROP_NOP2(func) {\
470 func,\
471 func,\
472 func,\
473 func,\
474 }
475
476 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
477 ROP2(cirrus_patternfill_0),
478 ROP2(cirrus_patternfill_src_and_dst),
479 ROP_NOP2(cirrus_bitblt_rop_nop),
480 ROP2(cirrus_patternfill_src_and_notdst),
481 ROP2(cirrus_patternfill_notdst),
482 ROP2(cirrus_patternfill_src),
483 ROP2(cirrus_patternfill_1),
484 ROP2(cirrus_patternfill_notsrc_and_dst),
485 ROP2(cirrus_patternfill_src_xor_dst),
486 ROP2(cirrus_patternfill_src_or_dst),
487 ROP2(cirrus_patternfill_notsrc_or_notdst),
488 ROP2(cirrus_patternfill_src_notxor_dst),
489 ROP2(cirrus_patternfill_src_or_notdst),
490 ROP2(cirrus_patternfill_notsrc),
491 ROP2(cirrus_patternfill_notsrc_or_dst),
492 ROP2(cirrus_patternfill_notsrc_and_notdst),
493 };
494
495 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
496 ROP2(cirrus_colorexpand_transp_0),
497 ROP2(cirrus_colorexpand_transp_src_and_dst),
498 ROP_NOP2(cirrus_bitblt_rop_nop),
499 ROP2(cirrus_colorexpand_transp_src_and_notdst),
500 ROP2(cirrus_colorexpand_transp_notdst),
501 ROP2(cirrus_colorexpand_transp_src),
502 ROP2(cirrus_colorexpand_transp_1),
503 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
504 ROP2(cirrus_colorexpand_transp_src_xor_dst),
505 ROP2(cirrus_colorexpand_transp_src_or_dst),
506 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
507 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
508 ROP2(cirrus_colorexpand_transp_src_or_notdst),
509 ROP2(cirrus_colorexpand_transp_notsrc),
510 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
511 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
512 };
513
514 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
515 ROP2(cirrus_colorexpand_0),
516 ROP2(cirrus_colorexpand_src_and_dst),
517 ROP_NOP2(cirrus_bitblt_rop_nop),
518 ROP2(cirrus_colorexpand_src_and_notdst),
519 ROP2(cirrus_colorexpand_notdst),
520 ROP2(cirrus_colorexpand_src),
521 ROP2(cirrus_colorexpand_1),
522 ROP2(cirrus_colorexpand_notsrc_and_dst),
523 ROP2(cirrus_colorexpand_src_xor_dst),
524 ROP2(cirrus_colorexpand_src_or_dst),
525 ROP2(cirrus_colorexpand_notsrc_or_notdst),
526 ROP2(cirrus_colorexpand_src_notxor_dst),
527 ROP2(cirrus_colorexpand_src_or_notdst),
528 ROP2(cirrus_colorexpand_notsrc),
529 ROP2(cirrus_colorexpand_notsrc_or_dst),
530 ROP2(cirrus_colorexpand_notsrc_and_notdst),
531 };
532
533 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
534 ROP2(cirrus_colorexpand_pattern_transp_0),
535 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
536 ROP_NOP2(cirrus_bitblt_rop_nop),
537 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
538 ROP2(cirrus_colorexpand_pattern_transp_notdst),
539 ROP2(cirrus_colorexpand_pattern_transp_src),
540 ROP2(cirrus_colorexpand_pattern_transp_1),
541 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
542 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
543 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
544 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
545 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
546 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
547 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
548 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
549 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
550 };
551
552 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
553 ROP2(cirrus_colorexpand_pattern_0),
554 ROP2(cirrus_colorexpand_pattern_src_and_dst),
555 ROP_NOP2(cirrus_bitblt_rop_nop),
556 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
557 ROP2(cirrus_colorexpand_pattern_notdst),
558 ROP2(cirrus_colorexpand_pattern_src),
559 ROP2(cirrus_colorexpand_pattern_1),
560 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
561 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
562 ROP2(cirrus_colorexpand_pattern_src_or_dst),
563 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
564 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
565 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
566 ROP2(cirrus_colorexpand_pattern_notsrc),
567 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
568 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
569 };
570
571 static const cirrus_fill_t cirrus_fill[16][4] = {
572 ROP2(cirrus_fill_0),
573 ROP2(cirrus_fill_src_and_dst),
574 ROP_NOP2(cirrus_bitblt_fill_nop),
575 ROP2(cirrus_fill_src_and_notdst),
576 ROP2(cirrus_fill_notdst),
577 ROP2(cirrus_fill_src),
578 ROP2(cirrus_fill_1),
579 ROP2(cirrus_fill_notsrc_and_dst),
580 ROP2(cirrus_fill_src_xor_dst),
581 ROP2(cirrus_fill_src_or_dst),
582 ROP2(cirrus_fill_notsrc_or_notdst),
583 ROP2(cirrus_fill_src_notxor_dst),
584 ROP2(cirrus_fill_src_or_notdst),
585 ROP2(cirrus_fill_notsrc),
586 ROP2(cirrus_fill_notsrc_or_dst),
587 ROP2(cirrus_fill_notsrc_and_notdst),
588 };
589
590 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
591 {
592 unsigned int color;
593 switch (s->cirrus_blt_pixelwidth) {
594 case 1:
595 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
596 break;
597 case 2:
598 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
599 s->cirrus_blt_fgcol = le16_to_cpu(color);
600 break;
601 case 3:
602 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
603 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
604 break;
605 default:
606 case 4:
607 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
608 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
609 s->cirrus_blt_fgcol = le32_to_cpu(color);
610 break;
611 }
612 }
613
614 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
615 {
616 unsigned int color;
617 switch (s->cirrus_blt_pixelwidth) {
618 case 1:
619 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
620 break;
621 case 2:
622 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
623 s->cirrus_blt_bgcol = le16_to_cpu(color);
624 break;
625 case 3:
626 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
627 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
628 break;
629 default:
630 case 4:
631 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
632 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
633 s->cirrus_blt_bgcol = le32_to_cpu(color);
634 break;
635 }
636 }
637
638 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
639 int off_pitch, int bytesperline,
640 int lines)
641 {
642 int y;
643 int off_cur;
644 int off_cur_end;
645
646 for (y = 0; y < lines; y++) {
647 off_cur = off_begin;
648 off_cur_end = off_cur + bytesperline;
649 off_cur &= TARGET_PAGE_MASK;
650 while (off_cur < off_cur_end) {
651 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
652 off_cur += TARGET_PAGE_SIZE;
653 }
654 off_begin += off_pitch;
655 }
656 }
657
658 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
659 const uint8_t * src)
660 {
661 uint8_t *dst;
662
663 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
664 (*s->cirrus_rop) (s, dst, src,
665 s->cirrus_blt_dstpitch, 0,
666 s->cirrus_blt_width, s->cirrus_blt_height);
667 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
668 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
669 s->cirrus_blt_height);
670 return 1;
671 }
672
673 /* fill */
674
675 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
676 {
677 cirrus_fill_t rop_func;
678
679 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
680 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
681 s->cirrus_blt_dstpitch,
682 s->cirrus_blt_width, s->cirrus_blt_height);
683 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
684 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
685 s->cirrus_blt_height);
686 cirrus_bitblt_reset(s);
687 return 1;
688 }
689
690 /***************************************
691 *
692 * bitblt (video-to-video)
693 *
694 ***************************************/
695
696 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
697 {
698 return cirrus_bitblt_common_patterncopy(s,
699 s->vram_ptr +
700 (s->cirrus_blt_srcaddr & ~7));
701 }
702
703 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
704 {
705 int sx, sy;
706 int dx, dy;
707 int width, height;
708 int depth;
709 int notify = 0;
710
711 depth = s->get_bpp((VGAState *)s) / 8;
712 s->get_resolution((VGAState *)s, &width, &height);
713
714 /* extra x, y */
715 sx = (src % (width * depth)) / depth;
716 sy = (src / (width * depth));
717 dx = (dst % (width *depth)) / depth;
718 dy = (dst / (width * depth));
719
720 /* normalize width */
721 w /= depth;
722
723 /* if we're doing a backward copy, we have to adjust
724 our x/y to be the upper left corner (instead of the lower
725 right corner) */
726 if (s->cirrus_blt_dstpitch < 0) {
727 sx -= (s->cirrus_blt_width / depth) - 1;
728 dx -= (s->cirrus_blt_width / depth) - 1;
729 sy -= s->cirrus_blt_height - 1;
730 dy -= s->cirrus_blt_height - 1;
731 }
732
733 /* are we in the visible portion of memory? */
734 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
735 (sx + w) <= width && (sy + h) <= height &&
736 (dx + w) <= width && (dy + h) <= height) {
737 notify = 1;
738 }
739
740 /* make to sure only copy if it's a plain copy ROP */
741 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
742 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
743 notify = 0;
744
745 /* we have to flush all pending changes so that the copy
746 is generated at the appropriate moment in time */
747 if (notify)
748 vga_hw_update();
749
750 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
751 s->vram_ptr + s->cirrus_blt_srcaddr,
752 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
753 s->cirrus_blt_width, s->cirrus_blt_height);
754
755 if (notify)
756 s->ds->dpy_copy(s->ds,
757 sx, sy, dx, dy,
758 s->cirrus_blt_width / depth,
759 s->cirrus_blt_height);
760
761 /* we don't have to notify the display that this portion has
762 changed since dpy_copy implies this */
763
764 if (!notify)
765 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
766 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
767 s->cirrus_blt_height);
768 }
769
770 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
771 {
772 if (s->ds->dpy_copy) {
773 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
774 s->cirrus_blt_srcaddr - s->start_addr,
775 s->cirrus_blt_width, s->cirrus_blt_height);
776 } else {
777 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
778 s->vram_ptr + s->cirrus_blt_srcaddr,
779 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
780 s->cirrus_blt_width, s->cirrus_blt_height);
781
782 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
783 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
784 s->cirrus_blt_height);
785 }
786
787 return 1;
788 }
789
790 /***************************************
791 *
792 * bitblt (cpu-to-video)
793 *
794 ***************************************/
795
796 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
797 {
798 int copy_count;
799 uint8_t *end_ptr;
800
801 if (s->cirrus_srccounter > 0) {
802 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
803 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
804 the_end:
805 s->cirrus_srccounter = 0;
806 cirrus_bitblt_reset(s);
807 } else {
808 /* at least one scan line */
809 do {
810 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
811 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
812 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
813 s->cirrus_blt_width, 1);
814 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
815 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
816 if (s->cirrus_srccounter <= 0)
817 goto the_end;
818 /* more bytes than needed can be transfered because of
819 word alignment, so we keep them for the next line */
820 /* XXX: keep alignment to speed up transfer */
821 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
822 copy_count = s->cirrus_srcptr_end - end_ptr;
823 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
824 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
825 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
826 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
827 }
828 }
829 }
830
831 /***************************************
832 *
833 * bitblt wrapper
834 *
835 ***************************************/
836
837 static void cirrus_bitblt_reset(CirrusVGAState * s)
838 {
839 s->gr[0x31] &=
840 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
841 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
842 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
843 s->cirrus_srccounter = 0;
844 cirrus_update_memory_access(s);
845 }
846
847 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
848 {
849 int w;
850
851 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
852 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
853 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
854
855 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
856 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
857 s->cirrus_blt_srcpitch = 8;
858 } else {
859 /* XXX: check for 24 bpp */
860 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
861 }
862 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
863 } else {
864 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
865 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
866 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
867 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
868 else
869 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
870 } else {
871 /* always align input size to 32 bits */
872 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
873 }
874 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
875 }
876 s->cirrus_srcptr = s->cirrus_bltbuf;
877 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
878 cirrus_update_memory_access(s);
879 return 1;
880 }
881
882 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
883 {
884 /* XXX */
885 #ifdef DEBUG_BITBLT
886 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
887 #endif
888 return 0;
889 }
890
891 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
892 {
893 int ret;
894
895 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
896 ret = cirrus_bitblt_videotovideo_patterncopy(s);
897 } else {
898 ret = cirrus_bitblt_videotovideo_copy(s);
899 }
900 if (ret)
901 cirrus_bitblt_reset(s);
902 return ret;
903 }
904
905 static void cirrus_bitblt_start(CirrusVGAState * s)
906 {
907 uint8_t blt_rop;
908
909 s->gr[0x31] |= CIRRUS_BLT_BUSY;
910
911 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
912 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
913 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
914 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
915 s->cirrus_blt_dstaddr =
916 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
917 s->cirrus_blt_srcaddr =
918 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
919 s->cirrus_blt_mode = s->gr[0x30];
920 s->cirrus_blt_modeext = s->gr[0x33];
921 blt_rop = s->gr[0x32];
922
923 #ifdef DEBUG_BITBLT
924 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
925 blt_rop,
926 s->cirrus_blt_mode,
927 s->cirrus_blt_modeext,
928 s->cirrus_blt_width,
929 s->cirrus_blt_height,
930 s->cirrus_blt_dstpitch,
931 s->cirrus_blt_srcpitch,
932 s->cirrus_blt_dstaddr,
933 s->cirrus_blt_srcaddr,
934 s->gr[0x2f]);
935 #endif
936
937 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
938 case CIRRUS_BLTMODE_PIXELWIDTH8:
939 s->cirrus_blt_pixelwidth = 1;
940 break;
941 case CIRRUS_BLTMODE_PIXELWIDTH16:
942 s->cirrus_blt_pixelwidth = 2;
943 break;
944 case CIRRUS_BLTMODE_PIXELWIDTH24:
945 s->cirrus_blt_pixelwidth = 3;
946 break;
947 case CIRRUS_BLTMODE_PIXELWIDTH32:
948 s->cirrus_blt_pixelwidth = 4;
949 break;
950 default:
951 #ifdef DEBUG_BITBLT
952 printf("cirrus: bitblt - pixel width is unknown\n");
953 #endif
954 goto bitblt_ignore;
955 }
956 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
957
958 if ((s->
959 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
960 CIRRUS_BLTMODE_MEMSYSDEST))
961 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
962 #ifdef DEBUG_BITBLT
963 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
964 #endif
965 goto bitblt_ignore;
966 }
967
968 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
969 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
970 CIRRUS_BLTMODE_TRANSPARENTCOMP |
971 CIRRUS_BLTMODE_PATTERNCOPY |
972 CIRRUS_BLTMODE_COLOREXPAND)) ==
973 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
974 cirrus_bitblt_fgcol(s);
975 cirrus_bitblt_solidfill(s, blt_rop);
976 } else {
977 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
978 CIRRUS_BLTMODE_PATTERNCOPY)) ==
979 CIRRUS_BLTMODE_COLOREXPAND) {
980
981 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
982 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
983 cirrus_bitblt_bgcol(s);
984 else
985 cirrus_bitblt_fgcol(s);
986 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
987 } else {
988 cirrus_bitblt_fgcol(s);
989 cirrus_bitblt_bgcol(s);
990 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
991 }
992 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
993 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
994 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
995 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
996 cirrus_bitblt_bgcol(s);
997 else
998 cirrus_bitblt_fgcol(s);
999 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1000 } else {
1001 cirrus_bitblt_fgcol(s);
1002 cirrus_bitblt_bgcol(s);
1003 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1004 }
1005 } else {
1006 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1007 }
1008 } else {
1009 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1010 if (s->cirrus_blt_pixelwidth > 2) {
1011 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1012 goto bitblt_ignore;
1013 }
1014 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1015 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1016 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1017 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1018 } else {
1019 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1020 }
1021 } else {
1022 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1023 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1024 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1025 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1026 } else {
1027 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1028 }
1029 }
1030 }
1031 // setup bitblt engine.
1032 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1033 if (!cirrus_bitblt_cputovideo(s))
1034 goto bitblt_ignore;
1035 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1036 if (!cirrus_bitblt_videotocpu(s))
1037 goto bitblt_ignore;
1038 } else {
1039 if (!cirrus_bitblt_videotovideo(s))
1040 goto bitblt_ignore;
1041 }
1042 }
1043 return;
1044 bitblt_ignore:;
1045 cirrus_bitblt_reset(s);
1046 }
1047
1048 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1049 {
1050 unsigned old_value;
1051
1052 old_value = s->gr[0x31];
1053 s->gr[0x31] = reg_value;
1054
1055 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1056 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1057 cirrus_bitblt_reset(s);
1058 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1059 ((reg_value & CIRRUS_BLT_START) != 0)) {
1060 cirrus_bitblt_start(s);
1061 }
1062 }
1063
1064
1065 /***************************************
1066 *
1067 * basic parameters
1068 *
1069 ***************************************/
1070
1071 static void cirrus_get_offsets(VGAState *s1,
1072 uint32_t *pline_offset,
1073 uint32_t *pstart_addr,
1074 uint32_t *pline_compare)
1075 {
1076 CirrusVGAState * s = (CirrusVGAState *)s1;
1077 uint32_t start_addr, line_offset, line_compare;
1078
1079 line_offset = s->cr[0x13]
1080 | ((s->cr[0x1b] & 0x10) << 4);
1081 line_offset <<= 3;
1082 *pline_offset = line_offset;
1083
1084 start_addr = (s->cr[0x0c] << 8)
1085 | s->cr[0x0d]
1086 | ((s->cr[0x1b] & 0x01) << 16)
1087 | ((s->cr[0x1b] & 0x0c) << 15)
1088 | ((s->cr[0x1d] & 0x80) << 12);
1089 *pstart_addr = start_addr;
1090
1091 line_compare = s->cr[0x18] |
1092 ((s->cr[0x07] & 0x10) << 4) |
1093 ((s->cr[0x09] & 0x40) << 3);
1094 *pline_compare = line_compare;
1095 }
1096
1097 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1098 {
1099 uint32_t ret = 16;
1100
1101 switch (s->cirrus_hidden_dac_data & 0xf) {
1102 case 0:
1103 ret = 15;
1104 break; /* Sierra HiColor */
1105 case 1:
1106 ret = 16;
1107 break; /* XGA HiColor */
1108 default:
1109 #ifdef DEBUG_CIRRUS
1110 printf("cirrus: invalid DAC value %x in 16bpp\n",
1111 (s->cirrus_hidden_dac_data & 0xf));
1112 #endif
1113 ret = 15; /* XXX */
1114 break;
1115 }
1116 return ret;
1117 }
1118
1119 static int cirrus_get_bpp(VGAState *s1)
1120 {
1121 CirrusVGAState * s = (CirrusVGAState *)s1;
1122 uint32_t ret = 8;
1123
1124 if ((s->sr[0x07] & 0x01) != 0) {
1125 /* Cirrus SVGA */
1126 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1127 case CIRRUS_SR7_BPP_8:
1128 ret = 8;
1129 break;
1130 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1131 ret = cirrus_get_bpp16_depth(s);
1132 break;
1133 case CIRRUS_SR7_BPP_24:
1134 ret = 24;
1135 break;
1136 case CIRRUS_SR7_BPP_16:
1137 ret = cirrus_get_bpp16_depth(s);
1138 break;
1139 case CIRRUS_SR7_BPP_32:
1140 ret = 32;
1141 break;
1142 default:
1143 #ifdef DEBUG_CIRRUS
1144 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1145 #endif
1146 ret = 8;
1147 break;
1148 }
1149 } else {
1150 /* VGA */
1151 ret = 0;
1152 }
1153
1154 return ret;
1155 }
1156
1157 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1158 {
1159 int width, height;
1160
1161 width = (s->cr[0x01] + 1) * 8;
1162 height = s->cr[0x12] |
1163 ((s->cr[0x07] & 0x02) << 7) |
1164 ((s->cr[0x07] & 0x40) << 3);
1165 height = (height + 1);
1166 /* interlace support */
1167 if (s->cr[0x1a] & 0x01)
1168 height = height * 2;
1169 *pwidth = width;
1170 *pheight = height;
1171 }
1172
1173 /***************************************
1174 *
1175 * bank memory
1176 *
1177 ***************************************/
1178
1179 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1180 {
1181 unsigned offset;
1182 unsigned limit;
1183
1184 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1185 offset = s->gr[0x09 + bank_index];
1186 else /* single bank */
1187 offset = s->gr[0x09];
1188
1189 if ((s->gr[0x0b] & 0x20) != 0)
1190 offset <<= 14;
1191 else
1192 offset <<= 12;
1193
1194 if (s->real_vram_size <= offset)
1195 limit = 0;
1196 else
1197 limit = s->real_vram_size - offset;
1198
1199 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1200 if (limit > 0x8000) {
1201 offset += 0x8000;
1202 limit -= 0x8000;
1203 } else {
1204 limit = 0;
1205 }
1206 }
1207
1208 if (limit > 0) {
1209 s->cirrus_bank_base[bank_index] = offset;
1210 s->cirrus_bank_limit[bank_index] = limit;
1211 } else {
1212 s->cirrus_bank_base[bank_index] = 0;
1213 s->cirrus_bank_limit[bank_index] = 0;
1214 }
1215 }
1216
1217 /***************************************
1218 *
1219 * I/O access between 0x3c4-0x3c5
1220 *
1221 ***************************************/
1222
1223 static int
1224 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1225 {
1226 switch (reg_index) {
1227 case 0x00: // Standard VGA
1228 case 0x01: // Standard VGA
1229 case 0x02: // Standard VGA
1230 case 0x03: // Standard VGA
1231 case 0x04: // Standard VGA
1232 return CIRRUS_HOOK_NOT_HANDLED;
1233 case 0x06: // Unlock Cirrus extensions
1234 *reg_value = s->sr[reg_index];
1235 break;
1236 case 0x10:
1237 case 0x30:
1238 case 0x50:
1239 case 0x70: // Graphics Cursor X
1240 case 0x90:
1241 case 0xb0:
1242 case 0xd0:
1243 case 0xf0: // Graphics Cursor X
1244 *reg_value = s->sr[0x10];
1245 break;
1246 case 0x11:
1247 case 0x31:
1248 case 0x51:
1249 case 0x71: // Graphics Cursor Y
1250 case 0x91:
1251 case 0xb1:
1252 case 0xd1:
1253 case 0xf1: // Graphics Cursor Y
1254 *reg_value = s->sr[0x11];
1255 break;
1256 case 0x05: // ???
1257 case 0x07: // Extended Sequencer Mode
1258 case 0x08: // EEPROM Control
1259 case 0x09: // Scratch Register 0
1260 case 0x0a: // Scratch Register 1
1261 case 0x0b: // VCLK 0
1262 case 0x0c: // VCLK 1
1263 case 0x0d: // VCLK 2
1264 case 0x0e: // VCLK 3
1265 case 0x0f: // DRAM Control
1266 case 0x12: // Graphics Cursor Attribute
1267 case 0x13: // Graphics Cursor Pattern Address
1268 case 0x14: // Scratch Register 2
1269 case 0x15: // Scratch Register 3
1270 case 0x16: // Performance Tuning Register
1271 case 0x17: // Configuration Readback and Extended Control
1272 case 0x18: // Signature Generator Control
1273 case 0x19: // Signal Generator Result
1274 case 0x1a: // Signal Generator Result
1275 case 0x1b: // VCLK 0 Denominator & Post
1276 case 0x1c: // VCLK 1 Denominator & Post
1277 case 0x1d: // VCLK 2 Denominator & Post
1278 case 0x1e: // VCLK 3 Denominator & Post
1279 case 0x1f: // BIOS Write Enable and MCLK select
1280 #ifdef DEBUG_CIRRUS
1281 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1282 #endif
1283 *reg_value = s->sr[reg_index];
1284 break;
1285 default:
1286 #ifdef DEBUG_CIRRUS
1287 printf("cirrus: inport sr_index %02x\n", reg_index);
1288 #endif
1289 *reg_value = 0xff;
1290 break;
1291 }
1292
1293 return CIRRUS_HOOK_HANDLED;
1294 }
1295
1296 static int
1297 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1298 {
1299 switch (reg_index) {
1300 case 0x00: // Standard VGA
1301 case 0x01: // Standard VGA
1302 case 0x02: // Standard VGA
1303 case 0x03: // Standard VGA
1304 case 0x04: // Standard VGA
1305 return CIRRUS_HOOK_NOT_HANDLED;
1306 case 0x06: // Unlock Cirrus extensions
1307 reg_value &= 0x17;
1308 if (reg_value == 0x12) {
1309 s->sr[reg_index] = 0x12;
1310 } else {
1311 s->sr[reg_index] = 0x0f;
1312 }
1313 break;
1314 case 0x10:
1315 case 0x30:
1316 case 0x50:
1317 case 0x70: // Graphics Cursor X
1318 case 0x90:
1319 case 0xb0:
1320 case 0xd0:
1321 case 0xf0: // Graphics Cursor X
1322 s->sr[0x10] = reg_value;
1323 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1324 break;
1325 case 0x11:
1326 case 0x31:
1327 case 0x51:
1328 case 0x71: // Graphics Cursor Y
1329 case 0x91:
1330 case 0xb1:
1331 case 0xd1:
1332 case 0xf1: // Graphics Cursor Y
1333 s->sr[0x11] = reg_value;
1334 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1335 break;
1336 case 0x07: // Extended Sequencer Mode
1337 case 0x08: // EEPROM Control
1338 case 0x09: // Scratch Register 0
1339 case 0x0a: // Scratch Register 1
1340 case 0x0b: // VCLK 0
1341 case 0x0c: // VCLK 1
1342 case 0x0d: // VCLK 2
1343 case 0x0e: // VCLK 3
1344 case 0x0f: // DRAM Control
1345 case 0x12: // Graphics Cursor Attribute
1346 case 0x13: // Graphics Cursor Pattern Address
1347 case 0x14: // Scratch Register 2
1348 case 0x15: // Scratch Register 3
1349 case 0x16: // Performance Tuning Register
1350 case 0x18: // Signature Generator Control
1351 case 0x19: // Signature Generator Result
1352 case 0x1a: // Signature Generator Result
1353 case 0x1b: // VCLK 0 Denominator & Post
1354 case 0x1c: // VCLK 1 Denominator & Post
1355 case 0x1d: // VCLK 2 Denominator & Post
1356 case 0x1e: // VCLK 3 Denominator & Post
1357 case 0x1f: // BIOS Write Enable and MCLK select
1358 s->sr[reg_index] = reg_value;
1359 #ifdef DEBUG_CIRRUS
1360 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1361 reg_index, reg_value);
1362 #endif
1363 if (reg_index == 0x07)
1364 cirrus_update_memory_access(s);
1365 break;
1366 case 0x17: // Configuration Readback and Extended Control
1367 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1368 cirrus_update_memory_access(s);
1369 break;
1370 default:
1371 #ifdef DEBUG_CIRRUS
1372 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1373 reg_value);
1374 #endif
1375 break;
1376 }
1377
1378 return CIRRUS_HOOK_HANDLED;
1379 }
1380
1381 /***************************************
1382 *
1383 * I/O access at 0x3c6
1384 *
1385 ***************************************/
1386
1387 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1388 {
1389 *reg_value = 0xff;
1390 if (++s->cirrus_hidden_dac_lockindex == 5) {
1391 *reg_value = s->cirrus_hidden_dac_data;
1392 s->cirrus_hidden_dac_lockindex = 0;
1393 }
1394 }
1395
1396 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1397 {
1398 if (s->cirrus_hidden_dac_lockindex == 4) {
1399 s->cirrus_hidden_dac_data = reg_value;
1400 #if defined(DEBUG_CIRRUS)
1401 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1402 #endif
1403 }
1404 s->cirrus_hidden_dac_lockindex = 0;
1405 }
1406
1407 /***************************************
1408 *
1409 * I/O access at 0x3c9
1410 *
1411 ***************************************/
1412
1413 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1414 {
1415 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1416 return CIRRUS_HOOK_NOT_HANDLED;
1417 *reg_value =
1418 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1419 s->dac_sub_index];
1420 if (++s->dac_sub_index == 3) {
1421 s->dac_sub_index = 0;
1422 s->dac_read_index++;
1423 }
1424 return CIRRUS_HOOK_HANDLED;
1425 }
1426
1427 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1428 {
1429 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1430 return CIRRUS_HOOK_NOT_HANDLED;
1431 s->dac_cache[s->dac_sub_index] = reg_value;
1432 if (++s->dac_sub_index == 3) {
1433 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1434 s->dac_cache, 3);
1435 /* XXX update cursor */
1436 s->dac_sub_index = 0;
1437 s->dac_write_index++;
1438 }
1439 return CIRRUS_HOOK_HANDLED;
1440 }
1441
1442 /***************************************
1443 *
1444 * I/O access between 0x3ce-0x3cf
1445 *
1446 ***************************************/
1447
1448 static int
1449 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1450 {
1451 switch (reg_index) {
1452 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1453 *reg_value = s->cirrus_shadow_gr0;
1454 return CIRRUS_HOOK_HANDLED;
1455 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1456 *reg_value = s->cirrus_shadow_gr1;
1457 return CIRRUS_HOOK_HANDLED;
1458 case 0x02: // Standard VGA
1459 case 0x03: // Standard VGA
1460 case 0x04: // Standard VGA
1461 case 0x06: // Standard VGA
1462 case 0x07: // Standard VGA
1463 case 0x08: // Standard VGA
1464 return CIRRUS_HOOK_NOT_HANDLED;
1465 case 0x05: // Standard VGA, Cirrus extended mode
1466 default:
1467 break;
1468 }
1469
1470 if (reg_index < 0x3a) {
1471 *reg_value = s->gr[reg_index];
1472 } else {
1473 #ifdef DEBUG_CIRRUS
1474 printf("cirrus: inport gr_index %02x\n", reg_index);
1475 #endif
1476 *reg_value = 0xff;
1477 }
1478
1479 return CIRRUS_HOOK_HANDLED;
1480 }
1481
1482 static int
1483 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1484 {
1485 #if defined(DEBUG_BITBLT) && 0
1486 printf("gr%02x: %02x\n", reg_index, reg_value);
1487 #endif
1488 switch (reg_index) {
1489 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1490 s->cirrus_shadow_gr0 = reg_value;
1491 return CIRRUS_HOOK_NOT_HANDLED;
1492 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1493 s->cirrus_shadow_gr1 = reg_value;
1494 return CIRRUS_HOOK_NOT_HANDLED;
1495 case 0x02: // Standard VGA
1496 case 0x03: // Standard VGA
1497 case 0x04: // Standard VGA
1498 case 0x06: // Standard VGA
1499 case 0x07: // Standard VGA
1500 case 0x08: // Standard VGA
1501 return CIRRUS_HOOK_NOT_HANDLED;
1502 case 0x05: // Standard VGA, Cirrus extended mode
1503 s->gr[reg_index] = reg_value & 0x7f;
1504 cirrus_update_memory_access(s);
1505 break;
1506 case 0x09: // bank offset #0
1507 case 0x0A: // bank offset #1
1508 s->gr[reg_index] = reg_value;
1509 cirrus_update_bank_ptr(s, 0);
1510 cirrus_update_bank_ptr(s, 1);
1511 cirrus_update_memory_access(s);
1512 break;
1513 case 0x0B:
1514 s->gr[reg_index] = reg_value;
1515 cirrus_update_bank_ptr(s, 0);
1516 cirrus_update_bank_ptr(s, 1);
1517 cirrus_update_memory_access(s);
1518 break;
1519 case 0x10: // BGCOLOR 0x0000ff00
1520 case 0x11: // FGCOLOR 0x0000ff00
1521 case 0x12: // BGCOLOR 0x00ff0000
1522 case 0x13: // FGCOLOR 0x00ff0000
1523 case 0x14: // BGCOLOR 0xff000000
1524 case 0x15: // FGCOLOR 0xff000000
1525 case 0x20: // BLT WIDTH 0x0000ff
1526 case 0x22: // BLT HEIGHT 0x0000ff
1527 case 0x24: // BLT DEST PITCH 0x0000ff
1528 case 0x26: // BLT SRC PITCH 0x0000ff
1529 case 0x28: // BLT DEST ADDR 0x0000ff
1530 case 0x29: // BLT DEST ADDR 0x00ff00
1531 case 0x2c: // BLT SRC ADDR 0x0000ff
1532 case 0x2d: // BLT SRC ADDR 0x00ff00
1533 case 0x2f: // BLT WRITEMASK
1534 case 0x30: // BLT MODE
1535 case 0x32: // RASTER OP
1536 case 0x33: // BLT MODEEXT
1537 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1538 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1539 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1540 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1541 s->gr[reg_index] = reg_value;
1542 break;
1543 case 0x21: // BLT WIDTH 0x001f00
1544 case 0x23: // BLT HEIGHT 0x001f00
1545 case 0x25: // BLT DEST PITCH 0x001f00
1546 case 0x27: // BLT SRC PITCH 0x001f00
1547 s->gr[reg_index] = reg_value & 0x1f;
1548 break;
1549 case 0x2a: // BLT DEST ADDR 0x3f0000
1550 s->gr[reg_index] = reg_value & 0x3f;
1551 /* if auto start mode, starts bit blt now */
1552 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1553 cirrus_bitblt_start(s);
1554 }
1555 break;
1556 case 0x2e: // BLT SRC ADDR 0x3f0000
1557 s->gr[reg_index] = reg_value & 0x3f;
1558 break;
1559 case 0x31: // BLT STATUS/START
1560 cirrus_write_bitblt(s, reg_value);
1561 break;
1562 default:
1563 #ifdef DEBUG_CIRRUS
1564 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1565 reg_value);
1566 #endif
1567 break;
1568 }
1569
1570 return CIRRUS_HOOK_HANDLED;
1571 }
1572
1573 /***************************************
1574 *
1575 * I/O access between 0x3d4-0x3d5
1576 *
1577 ***************************************/
1578
1579 static int
1580 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1581 {
1582 switch (reg_index) {
1583 case 0x00: // Standard VGA
1584 case 0x01: // Standard VGA
1585 case 0x02: // Standard VGA
1586 case 0x03: // Standard VGA
1587 case 0x04: // Standard VGA
1588 case 0x05: // Standard VGA
1589 case 0x06: // Standard VGA
1590 case 0x07: // Standard VGA
1591 case 0x08: // Standard VGA
1592 case 0x09: // Standard VGA
1593 case 0x0a: // Standard VGA
1594 case 0x0b: // Standard VGA
1595 case 0x0c: // Standard VGA
1596 case 0x0d: // Standard VGA
1597 case 0x0e: // Standard VGA
1598 case 0x0f: // Standard VGA
1599 case 0x10: // Standard VGA
1600 case 0x11: // Standard VGA
1601 case 0x12: // Standard VGA
1602 case 0x13: // Standard VGA
1603 case 0x14: // Standard VGA
1604 case 0x15: // Standard VGA
1605 case 0x16: // Standard VGA
1606 case 0x17: // Standard VGA
1607 case 0x18: // Standard VGA
1608 return CIRRUS_HOOK_NOT_HANDLED;
1609 case 0x19: // Interlace End
1610 case 0x1a: // Miscellaneous Control
1611 case 0x1b: // Extended Display Control
1612 case 0x1c: // Sync Adjust and Genlock
1613 case 0x1d: // Overlay Extended Control
1614 case 0x22: // Graphics Data Latches Readback (R)
1615 case 0x24: // Attribute Controller Toggle Readback (R)
1616 case 0x25: // Part Status
1617 case 0x27: // Part ID (R)
1618 *reg_value = s->cr[reg_index];
1619 break;
1620 case 0x26: // Attribute Controller Index Readback (R)
1621 *reg_value = s->ar_index & 0x3f;
1622 break;
1623 default:
1624 #ifdef DEBUG_CIRRUS
1625 printf("cirrus: inport cr_index %02x\n", reg_index);
1626 *reg_value = 0xff;
1627 #endif
1628 break;
1629 }
1630
1631 return CIRRUS_HOOK_HANDLED;
1632 }
1633
1634 static int
1635 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1636 {
1637 switch (reg_index) {
1638 case 0x00: // Standard VGA
1639 case 0x01: // Standard VGA
1640 case 0x02: // Standard VGA
1641 case 0x03: // Standard VGA
1642 case 0x04: // Standard VGA
1643 case 0x05: // Standard VGA
1644 case 0x06: // Standard VGA
1645 case 0x07: // Standard VGA
1646 case 0x08: // Standard VGA
1647 case 0x09: // Standard VGA
1648 case 0x0a: // Standard VGA
1649 case 0x0b: // Standard VGA
1650 case 0x0c: // Standard VGA
1651 case 0x0d: // Standard VGA
1652 case 0x0e: // Standard VGA
1653 case 0x0f: // Standard VGA
1654 case 0x10: // Standard VGA
1655 case 0x11: // Standard VGA
1656 case 0x12: // Standard VGA
1657 case 0x13: // Standard VGA
1658 case 0x14: // Standard VGA
1659 case 0x15: // Standard VGA
1660 case 0x16: // Standard VGA
1661 case 0x17: // Standard VGA
1662 case 0x18: // Standard VGA
1663 return CIRRUS_HOOK_NOT_HANDLED;
1664 case 0x19: // Interlace End
1665 case 0x1a: // Miscellaneous Control
1666 case 0x1b: // Extended Display Control
1667 case 0x1c: // Sync Adjust and Genlock
1668 case 0x1d: // Overlay Extended Control
1669 s->cr[reg_index] = reg_value;
1670 #ifdef DEBUG_CIRRUS
1671 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1672 reg_index, reg_value);
1673 #endif
1674 break;
1675 case 0x22: // Graphics Data Latches Readback (R)
1676 case 0x24: // Attribute Controller Toggle Readback (R)
1677 case 0x26: // Attribute Controller Index Readback (R)
1678 case 0x27: // Part ID (R)
1679 break;
1680 case 0x25: // Part Status
1681 default:
1682 #ifdef DEBUG_CIRRUS
1683 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1684 reg_value);
1685 #endif
1686 break;
1687 }
1688
1689 return CIRRUS_HOOK_HANDLED;
1690 }
1691
1692 /***************************************
1693 *
1694 * memory-mapped I/O (bitblt)
1695 *
1696 ***************************************/
1697
1698 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1699 {
1700 int value = 0xff;
1701
1702 switch (address) {
1703 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1704 cirrus_hook_read_gr(s, 0x00, &value);
1705 break;
1706 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1707 cirrus_hook_read_gr(s, 0x10, &value);
1708 break;
1709 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1710 cirrus_hook_read_gr(s, 0x12, &value);
1711 break;
1712 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1713 cirrus_hook_read_gr(s, 0x14, &value);
1714 break;
1715 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1716 cirrus_hook_read_gr(s, 0x01, &value);
1717 break;
1718 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1719 cirrus_hook_read_gr(s, 0x11, &value);
1720 break;
1721 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1722 cirrus_hook_read_gr(s, 0x13, &value);
1723 break;
1724 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1725 cirrus_hook_read_gr(s, 0x15, &value);
1726 break;
1727 case (CIRRUS_MMIO_BLTWIDTH + 0):
1728 cirrus_hook_read_gr(s, 0x20, &value);
1729 break;
1730 case (CIRRUS_MMIO_BLTWIDTH + 1):
1731 cirrus_hook_read_gr(s, 0x21, &value);
1732 break;
1733 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1734 cirrus_hook_read_gr(s, 0x22, &value);
1735 break;
1736 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1737 cirrus_hook_read_gr(s, 0x23, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1740 cirrus_hook_read_gr(s, 0x24, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1743 cirrus_hook_read_gr(s, 0x25, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1746 cirrus_hook_read_gr(s, 0x26, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1749 cirrus_hook_read_gr(s, 0x27, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1752 cirrus_hook_read_gr(s, 0x28, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1755 cirrus_hook_read_gr(s, 0x29, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1758 cirrus_hook_read_gr(s, 0x2a, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1761 cirrus_hook_read_gr(s, 0x2c, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1764 cirrus_hook_read_gr(s, 0x2d, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1767 cirrus_hook_read_gr(s, 0x2e, &value);
1768 break;
1769 case CIRRUS_MMIO_BLTWRITEMASK:
1770 cirrus_hook_read_gr(s, 0x2f, &value);
1771 break;
1772 case CIRRUS_MMIO_BLTMODE:
1773 cirrus_hook_read_gr(s, 0x30, &value);
1774 break;
1775 case CIRRUS_MMIO_BLTROP:
1776 cirrus_hook_read_gr(s, 0x32, &value);
1777 break;
1778 case CIRRUS_MMIO_BLTMODEEXT:
1779 cirrus_hook_read_gr(s, 0x33, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1782 cirrus_hook_read_gr(s, 0x34, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1785 cirrus_hook_read_gr(s, 0x35, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1788 cirrus_hook_read_gr(s, 0x38, &value);
1789 break;
1790 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1791 cirrus_hook_read_gr(s, 0x39, &value);
1792 break;
1793 case CIRRUS_MMIO_BLTSTATUS:
1794 cirrus_hook_read_gr(s, 0x31, &value);
1795 break;
1796 default:
1797 #ifdef DEBUG_CIRRUS
1798 printf("cirrus: mmio read - address 0x%04x\n", address);
1799 #endif
1800 break;
1801 }
1802
1803 return (uint8_t) value;
1804 }
1805
1806 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1807 uint8_t value)
1808 {
1809 switch (address) {
1810 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1811 cirrus_hook_write_gr(s, 0x00, value);
1812 break;
1813 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1814 cirrus_hook_write_gr(s, 0x10, value);
1815 break;
1816 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1817 cirrus_hook_write_gr(s, 0x12, value);
1818 break;
1819 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1820 cirrus_hook_write_gr(s, 0x14, value);
1821 break;
1822 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1823 cirrus_hook_write_gr(s, 0x01, value);
1824 break;
1825 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1826 cirrus_hook_write_gr(s, 0x11, value);
1827 break;
1828 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1829 cirrus_hook_write_gr(s, 0x13, value);
1830 break;
1831 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1832 cirrus_hook_write_gr(s, 0x15, value);
1833 break;
1834 case (CIRRUS_MMIO_BLTWIDTH + 0):
1835 cirrus_hook_write_gr(s, 0x20, value);
1836 break;
1837 case (CIRRUS_MMIO_BLTWIDTH + 1):
1838 cirrus_hook_write_gr(s, 0x21, value);
1839 break;
1840 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1841 cirrus_hook_write_gr(s, 0x22, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1844 cirrus_hook_write_gr(s, 0x23, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1847 cirrus_hook_write_gr(s, 0x24, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1850 cirrus_hook_write_gr(s, 0x25, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1853 cirrus_hook_write_gr(s, 0x26, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1856 cirrus_hook_write_gr(s, 0x27, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1859 cirrus_hook_write_gr(s, 0x28, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1862 cirrus_hook_write_gr(s, 0x29, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1865 cirrus_hook_write_gr(s, 0x2a, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1868 /* ignored */
1869 break;
1870 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1871 cirrus_hook_write_gr(s, 0x2c, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1874 cirrus_hook_write_gr(s, 0x2d, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1877 cirrus_hook_write_gr(s, 0x2e, value);
1878 break;
1879 case CIRRUS_MMIO_BLTWRITEMASK:
1880 cirrus_hook_write_gr(s, 0x2f, value);
1881 break;
1882 case CIRRUS_MMIO_BLTMODE:
1883 cirrus_hook_write_gr(s, 0x30, value);
1884 break;
1885 case CIRRUS_MMIO_BLTROP:
1886 cirrus_hook_write_gr(s, 0x32, value);
1887 break;
1888 case CIRRUS_MMIO_BLTMODEEXT:
1889 cirrus_hook_write_gr(s, 0x33, value);
1890 break;
1891 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1892 cirrus_hook_write_gr(s, 0x34, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1895 cirrus_hook_write_gr(s, 0x35, value);
1896 break;
1897 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1898 cirrus_hook_write_gr(s, 0x38, value);
1899 break;
1900 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1901 cirrus_hook_write_gr(s, 0x39, value);
1902 break;
1903 case CIRRUS_MMIO_BLTSTATUS:
1904 cirrus_hook_write_gr(s, 0x31, value);
1905 break;
1906 default:
1907 #ifdef DEBUG_CIRRUS
1908 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1909 address, value);
1910 #endif
1911 break;
1912 }
1913 }
1914
1915 /***************************************
1916 *
1917 * write mode 4/5
1918 *
1919 * assume TARGET_PAGE_SIZE >= 16
1920 *
1921 ***************************************/
1922
1923 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1924 unsigned mode,
1925 unsigned offset,
1926 uint32_t mem_value)
1927 {
1928 int x;
1929 unsigned val = mem_value;
1930 uint8_t *dst;
1931
1932 dst = s->vram_ptr + offset;
1933 for (x = 0; x < 8; x++) {
1934 if (val & 0x80) {
1935 *dst = s->cirrus_shadow_gr1;
1936 } else if (mode == 5) {
1937 *dst = s->cirrus_shadow_gr0;
1938 }
1939 val <<= 1;
1940 dst++;
1941 }
1942 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1943 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1944 }
1945
1946 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1947 unsigned mode,
1948 unsigned offset,
1949 uint32_t mem_value)
1950 {
1951 int x;
1952 unsigned val = mem_value;
1953 uint8_t *dst;
1954
1955 dst = s->vram_ptr + offset;
1956 for (x = 0; x < 8; x++) {
1957 if (val & 0x80) {
1958 *dst = s->cirrus_shadow_gr1;
1959 *(dst + 1) = s->gr[0x11];
1960 } else if (mode == 5) {
1961 *dst = s->cirrus_shadow_gr0;
1962 *(dst + 1) = s->gr[0x10];
1963 }
1964 val <<= 1;
1965 dst += 2;
1966 }
1967 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1968 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1969 }
1970
1971 /***************************************
1972 *
1973 * memory access between 0xa0000-0xbffff
1974 *
1975 ***************************************/
1976
1977 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1978 {
1979 CirrusVGAState *s = opaque;
1980 unsigned bank_index;
1981 unsigned bank_offset;
1982 uint32_t val;
1983
1984 if ((s->sr[0x07] & 0x01) == 0) {
1985 return vga_mem_readb(s, addr);
1986 }
1987
1988 addr &= 0x1ffff;
1989
1990 if (addr < 0x10000) {
1991 /* XXX handle bitblt */
1992 /* video memory */
1993 bank_index = addr >> 15;
1994 bank_offset = addr & 0x7fff;
1995 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1996 bank_offset += s->cirrus_bank_base[bank_index];
1997 if ((s->gr[0x0B] & 0x14) == 0x14) {
1998 bank_offset <<= 4;
1999 } else if (s->gr[0x0B] & 0x02) {
2000 bank_offset <<= 3;
2001 }
2002 bank_offset &= s->cirrus_addr_mask;
2003 val = *(s->vram_ptr + bank_offset);
2004 } else
2005 val = 0xff;
2006 } else if (addr >= 0x18000 && addr < 0x18100) {
2007 /* memory-mapped I/O */
2008 val = 0xff;
2009 if ((s->sr[0x17] & 0x44) == 0x04) {
2010 val = cirrus_mmio_blt_read(s, addr & 0xff);
2011 }
2012 } else {
2013 val = 0xff;
2014 #ifdef DEBUG_CIRRUS
2015 printf("cirrus: mem_readb %06x\n", addr);
2016 #endif
2017 }
2018 return val;
2019 }
2020
2021 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2022 {
2023 uint32_t v;
2024 #ifdef TARGET_WORDS_BIGENDIAN
2025 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2026 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2027 #else
2028 v = cirrus_vga_mem_readb(opaque, addr);
2029 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2030 #endif
2031 return v;
2032 }
2033
2034 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2035 {
2036 uint32_t v;
2037 #ifdef TARGET_WORDS_BIGENDIAN
2038 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2039 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2040 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2041 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2042 #else
2043 v = cirrus_vga_mem_readb(opaque, addr);
2044 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2045 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2046 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2047 #endif
2048 return v;
2049 }
2050
2051 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2052 uint32_t mem_value)
2053 {
2054 CirrusVGAState *s = opaque;
2055 unsigned bank_index;
2056 unsigned bank_offset;
2057 unsigned mode;
2058
2059 if ((s->sr[0x07] & 0x01) == 0) {
2060 vga_mem_writeb(s, addr, mem_value);
2061 return;
2062 }
2063
2064 addr &= 0x1ffff;
2065
2066 if (addr < 0x10000) {
2067 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2068 /* bitblt */
2069 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2070 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2071 cirrus_bitblt_cputovideo_next(s);
2072 }
2073 } else {
2074 /* video memory */
2075 bank_index = addr >> 15;
2076 bank_offset = addr & 0x7fff;
2077 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2078 bank_offset += s->cirrus_bank_base[bank_index];
2079 if ((s->gr[0x0B] & 0x14) == 0x14) {
2080 bank_offset <<= 4;
2081 } else if (s->gr[0x0B] & 0x02) {
2082 bank_offset <<= 3;
2083 }
2084 bank_offset &= s->cirrus_addr_mask;
2085 mode = s->gr[0x05] & 0x7;
2086 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2087 *(s->vram_ptr + bank_offset) = mem_value;
2088 cpu_physical_memory_set_dirty(s->vram_offset +
2089 bank_offset);
2090 } else {
2091 if ((s->gr[0x0B] & 0x14) != 0x14) {
2092 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2093 bank_offset,
2094 mem_value);
2095 } else {
2096 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2097 bank_offset,
2098 mem_value);
2099 }
2100 }
2101 }
2102 }
2103 } else if (addr >= 0x18000 && addr < 0x18100) {
2104 /* memory-mapped I/O */
2105 if ((s->sr[0x17] & 0x44) == 0x04) {
2106 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2107 }
2108 } else {
2109 #ifdef DEBUG_CIRRUS
2110 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2111 #endif
2112 }
2113 }
2114
2115 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2116 {
2117 #ifdef TARGET_WORDS_BIGENDIAN
2118 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2119 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2120 #else
2121 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2122 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2123 #endif
2124 }
2125
2126 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2127 {
2128 #ifdef TARGET_WORDS_BIGENDIAN
2129 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2130 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2131 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2132 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2133 #else
2134 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2135 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2136 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2137 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2138 #endif
2139 }
2140
2141 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2142 cirrus_vga_mem_readb,
2143 cirrus_vga_mem_readw,
2144 cirrus_vga_mem_readl,
2145 };
2146
2147 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2148 cirrus_vga_mem_writeb,
2149 cirrus_vga_mem_writew,
2150 cirrus_vga_mem_writel,
2151 };
2152
2153 /***************************************
2154 *
2155 * hardware cursor
2156 *
2157 ***************************************/
2158
2159 static inline void invalidate_cursor1(CirrusVGAState *s)
2160 {
2161 if (s->last_hw_cursor_size) {
2162 vga_invalidate_scanlines((VGAState *)s,
2163 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2164 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2165 }
2166 }
2167
2168 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2169 {
2170 const uint8_t *src;
2171 uint32_t content;
2172 int y, y_min, y_max;
2173
2174 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2175 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2176 src += (s->sr[0x13] & 0x3c) * 256;
2177 y_min = 64;
2178 y_max = -1;
2179 for(y = 0; y < 64; y++) {
2180 content = ((uint32_t *)src)[0] |
2181 ((uint32_t *)src)[1] |
2182 ((uint32_t *)src)[2] |
2183 ((uint32_t *)src)[3];
2184 if (content) {
2185 if (y < y_min)
2186 y_min = y;
2187 if (y > y_max)
2188 y_max = y;
2189 }
2190 src += 16;
2191 }
2192 } else {
2193 src += (s->sr[0x13] & 0x3f) * 256;
2194 y_min = 32;
2195 y_max = -1;
2196 for(y = 0; y < 32; y++) {
2197 content = ((uint32_t *)src)[0] |
2198 ((uint32_t *)(src + 128))[0];
2199 if (content) {
2200 if (y < y_min)
2201 y_min = y;
2202 if (y > y_max)
2203 y_max = y;
2204 }
2205 src += 4;
2206 }
2207 }
2208 if (y_min > y_max) {
2209 s->last_hw_cursor_y_start = 0;
2210 s->last_hw_cursor_y_end = 0;
2211 } else {
2212 s->last_hw_cursor_y_start = y_min;
2213 s->last_hw_cursor_y_end = y_max + 1;
2214 }
2215 }
2216
2217 /* NOTE: we do not currently handle the cursor bitmap change, so we
2218 update the cursor only if it moves. */
2219 static void cirrus_cursor_invalidate(VGAState *s1)
2220 {
2221 CirrusVGAState *s = (CirrusVGAState *)s1;
2222 int size;
2223
2224 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2225 size = 0;
2226 } else {
2227 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2228 size = 64;
2229 else
2230 size = 32;
2231 }
2232 /* invalidate last cursor and new cursor if any change */
2233 if (s->last_hw_cursor_size != size ||
2234 s->last_hw_cursor_x != s->hw_cursor_x ||
2235 s->last_hw_cursor_y != s->hw_cursor_y) {
2236
2237 invalidate_cursor1(s);
2238
2239 s->last_hw_cursor_size = size;
2240 s->last_hw_cursor_x = s->hw_cursor_x;
2241 s->last_hw_cursor_y = s->hw_cursor_y;
2242 /* compute the real cursor min and max y */
2243 cirrus_cursor_compute_yrange(s);
2244 invalidate_cursor1(s);
2245 }
2246 }
2247
2248 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2249 {
2250 CirrusVGAState *s = (CirrusVGAState *)s1;
2251 int w, h, bpp, x1, x2, poffset;
2252 unsigned int color0, color1;
2253 const uint8_t *palette, *src;
2254 uint32_t content;
2255
2256 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2257 return;
2258 /* fast test to see if the cursor intersects with the scan line */
2259 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2260 h = 64;
2261 } else {
2262 h = 32;
2263 }
2264 if (scr_y < s->hw_cursor_y ||
2265 scr_y >= (s->hw_cursor_y + h))
2266 return;
2267
2268 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2269 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2270 src += (s->sr[0x13] & 0x3c) * 256;
2271 src += (scr_y - s->hw_cursor_y) * 16;
2272 poffset = 8;
2273 content = ((uint32_t *)src)[0] |
2274 ((uint32_t *)src)[1] |
2275 ((uint32_t *)src)[2] |
2276 ((uint32_t *)src)[3];
2277 } else {
2278 src += (s->sr[0x13] & 0x3f) * 256;
2279 src += (scr_y - s->hw_cursor_y) * 4;
2280 poffset = 128;
2281 content = ((uint32_t *)src)[0] |
2282 ((uint32_t *)(src + 128))[0];
2283 }
2284 /* if nothing to draw, no need to continue */
2285 if (!content)
2286 return;
2287 w = h;
2288
2289 x1 = s->hw_cursor_x;
2290 if (x1 >= s->last_scr_width)
2291 return;
2292 x2 = s->hw_cursor_x + w;
2293 if (x2 > s->last_scr_width)
2294 x2 = s->last_scr_width;
2295 w = x2 - x1;
2296 palette = s->cirrus_hidden_palette;
2297 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2298 c6_to_8(palette[0x0 * 3 + 1]),
2299 c6_to_8(palette[0x0 * 3 + 2]));
2300 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2301 c6_to_8(palette[0xf * 3 + 1]),
2302 c6_to_8(palette[0xf * 3 + 2]));
2303 bpp = ((s->ds->depth + 7) >> 3);
2304 d1 += x1 * bpp;
2305 switch(s->ds->depth) {
2306 default:
2307 break;
2308 case 8:
2309 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2310 break;
2311 case 15:
2312 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2313 break;
2314 case 16:
2315 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2316 break;
2317 case 32:
2318 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2319 break;
2320 }
2321 }
2322
2323 /***************************************
2324 *
2325 * LFB memory access
2326 *
2327 ***************************************/
2328
2329 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2330 {
2331 CirrusVGAState *s = (CirrusVGAState *) opaque;
2332 uint32_t ret;
2333
2334 addr &= s->cirrus_addr_mask;
2335
2336 if (((s->sr[0x17] & 0x44) == 0x44) &&
2337 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2338 /* memory-mapped I/O */
2339 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2340 } else if (0) {
2341 /* XXX handle bitblt */
2342 ret = 0xff;
2343 } else {
2344 /* video memory */
2345 if ((s->gr[0x0B] & 0x14) == 0x14) {
2346 addr <<= 4;
2347 } else if (s->gr[0x0B] & 0x02) {
2348 addr <<= 3;
2349 }
2350 addr &= s->cirrus_addr_mask;
2351 ret = *(s->vram_ptr + addr);
2352 }
2353
2354 return ret;
2355 }
2356
2357 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2358 {
2359 uint32_t v;
2360 #ifdef TARGET_WORDS_BIGENDIAN
2361 v = cirrus_linear_readb(opaque, addr) << 8;
2362 v |= cirrus_linear_readb(opaque, addr + 1);
2363 #else
2364 v = cirrus_linear_readb(opaque, addr);
2365 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2366 #endif
2367 return v;
2368 }
2369
2370 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2371 {
2372 uint32_t v;
2373 #ifdef TARGET_WORDS_BIGENDIAN
2374 v = cirrus_linear_readb(opaque, addr) << 24;
2375 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2376 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2377 v |= cirrus_linear_readb(opaque, addr + 3);
2378 #else
2379 v = cirrus_linear_readb(opaque, addr);
2380 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2381 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2382 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2383 #endif
2384 return v;
2385 }
2386
2387 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2388 uint32_t val)
2389 {
2390 CirrusVGAState *s = (CirrusVGAState *) opaque;
2391 unsigned mode;
2392
2393 addr &= s->cirrus_addr_mask;
2394
2395 if (((s->sr[0x17] & 0x44) == 0x44) &&
2396 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2397 /* memory-mapped I/O */
2398 cirrus_mmio_blt_write(s, addr & 0xff, val);
2399 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2400 /* bitblt */
2401 *s->cirrus_srcptr++ = (uint8_t) val;
2402 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2403 cirrus_bitblt_cputovideo_next(s);
2404 }
2405 } else {
2406 /* video memory */
2407 if ((s->gr[0x0B] & 0x14) == 0x14) {
2408 addr <<= 4;
2409 } else if (s->gr[0x0B] & 0x02) {
2410 addr <<= 3;
2411 }
2412 addr &= s->cirrus_addr_mask;
2413
2414 mode = s->gr[0x05] & 0x7;
2415 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2416 *(s->vram_ptr + addr) = (uint8_t) val;
2417 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2418 } else {
2419 if ((s->gr[0x0B] & 0x14) != 0x14) {
2420 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2421 } else {
2422 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2423 }
2424 }
2425 }
2426 }
2427
2428 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2429 uint32_t val)
2430 {
2431 #ifdef TARGET_WORDS_BIGENDIAN
2432 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2433 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2434 #else
2435 cirrus_linear_writeb(opaque, addr, val & 0xff);
2436 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2437 #endif
2438 }
2439
2440 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2441 uint32_t val)
2442 {
2443 #ifdef TARGET_WORDS_BIGENDIAN
2444 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2445 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2446 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2447 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2448 #else
2449 cirrus_linear_writeb(opaque, addr, val & 0xff);
2450 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2451 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2452 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2453 #endif
2454 }
2455
2456
2457 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2458 cirrus_linear_readb,
2459 cirrus_linear_readw,
2460 cirrus_linear_readl,
2461 };
2462
2463 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2464 cirrus_linear_writeb,
2465 cirrus_linear_writew,
2466 cirrus_linear_writel,
2467 };
2468
2469 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2470 uint32_t val)
2471 {
2472 CirrusVGAState *s = (CirrusVGAState *) opaque;
2473
2474 addr &= s->cirrus_addr_mask;
2475 *(s->vram_ptr + addr) = val;
2476 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2477 }
2478
2479 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2480 uint32_t val)
2481 {
2482 CirrusVGAState *s = (CirrusVGAState *) opaque;
2483
2484 addr &= s->cirrus_addr_mask;
2485 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2486 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2487 }
2488
2489 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2490 uint32_t val)
2491 {
2492 CirrusVGAState *s = (CirrusVGAState *) opaque;
2493
2494 addr &= s->cirrus_addr_mask;
2495 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2496 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2497 }
2498
2499 /***************************************
2500 *
2501 * system to screen memory access
2502 *
2503 ***************************************/
2504
2505
2506 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2507 {
2508 uint32_t ret;
2509
2510 /* XXX handle bitblt */
2511 ret = 0xff;
2512 return ret;
2513 }
2514
2515 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2516 {
2517 uint32_t v;
2518 #ifdef TARGET_WORDS_BIGENDIAN
2519 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2520 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2521 #else
2522 v = cirrus_linear_bitblt_readb(opaque, addr);
2523 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2524 #endif
2525 return v;
2526 }
2527
2528 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2529 {
2530 uint32_t v;
2531 #ifdef TARGET_WORDS_BIGENDIAN
2532 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2533 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2534 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2535 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2536 #else
2537 v = cirrus_linear_bitblt_readb(opaque, addr);
2538 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2539 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2540 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2541 #endif
2542 return v;
2543 }
2544
2545 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2546 uint32_t val)
2547 {
2548 CirrusVGAState *s = (CirrusVGAState *) opaque;
2549
2550 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2551 /* bitblt */
2552 *s->cirrus_srcptr++ = (uint8_t) val;
2553 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2554 cirrus_bitblt_cputovideo_next(s);
2555 }
2556 }
2557 }
2558
2559 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2560 uint32_t val)
2561 {
2562 #ifdef TARGET_WORDS_BIGENDIAN
2563 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2564 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2565 #else
2566 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2567 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2568 #endif
2569 }
2570
2571 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2572 uint32_t val)
2573 {
2574 #ifdef TARGET_WORDS_BIGENDIAN
2575 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2576 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2577 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2578 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2579 #else
2580 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2581 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2582 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2583 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2584 #endif
2585 }
2586
2587
2588 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2589 cirrus_linear_bitblt_readb,
2590 cirrus_linear_bitblt_readw,
2591 cirrus_linear_bitblt_readl,
2592 };
2593
2594 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2595 cirrus_linear_bitblt_writeb,
2596 cirrus_linear_bitblt_writew,
2597 cirrus_linear_bitblt_writel,
2598 };
2599
2600 void *set_vram_mapping(unsigned long begin, unsigned long end)
2601 {
2602 void *vram_pointer = NULL;
2603
2604 /* align begin and end address */
2605 begin = begin & TARGET_PAGE_MASK;
2606 end = begin + VGA_RAM_SIZE;
2607 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2608
2609 if (kvm_enabled())
2610 vram_pointer = kvm_cpu_create_phys_mem(begin, end - begin, 1, 1);
2611
2612 if (vram_pointer == NULL) {
2613 printf("set_vram_mapping: cannot allocate memory: %m\n");
2614 return NULL;
2615 }
2616
2617 memset(vram_pointer, 0, end - begin);
2618
2619 return vram_pointer;
2620 }
2621
2622 int unset_vram_mapping(unsigned long begin, unsigned long end)
2623 {
2624 /* align begin and end address */
2625 end = begin + VGA_RAM_SIZE;
2626 begin = begin & TARGET_PAGE_MASK;
2627 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2628
2629 if (kvm_enabled())
2630 kvm_cpu_destroy_phys_mem(begin, end - begin);
2631
2632 return 0;
2633 }
2634 #ifdef CONFIG_X86
2635 static void kvm_update_vga_alias(CirrusVGAState *s, int ok, int bank)
2636 {
2637 unsigned limit, base;
2638
2639 if (!ok && !s->aliases_enabled)
2640 return;
2641 limit = s->cirrus_bank_limit[bank];
2642 if (limit > 0x8000)
2643 limit = 0x8000;
2644 base = s->cirrus_lfb_addr + s->cirrus_bank_base[bank];
2645 if (ok) {
2646 if (!s->aliases_enabled
2647 || base != s->aliased_bank_base[bank]
2648 || limit != s->aliased_bank_limit[bank]) {
2649 kvm_create_memory_alias(kvm_context,
2650 0xa0000 + bank * 0x8000,
2651 limit, base);
2652 s->aliased_bank_base[bank] = base;
2653 s->aliased_bank_limit[bank] = limit;
2654 }
2655 } else {
2656 kvm_destroy_memory_alias(kvm_context, 0xa0000 + bank * 0x8000);
2657 }
2658 }
2659
2660 static void kvm_update_vga_aliases(CirrusVGAState *s, int ok)
2661 {
2662 if (kvm_enabled()) {
2663 kvm_update_vga_alias(s, ok, 0);
2664 kvm_update_vga_alias(s, ok, 1);
2665 }
2666 s->aliases_enabled = ok;
2667 }
2668 #endif
2669
2670 /* Compute the memory access functions */
2671 static void cirrus_update_memory_access(CirrusVGAState *s)
2672 {
2673 unsigned mode;
2674 #ifdef CONFIG_X86
2675 int want_vga_alias = 0;
2676 #endif
2677
2678 if ((s->sr[0x17] & 0x44) == 0x44) {
2679 goto generic_io;
2680 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2681 goto generic_io;
2682 } else {
2683 if ((s->gr[0x0B] & 0x14) == 0x14) {
2684 goto generic_io;
2685 } else if (s->gr[0x0B] & 0x02) {
2686 goto generic_io;
2687 }
2688
2689 mode = s->gr[0x05] & 0x7;
2690 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2691 if (kvm_enabled() && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2692 !s->map_addr) {
2693 void *vram_pointer, *old_vram;
2694
2695 vram_pointer = set_vram_mapping(s->cirrus_lfb_addr,
2696 s->cirrus_lfb_end);
2697 if (!vram_pointer)
2698 fprintf(stderr, "NULL vram_pointer\n");
2699 else {
2700 old_vram = vga_update_vram((VGAState *)s, vram_pointer,
2701 VGA_RAM_SIZE);
2702 qemu_free(old_vram);
2703 }
2704 s->map_addr = s->cirrus_lfb_addr;
2705 s->map_end = s->cirrus_lfb_end;
2706 }
2707 #ifdef CONFIG_X86
2708 if (kvm_enabled()
2709 && !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2710 && !((s->sr[0x07] & 0x01) == 0)
2711 && !((s->gr[0x0B] & 0x14) == 0x14)
2712 && !(s->gr[0x0B] & 0x02))
2713 want_vga_alias = 1;
2714 #endif
2715 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2716 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2717 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2718 } else {
2719 generic_io:
2720 if (kvm_enabled() && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2721 s->map_addr) {
2722 int error;
2723 void *old_vram = NULL;
2724
2725 error = unset_vram_mapping(s->cirrus_lfb_addr,
2726 s->cirrus_lfb_end);
2727 if (!error)
2728 old_vram = vga_update_vram((VGAState *)s, NULL,
2729 VGA_RAM_SIZE);
2730 if (old_vram)
2731 munmap(old_vram, s->map_end - s->map_addr);
2732 s->map_addr = s->map_end = 0;
2733 }
2734 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2735 s->cirrus_linear_write[1] = cirrus_linear_writew;
2736 s->cirrus_linear_write[2] = cirrus_linear_writel;
2737 }
2738 }
2739 #if defined(CONFIG_X86)
2740 kvm_update_vga_aliases(s, want_vga_alias);
2741 #endif
2742
2743 }
2744
2745
2746 /* I/O ports */
2747
2748 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2749 {
2750 CirrusVGAState *s = opaque;
2751 int val, index;
2752
2753 /* check port range access depending on color/monochrome mode */
2754 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2755 || (addr >= 0x3d0 && addr <= 0x3df
2756 && !(s->msr & MSR_COLOR_EMULATION))) {
2757 val = 0xff;
2758 } else {
2759 switch (addr) {
2760 case 0x3c0:
2761 if (s->ar_flip_flop == 0) {
2762 val = s->ar_index;
2763 } else {
2764 val = 0;
2765 }
2766 break;
2767 case 0x3c1:
2768 index = s->ar_index & 0x1f;
2769 if (index < 21)
2770 val = s->ar[index];
2771 else
2772 val = 0;
2773 break;
2774 case 0x3c2:
2775 val = s->st00;
2776 break;
2777 case 0x3c4:
2778 val = s->sr_index;
2779 break;
2780 case 0x3c5:
2781 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2782 break;
2783 val = s->sr[s->sr_index];
2784 #ifdef DEBUG_VGA_REG
2785 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2786 #endif
2787 break;
2788 case 0x3c6:
2789 cirrus_read_hidden_dac(s, &val);
2790 break;
2791 case 0x3c7:
2792 val = s->dac_state;
2793 break;
2794 case 0x3c8:
2795 val = s->dac_write_index;
2796 s->cirrus_hidden_dac_lockindex = 0;
2797 break;
2798 case 0x3c9:
2799 if (cirrus_hook_read_palette(s, &val))
2800 break;
2801 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2802 if (++s->dac_sub_index == 3) {
2803 s->dac_sub_index = 0;
2804 s->dac_read_index++;
2805 }
2806 break;
2807 case 0x3ca:
2808 val = s->fcr;
2809 break;
2810 case 0x3cc:
2811 val = s->msr;
2812 break;
2813 case 0x3ce:
2814 val = s->gr_index;
2815 break;
2816 case 0x3cf:
2817 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2818 break;
2819 val = s->gr[s->gr_index];
2820 #ifdef DEBUG_VGA_REG
2821 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2822 #endif
2823 break;
2824 case 0x3b4:
2825 case 0x3d4:
2826 val = s->cr_index;
2827 break;
2828 case 0x3b5:
2829 case 0x3d5:
2830 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2831 break;
2832 val = s->cr[s->cr_index];
2833 #ifdef DEBUG_VGA_REG
2834 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2835 #endif
2836 break;
2837 case 0x3ba:
2838 case 0x3da:
2839 /* just toggle to fool polling */
2840 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2841 val = s->st01;
2842 s->ar_flip_flop = 0;
2843 break;
2844 default:
2845 val = 0x00;
2846 break;
2847 }
2848 }
2849 #if defined(DEBUG_VGA)
2850 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2851 #endif
2852 return val;
2853 }
2854
2855 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2856 {
2857 CirrusVGAState *s = opaque;
2858 int index;
2859
2860 /* check port range access depending on color/monochrome mode */
2861 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2862 || (addr >= 0x3d0 && addr <= 0x3df
2863 && !(s->msr & MSR_COLOR_EMULATION)))
2864 return;
2865
2866 #ifdef DEBUG_VGA
2867 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2868 #endif
2869
2870 switch (addr) {
2871 case 0x3c0:
2872 if (s->ar_flip_flop == 0) {
2873 val &= 0x3f;
2874 s->ar_index = val;
2875 } else {
2876 index = s->ar_index & 0x1f;
2877 switch (index) {
2878 case 0x00 ... 0x0f:
2879 s->ar[index] = val & 0x3f;
2880 break;
2881 case 0x10:
2882 s->ar[index] = val & ~0x10;
2883 break;
2884 case 0x11:
2885 s->ar[index] = val;
2886 break;
2887 case 0x12:
2888 s->ar[index] = val & ~0xc0;
2889 break;
2890 case 0x13:
2891 s->ar[index] = val & ~0xf0;
2892 break;
2893 case 0x14:
2894 s->ar[index] = val & ~0xf0;
2895 break;
2896 default:
2897 break;
2898 }
2899 }
2900 s->ar_flip_flop ^= 1;
2901 break;
2902 case 0x3c2:
2903 s->msr = val & ~0x10;
2904 break;
2905 case 0x3c4:
2906 s->sr_index = val;
2907 break;
2908 case 0x3c5:
2909 if (cirrus_hook_write_sr(s, s->sr_index, val))
2910 break;
2911 #ifdef DEBUG_VGA_REG
2912 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2913 #endif
2914 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2915 break;
2916 case 0x3c6:
2917 cirrus_write_hidden_dac(s, val);
2918 break;
2919 case 0x3c7:
2920 s->dac_read_index = val;
2921 s->dac_sub_index = 0;
2922 s->dac_state = 3;
2923 break;
2924 case 0x3c8:
2925 s->dac_write_index = val;
2926 s->dac_sub_index = 0;
2927 s->dac_state = 0;
2928 break;
2929 case 0x3c9:
2930 if (cirrus_hook_write_palette(s, val))
2931 break;
2932 s->dac_cache[s->dac_sub_index] = val;
2933 if (++s->dac_sub_index == 3) {
2934 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2935 s->dac_sub_index = 0;
2936 s->dac_write_index++;
2937 }
2938 break;
2939 case 0x3ce:
2940 s->gr_index = val;
2941 break;
2942 case 0x3cf:
2943 if (cirrus_hook_write_gr(s, s->gr_index, val))
2944 break;
2945 #ifdef DEBUG_VGA_REG
2946 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2947 #endif
2948 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2949 break;
2950 case 0x3b4:
2951 case 0x3d4:
2952 s->cr_index = val;
2953 break;
2954 case 0x3b5:
2955 case 0x3d5:
2956 if (cirrus_hook_write_cr(s, s->cr_index, val))
2957 break;
2958 #ifdef DEBUG_VGA_REG
2959 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2960 #endif
2961 /* handle CR0-7 protection */
2962 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2963 /* can always write bit 4 of CR7 */
2964 if (s->cr_index == 7)
2965 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2966 return;
2967 }
2968 switch (s->cr_index) {
2969 case 0x01: /* horizontal display end */
2970 case 0x07:
2971 case 0x09:
2972 case 0x0c:
2973 case 0x0d:
2974 case 0x12: /* vertical display end */
2975 s->cr[s->cr_index] = val;
2976 break;
2977
2978 default:
2979 s->cr[s->cr_index] = val;
2980 break;
2981 }
2982 break;
2983 case 0x3ba:
2984 case 0x3da:
2985 s->fcr = val & 0x10;
2986 break;
2987 }
2988 }
2989
2990 /***************************************
2991 *
2992 * memory-mapped I/O access
2993 *
2994 ***************************************/
2995
2996 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2997 {
2998 CirrusVGAState *s = (CirrusVGAState *) opaque;
2999
3000 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3001
3002 if (addr >= 0x100) {
3003 return cirrus_mmio_blt_read(s, addr - 0x100);
3004 } else {
3005 return vga_ioport_read(s, addr + 0x3c0);
3006 }
3007 }
3008
3009 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
3010 {
3011 uint32_t v;
3012 #ifdef TARGET_WORDS_BIGENDIAN
3013 v = cirrus_mmio_readb(opaque, addr) << 8;
3014 v |= cirrus_mmio_readb(opaque, addr + 1);
3015 #else
3016 v = cirrus_mmio_readb(opaque, addr);
3017 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3018 #endif
3019 return v;
3020 }
3021
3022 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3023 {
3024 uint32_t v;
3025 #ifdef TARGET_WORDS_BIGENDIAN
3026 v = cirrus_mmio_readb(opaque, addr) << 24;
3027 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3028 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3029 v |= cirrus_mmio_readb(opaque, addr + 3);
3030 #else
3031 v = cirrus_mmio_readb(opaque, addr);
3032 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3033 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3034 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3035 #endif
3036 return v;
3037 }
3038
3039 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3040 uint32_t val)
3041 {
3042 CirrusVGAState *s = (CirrusVGAState *) opaque;
3043
3044 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3045
3046 if (addr >= 0x100) {
3047 cirrus_mmio_blt_write(s, addr - 0x100, val);
3048 } else {
3049 vga_ioport_write(s, addr + 0x3c0, val);
3050 }
3051 }
3052
3053 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3054 uint32_t val)
3055 {
3056 #ifdef TARGET_WORDS_BIGENDIAN
3057 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3058 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3059 #else
3060 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3061 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3062 #endif
3063 }
3064
3065 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3066 uint32_t val)
3067 {
3068 #ifdef TARGET_WORDS_BIGENDIAN
3069 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3070 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3071 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3072 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3073 #else
3074 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3075 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3076 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3077 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3078 #endif
3079 }
3080
3081
3082 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3083 cirrus_mmio_readb,
3084 cirrus_mmio_readw,
3085 cirrus_mmio_readl,
3086 };
3087
3088 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3089 cirrus_mmio_writeb,
3090 cirrus_mmio_writew,
3091 cirrus_mmio_writel,
3092 };
3093
3094 /* load/save state */
3095
3096 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3097 {
3098 CirrusVGAState *s = opaque;
3099
3100 if (s->pci_dev)
3101 pci_device_save(s->pci_dev, f);
3102
3103 qemu_put_be32s(f, &s->latch);
3104 qemu_put_8s(f, &s->sr_index);
3105 qemu_put_buffer(f, s->sr, 256);
3106 qemu_put_8s(f, &s->gr_index);
3107 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3108 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3109 qemu_put_buffer(f, s->gr + 2, 254);
3110 qemu_put_8s(f, &s->ar_index);
3111 qemu_put_buffer(f, s->ar, 21);
3112 qemu_put_be32(f, s->ar_flip_flop);
3113 qemu_put_8s(f, &s->cr_index);
3114 qemu_put_buffer(f, s->cr, 256);
3115 qemu_put_8s(f, &s->msr);
3116 qemu_put_8s(f, &s->fcr);
3117 qemu_put_8s(f, &s->st00);
3118 qemu_put_8s(f, &s->st01);
3119
3120 qemu_put_8s(f, &s->dac_state);
3121 qemu_put_8s(f, &s->dac_sub_index);
3122 qemu_put_8s(f, &s->dac_read_index);
3123 qemu_put_8s(f, &s->dac_write_index);
3124 qemu_put_buffer(f, s->dac_cache, 3);
3125 qemu_put_buffer(f, s->palette, 768);
3126
3127 qemu_put_be32(f, s->bank_offset);
3128
3129 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3130 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3131
3132 qemu_put_be32s(f, &s->hw_cursor_x);
3133 qemu_put_be32s(f, &s->hw_cursor_y);
3134 /* XXX: we do not save the bitblt state - we assume we do not save
3135 the state when the blitter is active */
3136
3137 if (kvm_enabled()) { /* XXX: KVM images ought to be loadable in QEMU */
3138 qemu_put_be32s(f, &s->real_vram_size);
3139 qemu_put_buffer(f, s->vram_ptr, s->real_vram_size);
3140 }
3141 }
3142
3143 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3144 {
3145 CirrusVGAState *s = opaque;
3146 int ret;
3147
3148 if (version_id > 2)
3149 return -EINVAL;
3150
3151 if (s->pci_dev && version_id >= 2) {
3152 ret = pci_device_load(s->pci_dev, f);
3153 if (ret < 0)
3154 return ret;
3155 }
3156
3157 qemu_get_be32s(f, &s->latch);
3158 qemu_get_8s(f, &s->sr_index);
3159 qemu_get_buffer(f, s->sr, 256);
3160 qemu_get_8s(f, &s->gr_index);
3161 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3162 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3163 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3164 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3165 qemu_get_buffer(f, s->gr + 2, 254);
3166 qemu_get_8s(f, &s->ar_index);
3167 qemu_get_buffer(f, s->ar, 21);
3168 s->ar_flip_flop=qemu_get_be32(f);
3169 qemu_get_8s(f, &s->cr_index);
3170 qemu_get_buffer(f, s->cr, 256);
3171 qemu_get_8s(f, &s->msr);
3172 qemu_get_8s(f, &s->fcr);
3173 qemu_get_8s(f, &s->st00);
3174 qemu_get_8s(f, &s->st01);
3175
3176 qemu_get_8s(f, &s->dac_state);
3177 qemu_get_8s(f, &s->dac_sub_index);
3178 qemu_get_8s(f, &s->dac_read_index);
3179 qemu_get_8s(f, &s->dac_write_index);
3180 qemu_get_buffer(f, s->dac_cache, 3);
3181 qemu_get_buffer(f, s->palette, 768);
3182
3183 s->bank_offset=qemu_get_be32(f);
3184
3185 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3186 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3187
3188 qemu_get_be32s(f, &s->hw_cursor_x);
3189 qemu_get_be32s(f, &s->hw_cursor_y);
3190
3191 if (kvm_enabled()) {
3192 int real_vram_size;
3193 qemu_get_be32s(f, &real_vram_size);
3194 if (real_vram_size != s->real_vram_size) {
3195 if (real_vram_size > s->real_vram_size)
3196 real_vram_size = s->real_vram_size;
3197 printf("%s: REAL_VRAM_SIZE MISMATCH !!!!!! SAVED=%d CURRENT=%d",
3198 __FUNCTION__, real_vram_size, s->real_vram_size);
3199 }
3200 qemu_get_buffer(f, s->vram_ptr, real_vram_size);
3201 cirrus_update_memory_access(s);
3202 }
3203
3204
3205 /* force refresh */
3206 s->graphic_mode = -1;
3207 cirrus_update_bank_ptr(s, 0);
3208 cirrus_update_bank_ptr(s, 1);
3209 return 0;
3210 }
3211
3212 /***************************************
3213 *
3214 * initialize
3215 *
3216 ***************************************/
3217
3218 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3219 {
3220 int vga_io_memory, i;
3221 static int inited;
3222
3223 if (!inited) {
3224 inited = 1;
3225 for(i = 0;i < 256; i++)
3226 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3227 rop_to_index[CIRRUS_ROP_0] = 0;
3228 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3229 rop_to_index[CIRRUS_ROP_NOP] = 2;
3230 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3231 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3232 rop_to_index[CIRRUS_ROP_SRC] = 5;
3233 rop_to_index[CIRRUS_ROP_1] = 6;
3234 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3235 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3236 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3237 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3238 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3239 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3240 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3241 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3242 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3243 }
3244
3245 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3246
3247 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3248 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3249 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3250 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3251
3252 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3253
3254 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3255 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3256 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3257 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3258
3259 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3260 cirrus_vga_mem_write, s);
3261 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3262 vga_io_memory);
3263
3264 s->sr[0x06] = 0x0f;
3265 if (device_id == CIRRUS_ID_CLGD5446) {
3266 /* 4MB 64 bit memory config, always PCI */
3267 s->sr[0x1F] = 0x2d; // MemClock
3268 s->gr[0x18] = 0x0f; // fastest memory configuration
3269 #if 1
3270 s->sr[0x0f] = 0x98;
3271 s->sr[0x17] = 0x20;
3272 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3273 s->real_vram_size = 4096 * 1024;
3274 #else
3275 s->sr[0x0f] = 0x18;
3276 s->sr[0x17] = 0x20;
3277 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3278 s->real_vram_size = 2048 * 1024;
3279 #endif
3280 } else {
3281 s->sr[0x1F] = 0x22; // MemClock
3282 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3283 if (is_pci)
3284 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3285 else
3286 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3287 s->real_vram_size = 2048 * 1024;
3288 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3289 }
3290 s->cr[0x27] = device_id;
3291
3292 /* Win2K seems to assume that the pattern buffer is at 0xff
3293 initially ! */
3294 memset(s->vram_ptr, 0xff, s->real_vram_size);
3295
3296 s->cirrus_hidden_dac_lockindex = 5;
3297 s->cirrus_hidden_dac_data = 0;
3298
3299 /* I/O handler for LFB */
3300 s->cirrus_linear_io_addr =
3301 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3302 s);
3303 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3304
3305 /* I/O handler for LFB */
3306 s->cirrus_linear_bitblt_io_addr =
3307 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3308 s);
3309
3310 /* I/O handler for memory-mapped I/O */
3311 s->cirrus_mmio_io_addr =
3312 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3313
3314 /* XXX: s->vram_size must be a power of two */
3315 s->cirrus_addr_mask = s->real_vram_size - 1;
3316 s->linear_mmio_mask = s->real_vram_size - 256;
3317
3318 s->get_bpp = cirrus_get_bpp;
3319 s->get_offsets = cirrus_get_offsets;
3320 s->get_resolution = cirrus_get_resolution;
3321 s->cursor_invalidate = cirrus_cursor_invalidate;
3322 s->cursor_draw_line = cirrus_cursor_draw_line;
3323
3324 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3325 }
3326
3327 /***************************************
3328 *
3329 * ISA bus support
3330 *
3331 ***************************************/
3332
3333 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3334 unsigned long vga_ram_offset, int vga_ram_size)
3335 {
3336 CirrusVGAState *s;
3337
3338 s = qemu_mallocz(sizeof(CirrusVGAState));
3339
3340 vga_common_init((VGAState *)s,
3341 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3342 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3343 /* XXX ISA-LFB support */
3344 }
3345
3346 /***************************************
3347 *
3348 * PCI bus support
3349 *
3350 ***************************************/
3351
3352 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3353 uint32_t addr, uint32_t size, int type)
3354 {
3355 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3356
3357 /* XXX: add byte swapping apertures */
3358 cpu_register_physical_memory(addr, s->vram_size,
3359 s->cirrus_linear_io_addr);
3360 if (kvm_enabled()) {
3361 s->cirrus_lfb_addr = addr;
3362 s->cirrus_lfb_end = addr + VGA_RAM_SIZE;
3363
3364 if (s->map_addr && (s->cirrus_lfb_addr != s->map_addr) &&
3365 (s->cirrus_lfb_end != s->map_end))
3366 printf("cirrus vga map change while on lfb mode\n");
3367 }
3368
3369 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3370 s->cirrus_linear_bitblt_io_addr);
3371 }
3372
3373 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3374 uint32_t addr, uint32_t size, int type)
3375 {
3376 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3377
3378 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3379 s->cirrus_mmio_io_addr);
3380 }
3381
3382 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3383 unsigned long vga_ram_offset, int vga_ram_size)
3384 {
3385 PCICirrusVGAState *d;
3386 uint8_t *pci_conf;
3387 CirrusVGAState *s;
3388 int device_id;
3389
3390 device_id = CIRRUS_ID_CLGD5446;
3391
3392 /* setup PCI configuration registers */
3393 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3394 sizeof(PCICirrusVGAState),
3395 -1, NULL, NULL);
3396 pci_conf = d->dev.config;
3397 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3398 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3399 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3400 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3401 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3402 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3403 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3404 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3405
3406 /* setup VGA */
3407 s = &d->cirrus_vga;
3408 vga_common_init((VGAState *)s,
3409 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3410 cirrus_init_common(s, device_id, 1);
3411
3412 graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump,
3413 s->text_update, s);
3414
3415 s->pci_dev = (PCIDevice *)d;
3416
3417 /* setup memory space */
3418 /* memory #0 LFB */
3419 /* memory #1 memory-mapped I/O */
3420 /* XXX: s->vram_size must be a power of two */
3421 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3422 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3423 if (device_id == CIRRUS_ID_CLGD5446) {
3424 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3425 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3426 }
3427 /* XXX: ROM BIOS */
3428 }
Patches shipped by Fedora