Kill redundant declarion of perror()
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blob01748ed25b22a950f9df9528b35f8f9216140cd6
1 /*
2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
9 #include "config.h"
10 #include "config-host.h"
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
17 #include "qemu-kvm.h"
18 #include <libkvm.h>
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
23 #define MSR_IA32_TSC 0x10
25 static struct kvm_msr_list *kvm_msr_list;
26 extern unsigned int kvm_shadow_memory;
27 static int kvm_has_msr_star;
29 static int lm_capable_kernel;
31 int kvm_qemu_create_memory_alias(uint64_t phys_start,
32 uint64_t len,
33 uint64_t target_phys)
35 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
38 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
40 return kvm_destroy_memory_alias(kvm_context, phys_start);
43 int kvm_arch_qemu_create_context(void)
45 int i;
46 struct utsname utsname;
48 uname(&utsname);
49 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
51 if (kvm_shadow_memory)
52 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
54 kvm_msr_list = kvm_get_msr_list(kvm_context);
55 if (!kvm_msr_list)
56 return -1;
57 for (i = 0; i < kvm_msr_list->nmsrs; ++i)
58 if (kvm_msr_list->indices[i] == MSR_STAR)
59 kvm_has_msr_star = 1;
60 return 0;
63 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
64 uint64_t data)
66 entry->index = index;
67 entry->data = data;
70 /* returns 0 on success, non-0 on failure */
71 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
73 switch (entry->index) {
74 case MSR_IA32_SYSENTER_CS:
75 env->sysenter_cs = entry->data;
76 break;
77 case MSR_IA32_SYSENTER_ESP:
78 env->sysenter_esp = entry->data;
79 break;
80 case MSR_IA32_SYSENTER_EIP:
81 env->sysenter_eip = entry->data;
82 break;
83 case MSR_STAR:
84 env->star = entry->data;
85 break;
86 #ifdef TARGET_X86_64
87 case MSR_CSTAR:
88 env->cstar = entry->data;
89 break;
90 case MSR_KERNELGSBASE:
91 env->kernelgsbase = entry->data;
92 break;
93 case MSR_FMASK:
94 env->fmask = entry->data;
95 break;
96 case MSR_LSTAR:
97 env->lstar = entry->data;
98 break;
99 #endif
100 case MSR_IA32_TSC:
101 env->tsc = entry->data;
102 break;
103 case MSR_VM_HSAVE_PA:
104 env->vm_hsave = entry->data;
105 break;
106 default:
107 printf("Warning unknown msr index 0x%x\n", entry->index);
108 return 1;
110 return 0;
113 #ifdef TARGET_X86_64
114 #define MSR_COUNT 9
115 #else
116 #define MSR_COUNT 5
117 #endif
119 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
121 lhs->selector = rhs->selector;
122 lhs->base = rhs->base;
123 lhs->limit = rhs->limit;
124 lhs->type = 3;
125 lhs->present = 1;
126 lhs->dpl = 3;
127 lhs->db = 0;
128 lhs->s = 1;
129 lhs->l = 0;
130 lhs->g = 0;
131 lhs->avl = 0;
132 lhs->unusable = 0;
135 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
137 unsigned flags = rhs->flags;
138 lhs->selector = rhs->selector;
139 lhs->base = rhs->base;
140 lhs->limit = rhs->limit;
141 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
142 lhs->present = (flags & DESC_P_MASK) != 0;
143 lhs->dpl = rhs->selector & 3;
144 lhs->db = (flags >> DESC_B_SHIFT) & 1;
145 lhs->s = (flags & DESC_S_MASK) != 0;
146 lhs->l = (flags >> DESC_L_SHIFT) & 1;
147 lhs->g = (flags & DESC_G_MASK) != 0;
148 lhs->avl = (flags & DESC_AVL_MASK) != 0;
149 lhs->unusable = 0;
152 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
154 lhs->selector = rhs->selector;
155 lhs->base = rhs->base;
156 lhs->limit = rhs->limit;
157 lhs->flags =
158 (rhs->type << DESC_TYPE_SHIFT)
159 | (rhs->present * DESC_P_MASK)
160 | (rhs->dpl << DESC_DPL_SHIFT)
161 | (rhs->db << DESC_B_SHIFT)
162 | (rhs->s * DESC_S_MASK)
163 | (rhs->l << DESC_L_SHIFT)
164 | (rhs->g * DESC_G_MASK)
165 | (rhs->avl * DESC_AVL_MASK);
168 void kvm_arch_load_regs(CPUState *env)
170 struct kvm_regs regs;
171 struct kvm_fpu fpu;
172 struct kvm_sregs sregs;
173 struct kvm_msr_entry msrs[MSR_COUNT];
174 int rc, n, i;
176 regs.rax = env->regs[R_EAX];
177 regs.rbx = env->regs[R_EBX];
178 regs.rcx = env->regs[R_ECX];
179 regs.rdx = env->regs[R_EDX];
180 regs.rsi = env->regs[R_ESI];
181 regs.rdi = env->regs[R_EDI];
182 regs.rsp = env->regs[R_ESP];
183 regs.rbp = env->regs[R_EBP];
184 #ifdef TARGET_X86_64
185 regs.r8 = env->regs[8];
186 regs.r9 = env->regs[9];
187 regs.r10 = env->regs[10];
188 regs.r11 = env->regs[11];
189 regs.r12 = env->regs[12];
190 regs.r13 = env->regs[13];
191 regs.r14 = env->regs[14];
192 regs.r15 = env->regs[15];
193 #endif
195 regs.rflags = env->eflags;
196 regs.rip = env->eip;
198 kvm_set_regs(kvm_context, env->cpu_index, &regs);
200 memset(&fpu, 0, sizeof fpu);
201 fpu.fsw = env->fpus & ~(7 << 11);
202 fpu.fsw |= (env->fpstt & 7) << 11;
203 fpu.fcw = env->fpuc;
204 for (i = 0; i < 8; ++i)
205 fpu.ftwx |= (!env->fptags[i]) << i;
206 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
207 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
208 fpu.mxcsr = env->mxcsr;
209 kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
211 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
213 if ((env->eflags & VM_MASK)) {
214 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
215 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
216 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
217 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
218 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
219 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
220 } else {
221 set_seg(&sregs.cs, &env->segs[R_CS]);
222 set_seg(&sregs.ds, &env->segs[R_DS]);
223 set_seg(&sregs.es, &env->segs[R_ES]);
224 set_seg(&sregs.fs, &env->segs[R_FS]);
225 set_seg(&sregs.gs, &env->segs[R_GS]);
226 set_seg(&sregs.ss, &env->segs[R_SS]);
228 if (env->cr[0] & CR0_PE_MASK) {
229 /* force ss cpl to cs cpl */
230 sregs.ss.selector = (sregs.ss.selector & ~3) |
231 (sregs.cs.selector & 3);
232 sregs.ss.dpl = sregs.ss.selector & 3;
236 set_seg(&sregs.tr, &env->tr);
237 set_seg(&sregs.ldt, &env->ldt);
239 sregs.idt.limit = env->idt.limit;
240 sregs.idt.base = env->idt.base;
241 sregs.gdt.limit = env->gdt.limit;
242 sregs.gdt.base = env->gdt.base;
244 sregs.cr0 = env->cr[0];
245 sregs.cr2 = env->cr[2];
246 sregs.cr3 = env->cr[3];
247 sregs.cr4 = env->cr[4];
249 sregs.cr8 = cpu_get_apic_tpr(env);
250 sregs.apic_base = cpu_get_apic_base(env);
252 sregs.efer = env->efer;
254 kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
256 /* msrs */
257 n = 0;
258 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
259 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
260 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
261 if (kvm_has_msr_star)
262 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
263 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
264 #ifdef TARGET_X86_64
265 if (lm_capable_kernel) {
266 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
267 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
268 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
269 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
271 #endif
273 rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
274 if (rc == -1)
275 perror("kvm_set_msrs FAILED");
278 void kvm_load_tsc(CPUState *env)
280 int rc;
281 struct kvm_msr_entry msr;
283 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
285 rc = kvm_set_msrs(kvm_context, env->cpu_index, &msr, 1);
286 if (rc == -1)
287 perror("kvm_set_tsc FAILED.\n");
290 void kvm_save_mpstate(CPUState *env)
292 #ifdef KVM_CAP_MP_STATE
293 int r;
294 struct kvm_mp_state mp_state;
296 r = kvm_get_mpstate(kvm_context, env->cpu_index, &mp_state);
297 if (r < 0)
298 env->mp_state = -1;
299 else
300 env->mp_state = mp_state.mp_state;
301 #endif
304 void kvm_load_mpstate(CPUState *env)
306 #ifdef KVM_CAP_MP_STATE
307 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
310 * -1 indicates that the host did not support GET_MP_STATE ioctl,
311 * so don't touch it.
313 if (env->mp_state != -1)
314 kvm_set_mpstate(kvm_context, env->cpu_index, &mp_state);
315 #endif
318 void kvm_arch_save_regs(CPUState *env)
320 struct kvm_regs regs;
321 struct kvm_fpu fpu;
322 struct kvm_sregs sregs;
323 struct kvm_msr_entry msrs[MSR_COUNT];
324 uint32_t hflags;
325 uint32_t i, n, rc;
327 kvm_get_regs(kvm_context, env->cpu_index, &regs);
329 env->regs[R_EAX] = regs.rax;
330 env->regs[R_EBX] = regs.rbx;
331 env->regs[R_ECX] = regs.rcx;
332 env->regs[R_EDX] = regs.rdx;
333 env->regs[R_ESI] = regs.rsi;
334 env->regs[R_EDI] = regs.rdi;
335 env->regs[R_ESP] = regs.rsp;
336 env->regs[R_EBP] = regs.rbp;
337 #ifdef TARGET_X86_64
338 env->regs[8] = regs.r8;
339 env->regs[9] = regs.r9;
340 env->regs[10] = regs.r10;
341 env->regs[11] = regs.r11;
342 env->regs[12] = regs.r12;
343 env->regs[13] = regs.r13;
344 env->regs[14] = regs.r14;
345 env->regs[15] = regs.r15;
346 #endif
348 env->eflags = regs.rflags;
349 env->eip = regs.rip;
351 kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
352 env->fpstt = (fpu.fsw >> 11) & 7;
353 env->fpus = fpu.fsw;
354 env->fpuc = fpu.fcw;
355 for (i = 0; i < 8; ++i)
356 env->fptags[i] = !((fpu.ftwx >> i) & 1);
357 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
358 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
359 env->mxcsr = fpu.mxcsr;
361 kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
363 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
365 get_seg(&env->segs[R_CS], &sregs.cs);
366 get_seg(&env->segs[R_DS], &sregs.ds);
367 get_seg(&env->segs[R_ES], &sregs.es);
368 get_seg(&env->segs[R_FS], &sregs.fs);
369 get_seg(&env->segs[R_GS], &sregs.gs);
370 get_seg(&env->segs[R_SS], &sregs.ss);
372 get_seg(&env->tr, &sregs.tr);
373 get_seg(&env->ldt, &sregs.ldt);
375 env->idt.limit = sregs.idt.limit;
376 env->idt.base = sregs.idt.base;
377 env->gdt.limit = sregs.gdt.limit;
378 env->gdt.base = sregs.gdt.base;
380 env->cr[0] = sregs.cr0;
381 env->cr[2] = sregs.cr2;
382 env->cr[3] = sregs.cr3;
383 env->cr[4] = sregs.cr4;
385 cpu_set_apic_base(env, sregs.apic_base);
387 env->efer = sregs.efer;
388 //cpu_set_apic_tpr(env, sregs.cr8);
390 #define HFLAG_COPY_MASK ~( \
391 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
392 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
393 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
394 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
398 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
399 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
400 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
401 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
402 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
403 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
404 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
406 if (env->efer & MSR_EFER_LMA) {
407 hflags |= HF_LMA_MASK;
410 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
411 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
412 } else {
413 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
414 (DESC_B_SHIFT - HF_CS32_SHIFT);
415 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
416 (DESC_B_SHIFT - HF_SS32_SHIFT);
417 if (!(env->cr[0] & CR0_PE_MASK) ||
418 (env->eflags & VM_MASK) ||
419 !(hflags & HF_CS32_MASK)) {
420 hflags |= HF_ADDSEG_MASK;
421 } else {
422 hflags |= ((env->segs[R_DS].base |
423 env->segs[R_ES].base |
424 env->segs[R_SS].base) != 0) <<
425 HF_ADDSEG_SHIFT;
428 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
429 env->cc_src = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
430 env->df = 1 - (2 * ((env->eflags >> 10) & 1));
431 env->cc_op = CC_OP_EFLAGS;
432 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
434 /* msrs */
435 n = 0;
436 msrs[n++].index = MSR_IA32_SYSENTER_CS;
437 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
438 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
439 if (kvm_has_msr_star)
440 msrs[n++].index = MSR_STAR;
441 msrs[n++].index = MSR_IA32_TSC;
442 msrs[n++].index = MSR_VM_HSAVE_PA;
443 #ifdef TARGET_X86_64
444 if (lm_capable_kernel) {
445 msrs[n++].index = MSR_CSTAR;
446 msrs[n++].index = MSR_KERNELGSBASE;
447 msrs[n++].index = MSR_FMASK;
448 msrs[n++].index = MSR_LSTAR;
450 #endif
451 rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
452 if (rc == -1) {
453 perror("kvm_get_msrs FAILED");
455 else {
456 n = rc; /* actual number of MSRs */
457 for (i=0 ; i<n; i++) {
458 if (get_msr_entry(&msrs[i], env))
459 return;
464 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
465 uint32_t count, CPUState *env)
467 env->regs[R_EAX] = function;
468 env->regs[R_ECX] = count;
469 qemu_kvm_cpuid_on_env(env);
470 e->function = function;
471 e->eax = env->regs[R_EAX];
472 e->ebx = env->regs[R_EBX];
473 e->ecx = env->regs[R_ECX];
474 e->edx = env->regs[R_EDX];
477 struct kvm_para_features {
478 int cap;
479 int feature;
480 } para_features[] = {
481 #ifdef KVM_CAP_CLOCKSOURCE
482 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
483 #endif
484 #ifdef KVM_CAP_NOP_IO_DELAY
485 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
486 #endif
487 #ifdef KVM_CAP_PV_MMU
488 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
489 #endif
490 #ifdef KVM_CAP_CR3_CACHE
491 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
492 #endif
493 { -1, -1 }
496 static int get_para_features(kvm_context_t kvm_context)
498 int i, features = 0;
500 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
501 if (kvm_check_extension(kvm_context, para_features[i].cap))
502 features |= (1 << para_features[i].feature);
505 return features;
508 int kvm_arch_qemu_init_env(CPUState *cenv)
510 struct kvm_cpuid_entry2 cpuid_ent[100];
511 #ifdef KVM_CPUID_SIGNATURE
512 struct kvm_cpuid_entry2 *pv_ent;
513 uint32_t signature[3];
514 #endif
515 int cpuid_nent = 0;
516 CPUState copy;
517 uint32_t i, j, limit;
519 copy = *cenv;
521 #ifdef KVM_CPUID_SIGNATURE
522 /* Paravirtualization CPUIDs */
523 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
524 pv_ent = &cpuid_ent[cpuid_nent++];
525 memset(pv_ent, 0, sizeof(*pv_ent));
526 pv_ent->function = KVM_CPUID_SIGNATURE;
527 pv_ent->eax = 0;
528 pv_ent->ebx = signature[0];
529 pv_ent->ecx = signature[1];
530 pv_ent->edx = signature[2];
532 pv_ent = &cpuid_ent[cpuid_nent++];
533 memset(pv_ent, 0, sizeof(*pv_ent));
534 pv_ent->function = KVM_CPUID_FEATURES;
535 pv_ent->eax = get_para_features(kvm_context);
536 #endif
538 copy.regs[R_EAX] = 0;
539 qemu_kvm_cpuid_on_env(&copy);
540 limit = copy.regs[R_EAX];
542 for (i = 0; i <= limit; ++i) {
543 if (i == 4 || i == 0xb || i == 0xd) {
544 for (j = 0; ; ++j) {
545 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
547 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
548 cpuid_ent[cpuid_nent].index = j;
550 cpuid_nent++;
552 if (i == 4 && copy.regs[R_EAX] == 0)
553 break;
554 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
555 break;
556 if (i == 0xd && copy.regs[R_EAX] == 0)
557 break;
559 } else
560 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
563 copy.regs[R_EAX] = 0x80000000;
564 qemu_kvm_cpuid_on_env(&copy);
565 limit = copy.regs[R_EAX];
567 for (i = 0x80000000; i <= limit; ++i)
568 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
570 kvm_setup_cpuid2(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
571 return 0;
574 int kvm_arch_halt(void *opaque, int vcpu)
576 CPUState *env = cpu_single_env;
578 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
579 (env->eflags & IF_MASK)) &&
580 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
581 env->halted = 1;
582 env->exception_index = EXCP_HLT;
584 return 1;
587 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
589 if (!kvm_irqchip_in_kernel(kvm_context))
590 kvm_set_cr8(kvm_context, env->cpu_index, cpu_get_apic_tpr(env));
593 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
595 int vcpu = env->cpu_index;
597 cpu_single_env = env;
599 env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
600 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
602 cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
603 cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
606 int kvm_arch_has_work(CPUState *env)
608 if (((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
609 (env->eflags & IF_MASK)) ||
610 (env->interrupt_request & CPU_INTERRUPT_NMI))
611 return 1;
612 return 0;
615 int kvm_arch_try_push_interrupts(void *opaque)
617 CPUState *env = cpu_single_env;
618 int r, irq;
620 if (kvm_is_ready_for_interrupt_injection(kvm_context, env->cpu_index) &&
621 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
622 (env->eflags & IF_MASK)) {
623 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
624 irq = cpu_get_pic_interrupt(env);
625 if (irq >= 0) {
626 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
627 if (r < 0)
628 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
632 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
635 #ifdef KVM_CAP_USER_NMI
636 void kvm_arch_push_nmi(void *opaque)
638 CPUState *env = cpu_single_env;
639 int r;
641 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
642 return;
644 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
645 r = kvm_inject_nmi(kvm_context, env->cpu_index);
646 if (r < 0)
647 printf("cpu %d fail inject NMI\n", env->cpu_index);
649 #endif /* KVM_CAP_USER_NMI */
651 void kvm_arch_update_regs_for_sipi(CPUState *env)
653 SegmentCache cs = env->segs[R_CS];
655 kvm_arch_save_regs(env);
656 env->segs[R_CS] = cs;
657 env->eip = 0;
658 kvm_arch_load_regs(env);
661 int handle_tpr_access(void *opaque, int vcpu,
662 uint64_t rip, int is_write)
664 kvm_tpr_access_report(cpu_single_env, rip, is_write);
665 return 0;
668 void kvm_arch_cpu_reset(CPUState *env)
670 kvm_arch_load_regs(env);
671 if (env->cpu_index != 0) {
672 if (kvm_irqchip_in_kernel(kvm_context)) {
673 #ifdef KVM_CAP_MP_STATE
674 kvm_reset_mpstate(kvm_context, env->cpu_index);
675 #endif
676 } else {
677 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
678 env->halted = 1;
679 env->exception_index = EXCP_HLT;
684 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
686 uint8_t int3 = 0xcc;
688 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
689 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
690 return -EINVAL;
691 return 0;
694 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
696 uint8_t int3;
698 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
699 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
700 return -EINVAL;
701 return 0;
704 #ifdef KVM_CAP_SET_GUEST_DEBUG
705 static struct {
706 target_ulong addr;
707 int len;
708 int type;
709 } hw_breakpoint[4];
711 static int nb_hw_breakpoint;
713 static int find_hw_breakpoint(target_ulong addr, int len, int type)
715 int n;
717 for (n = 0; n < nb_hw_breakpoint; n++)
718 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
719 (hw_breakpoint[n].len == len || len == -1))
720 return n;
721 return -1;
724 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
725 target_ulong len, int type)
727 switch (type) {
728 case GDB_BREAKPOINT_HW:
729 len = 1;
730 break;
731 case GDB_WATCHPOINT_WRITE:
732 case GDB_WATCHPOINT_ACCESS:
733 switch (len) {
734 case 1:
735 break;
736 case 2:
737 case 4:
738 case 8:
739 if (addr & (len - 1))
740 return -EINVAL;
741 break;
742 default:
743 return -EINVAL;
745 break;
746 default:
747 return -ENOSYS;
750 if (nb_hw_breakpoint == 4)
751 return -ENOBUFS;
753 if (find_hw_breakpoint(addr, len, type) >= 0)
754 return -EEXIST;
756 hw_breakpoint[nb_hw_breakpoint].addr = addr;
757 hw_breakpoint[nb_hw_breakpoint].len = len;
758 hw_breakpoint[nb_hw_breakpoint].type = type;
759 nb_hw_breakpoint++;
761 return 0;
764 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
765 target_ulong len, int type)
767 int n;
769 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
770 if (n < 0)
771 return -ENOENT;
773 nb_hw_breakpoint--;
774 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
776 return 0;
779 void kvm_arch_remove_all_hw_breakpoints(void)
781 nb_hw_breakpoint = 0;
784 static CPUWatchpoint hw_watchpoint;
786 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
788 int handle = 0;
789 int n;
791 if (arch_info->exception == 1) {
792 if (arch_info->dr6 & (1 << 14)) {
793 if (cpu_single_env->singlestep_enabled)
794 handle = 1;
795 } else {
796 for (n = 0; n < 4; n++)
797 if (arch_info->dr6 & (1 << n))
798 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
799 case 0x0:
800 handle = 1;
801 break;
802 case 0x1:
803 handle = 1;
804 cpu_single_env->watchpoint_hit = &hw_watchpoint;
805 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
806 hw_watchpoint.flags = BP_MEM_WRITE;
807 break;
808 case 0x3:
809 handle = 1;
810 cpu_single_env->watchpoint_hit = &hw_watchpoint;
811 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
812 hw_watchpoint.flags = BP_MEM_ACCESS;
813 break;
816 } else if (kvm_find_sw_breakpoint(arch_info->pc))
817 handle = 1;
819 if (!handle)
820 kvm_update_guest_debug(cpu_single_env,
821 (arch_info->exception == 1) ?
822 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
824 return handle;
827 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
829 const uint8_t type_code[] = {
830 [GDB_BREAKPOINT_HW] = 0x0,
831 [GDB_WATCHPOINT_WRITE] = 0x1,
832 [GDB_WATCHPOINT_ACCESS] = 0x3
834 const uint8_t len_code[] = {
835 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
837 int n;
839 if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
840 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
842 if (nb_hw_breakpoint > 0) {
843 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
844 dbg->arch.debugreg[7] = 0x0600;
845 for (n = 0; n < nb_hw_breakpoint; n++) {
846 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
847 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
848 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
849 (len_code[hw_breakpoint[n].len] << (18 + n*4));
853 #endif
855 void kvm_arch_do_ioperm(void *_data)
857 struct ioperm_data *data = _data;
858 ioperm(data->start_port, data->num, data->turn_on);