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Kill redundant declarion of perror()
[qemu-kvm/fedora.git] / hw / vga.c
blob3cde8189422b10162b8cd02aacc8a215c51ead89
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "vga_int.h"
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
31 #include "kvm.h"
32 #include "qemu-kvm.h"
33
34 //#define DEBUG_VGA
35 //#define DEBUG_VGA_MEM
36 //#define DEBUG_VGA_REG
37
38 //#define DEBUG_BOCHS_VBE
39
40 /* force some bits to zero */
41 const uint8_t sr_mask[8] = {
42 (uint8_t)~0xfc,
43 (uint8_t)~0xc2,
44 (uint8_t)~0xf0,
45 (uint8_t)~0xc0,
46 (uint8_t)~0xf1,
47 (uint8_t)~0xff,
48 (uint8_t)~0xff,
49 (uint8_t)~0x00,
50 };
51
52 const uint8_t gr_mask[16] = {
53 (uint8_t)~0xf0, /* 0x00 */
54 (uint8_t)~0xf0, /* 0x01 */
55 (uint8_t)~0xf0, /* 0x02 */
56 (uint8_t)~0xe0, /* 0x03 */
57 (uint8_t)~0xfc, /* 0x04 */
58 (uint8_t)~0x84, /* 0x05 */
59 (uint8_t)~0xf0, /* 0x06 */
60 (uint8_t)~0xf0, /* 0x07 */
61 (uint8_t)~0x00, /* 0x08 */
62 (uint8_t)~0xff, /* 0x09 */
63 (uint8_t)~0xff, /* 0x0a */
64 (uint8_t)~0xff, /* 0x0b */
65 (uint8_t)~0xff, /* 0x0c */
66 (uint8_t)~0xff, /* 0x0d */
67 (uint8_t)~0xff, /* 0x0e */
68 (uint8_t)~0xff, /* 0x0f */
69 };
70
71 #define cbswap_32(__x) \
72 ((uint32_t)( \
73 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
74 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
75 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
76 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77
78 #ifdef WORDS_BIGENDIAN
79 #define PAT(x) cbswap_32(x)
80 #else
81 #define PAT(x) (x)
82 #endif
83
84 #ifdef WORDS_BIGENDIAN
85 #define BIG 1
86 #else
87 #define BIG 0
88 #endif
89
90 #ifdef WORDS_BIGENDIAN
91 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #else
93 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
94 #endif
95
96 static const uint32_t mask16[16] = {
97 PAT(0x00000000),
98 PAT(0x000000ff),
99 PAT(0x0000ff00),
100 PAT(0x0000ffff),
101 PAT(0x00ff0000),
102 PAT(0x00ff00ff),
103 PAT(0x00ffff00),
104 PAT(0x00ffffff),
105 PAT(0xff000000),
106 PAT(0xff0000ff),
107 PAT(0xff00ff00),
108 PAT(0xff00ffff),
109 PAT(0xffff0000),
110 PAT(0xffff00ff),
111 PAT(0xffffff00),
112 PAT(0xffffffff),
113 };
114
115 #undef PAT
116
117 #ifdef WORDS_BIGENDIAN
118 #define PAT(x) (x)
119 #else
120 #define PAT(x) cbswap_32(x)
121 #endif
122
123 static const uint32_t dmask16[16] = {
124 PAT(0x00000000),
125 PAT(0x000000ff),
126 PAT(0x0000ff00),
127 PAT(0x0000ffff),
128 PAT(0x00ff0000),
129 PAT(0x00ff00ff),
130 PAT(0x00ffff00),
131 PAT(0x00ffffff),
132 PAT(0xff000000),
133 PAT(0xff0000ff),
134 PAT(0xff00ff00),
135 PAT(0xff00ffff),
136 PAT(0xffff0000),
137 PAT(0xffff00ff),
138 PAT(0xffffff00),
139 PAT(0xffffffff),
140 };
141
142 static const uint32_t dmask4[4] = {
143 PAT(0x00000000),
144 PAT(0x0000ffff),
145 PAT(0xffff0000),
146 PAT(0xffffffff),
147 };
148
149 static uint32_t expand4[256];
150 static uint16_t expand2[256];
151 static uint8_t expand4to8[16];
152
153 static void vga_screen_dump(void *opaque, const char *filename);
154
155 static void vga_dumb_update_retrace_info(VGAState *s)
156 {
157 (void) s;
158 }
159
160 static void vga_precise_update_retrace_info(VGAState *s)
161 {
162 int htotal_chars;
163 int hretr_start_char;
164 int hretr_skew_chars;
165 int hretr_end_char;
166
167 int vtotal_lines;
168 int vretr_start_line;
169 int vretr_end_line;
170
171 int div2, sldiv2, dots;
172 int clocking_mode;
173 int clock_sel;
174 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
175 int64_t chars_per_sec;
176 struct vga_precise_retrace *r = &s->retrace_info.precise;
177
178 htotal_chars = s->cr[0x00] + 5;
179 hretr_start_char = s->cr[0x04];
180 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
181 hretr_end_char = s->cr[0x05] & 0x1f;
182
183 vtotal_lines = (s->cr[0x06]
184 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
185 ;
186 vretr_start_line = s->cr[0x10]
187 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
188 ;
189 vretr_end_line = s->cr[0x11] & 0xf;
190
191
192 div2 = (s->cr[0x17] >> 2) & 1;
193 sldiv2 = (s->cr[0x17] >> 3) & 1;
194
195 clocking_mode = (s->sr[0x01] >> 3) & 1;
196 clock_sel = (s->msr >> 2) & 3;
197 dots = (s->msr & 1) ? 8 : 9;
198
199 chars_per_sec = clk_hz[clock_sel] / dots;
200
201 htotal_chars <<= clocking_mode;
202
203 r->total_chars = vtotal_lines * htotal_chars;
204 if (r->freq) {
205 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
206 } else {
207 r->ticks_per_char = ticks_per_sec / chars_per_sec;
208 }
209
210 r->vstart = vretr_start_line;
211 r->vend = r->vstart + vretr_end_line + 1;
212
213 r->hstart = hretr_start_char + hretr_skew_chars;
214 r->hend = r->hstart + hretr_end_char + 1;
215 r->htotal = htotal_chars;
216
217 #if 0
218 printf (
219 "hz=%f\n"
220 "htotal = %d\n"
221 "hretr_start = %d\n"
222 "hretr_skew = %d\n"
223 "hretr_end = %d\n"
224 "vtotal = %d\n"
225 "vretr_start = %d\n"
226 "vretr_end = %d\n"
227 "div2 = %d sldiv2 = %d\n"
228 "clocking_mode = %d\n"
229 "clock_sel = %d %d\n"
230 "dots = %d\n"
231 "ticks/char = %lld\n"
232 "\n",
233 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
234 htotal_chars,
235 hretr_start_char,
236 hretr_skew_chars,
237 hretr_end_char,
238 vtotal_lines,
239 vretr_start_line,
240 vretr_end_line,
241 div2, sldiv2,
242 clocking_mode,
243 clock_sel,
244 clk_hz[clock_sel],
245 dots,
246 r->ticks_per_char
247 );
248 #endif
249 }
250
251 static uint8_t vga_precise_retrace(VGAState *s)
252 {
253 struct vga_precise_retrace *r = &s->retrace_info.precise;
254 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
255
256 if (r->total_chars) {
257 int cur_line, cur_line_char, cur_char;
258 int64_t cur_tick;
259
260 cur_tick = qemu_get_clock(vm_clock);
261
262 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
263 cur_line = cur_char / r->htotal;
264
265 if (cur_line >= r->vstart && cur_line <= r->vend) {
266 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
267 } else {
268 cur_line_char = cur_char % r->htotal;
269 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
270 val |= ST01_DISP_ENABLE;
271 }
272 }
273
274 return val;
275 } else {
276 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
277 }
278 }
279
280 static uint8_t vga_dumb_retrace(VGAState *s)
281 {
282 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
283 }
284
285 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
286 {
287 VGAState *s = opaque;
288 int val, index;
289
290 /* check port range access depending on color/monochrome mode */
291 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
292 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
293 val = 0xff;
294 } else {
295 switch(addr) {
296 case 0x3c0:
297 if (s->ar_flip_flop == 0) {
298 val = s->ar_index;
299 } else {
300 val = 0;
301 }
302 break;
303 case 0x3c1:
304 index = s->ar_index & 0x1f;
305 if (index < 21)
306 val = s->ar[index];
307 else
308 val = 0;
309 break;
310 case 0x3c2:
311 val = s->st00;
312 break;
313 case 0x3c4:
314 val = s->sr_index;
315 break;
316 case 0x3c5:
317 val = s->sr[s->sr_index];
318 #ifdef DEBUG_VGA_REG
319 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
320 #endif
321 break;
322 case 0x3c7:
323 val = s->dac_state;
324 break;
325 case 0x3c8:
326 val = s->dac_write_index;
327 break;
328 case 0x3c9:
329 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
330 if (++s->dac_sub_index == 3) {
331 s->dac_sub_index = 0;
332 s->dac_read_index++;
333 }
334 break;
335 case 0x3ca:
336 val = s->fcr;
337 break;
338 case 0x3cc:
339 val = s->msr;
340 break;
341 case 0x3ce:
342 val = s->gr_index;
343 break;
344 case 0x3cf:
345 val = s->gr[s->gr_index];
346 #ifdef DEBUG_VGA_REG
347 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
348 #endif
349 break;
350 case 0x3b4:
351 case 0x3d4:
352 val = s->cr_index;
353 break;
354 case 0x3b5:
355 case 0x3d5:
356 val = s->cr[s->cr_index];
357 #ifdef DEBUG_VGA_REG
358 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
359 #endif
360 break;
361 case 0x3ba:
362 case 0x3da:
363 /* just toggle to fool polling */
364 val = s->st01 = s->retrace(s);
365 s->ar_flip_flop = 0;
366 break;
367 default:
368 val = 0x00;
369 break;
370 }
371 }
372 #if defined(DEBUG_VGA)
373 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
374 #endif
375 return val;
376 }
377
378 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
379 {
380 VGAState *s = opaque;
381 int index;
382
383 /* check port range access depending on color/monochrome mode */
384 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
385 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
386 return;
387
388 #ifdef DEBUG_VGA
389 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
390 #endif
391
392 switch(addr) {
393 case 0x3c0:
394 if (s->ar_flip_flop == 0) {
395 val &= 0x3f;
396 s->ar_index = val;
397 } else {
398 index = s->ar_index & 0x1f;
399 switch(index) {
400 case 0x00 ... 0x0f:
401 s->ar[index] = val & 0x3f;
402 break;
403 case 0x10:
404 s->ar[index] = val & ~0x10;
405 break;
406 case 0x11:
407 s->ar[index] = val;
408 break;
409 case 0x12:
410 s->ar[index] = val & ~0xc0;
411 break;
412 case 0x13:
413 s->ar[index] = val & ~0xf0;
414 break;
415 case 0x14:
416 s->ar[index] = val & ~0xf0;
417 break;
418 default:
419 break;
420 }
421 }
422 s->ar_flip_flop ^= 1;
423 break;
424 case 0x3c2:
425 s->msr = val & ~0x10;
426 s->update_retrace_info(s);
427 break;
428 case 0x3c4:
429 s->sr_index = val & 7;
430 break;
431 case 0x3c5:
432 #ifdef DEBUG_VGA_REG
433 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
434 #endif
435 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
436 if (s->sr_index == 1) s->update_retrace_info(s);
437 break;
438 case 0x3c7:
439 s->dac_read_index = val;
440 s->dac_sub_index = 0;
441 s->dac_state = 3;
442 break;
443 case 0x3c8:
444 s->dac_write_index = val;
445 s->dac_sub_index = 0;
446 s->dac_state = 0;
447 break;
448 case 0x3c9:
449 s->dac_cache[s->dac_sub_index] = val;
450 if (++s->dac_sub_index == 3) {
451 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
452 s->dac_sub_index = 0;
453 s->dac_write_index++;
454 }
455 break;
456 case 0x3ce:
457 s->gr_index = val & 0x0f;
458 break;
459 case 0x3cf:
460 #ifdef DEBUG_VGA_REG
461 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
462 #endif
463 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
464 break;
465 case 0x3b4:
466 case 0x3d4:
467 s->cr_index = val;
468 break;
469 case 0x3b5:
470 case 0x3d5:
471 #ifdef DEBUG_VGA_REG
472 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
473 #endif
474 /* handle CR0-7 protection */
475 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
476 /* can always write bit 4 of CR7 */
477 if (s->cr_index == 7)
478 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
479 return;
480 }
481 switch(s->cr_index) {
482 case 0x01: /* horizontal display end */
483 case 0x07:
484 case 0x09:
485 case 0x0c:
486 case 0x0d:
487 case 0x12: /* vertical display end */
488 s->cr[s->cr_index] = val;
489 break;
490 default:
491 s->cr[s->cr_index] = val;
492 break;
493 }
494
495 switch(s->cr_index) {
496 case 0x00:
497 case 0x04:
498 case 0x05:
499 case 0x06:
500 case 0x07:
501 case 0x11:
502 case 0x17:
503 s->update_retrace_info(s);
504 break;
505 }
506 break;
507 case 0x3ba:
508 case 0x3da:
509 s->fcr = val & 0x10;
510 break;
511 }
512 }
513
514 #ifdef CONFIG_BOCHS_VBE
515 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
516 {
517 VGAState *s = opaque;
518 uint32_t val;
519 val = s->vbe_index;
520 return val;
521 }
522
523 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
524 {
525 VGAState *s = opaque;
526 uint32_t val;
527
528 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
529 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
530 switch(s->vbe_index) {
531 /* XXX: do not hardcode ? */
532 case VBE_DISPI_INDEX_XRES:
533 val = VBE_DISPI_MAX_XRES;
534 break;
535 case VBE_DISPI_INDEX_YRES:
536 val = VBE_DISPI_MAX_YRES;
537 break;
538 case VBE_DISPI_INDEX_BPP:
539 val = VBE_DISPI_MAX_BPP;
540 break;
541 default:
542 val = s->vbe_regs[s->vbe_index];
543 break;
544 }
545 } else {
546 val = s->vbe_regs[s->vbe_index];
547 }
548 } else {
549 val = 0;
550 }
551 #ifdef DEBUG_BOCHS_VBE
552 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
553 #endif
554 return val;
555 }
556
557 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
558 {
559 VGAState *s = opaque;
560 s->vbe_index = val;
561 }
562
563 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
564 {
565 VGAState *s = opaque;
566
567 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
568 #ifdef DEBUG_BOCHS_VBE
569 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
570 #endif
571 switch(s->vbe_index) {
572 case VBE_DISPI_INDEX_ID:
573 if (val == VBE_DISPI_ID0 ||
574 val == VBE_DISPI_ID1 ||
575 val == VBE_DISPI_ID2 ||
576 val == VBE_DISPI_ID3 ||
577 val == VBE_DISPI_ID4) {
578 s->vbe_regs[s->vbe_index] = val;
579 }
580 break;
581 case VBE_DISPI_INDEX_XRES:
582 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
583 s->vbe_regs[s->vbe_index] = val;
584 }
585 break;
586 case VBE_DISPI_INDEX_YRES:
587 if (val <= VBE_DISPI_MAX_YRES) {
588 s->vbe_regs[s->vbe_index] = val;
589 }
590 break;
591 case VBE_DISPI_INDEX_BPP:
592 if (val == 0)
593 val = 8;
594 if (val == 4 || val == 8 || val == 15 ||
595 val == 16 || val == 24 || val == 32) {
596 s->vbe_regs[s->vbe_index] = val;
597 }
598 break;
599 case VBE_DISPI_INDEX_BANK:
600 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
601 val &= (s->vbe_bank_mask >> 2);
602 } else {
603 val &= s->vbe_bank_mask;
604 }
605 s->vbe_regs[s->vbe_index] = val;
606 s->bank_offset = (val << 16);
607 break;
608 case VBE_DISPI_INDEX_ENABLE:
609 if ((val & VBE_DISPI_ENABLED) &&
610 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
611 int h, shift_control;
612
613 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
614 s->vbe_regs[VBE_DISPI_INDEX_XRES];
615 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
616 s->vbe_regs[VBE_DISPI_INDEX_YRES];
617 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
618 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
619
620 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
621 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
622 else
623 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
624 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
625 s->vbe_start_addr = 0;
626
627 /* clear the screen (should be done in BIOS) */
628 if (!(val & VBE_DISPI_NOCLEARMEM)) {
629 memset(s->vram_ptr, 0,
630 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
631 }
632
633 /* we initialize the VGA graphic mode (should be done
634 in BIOS) */
635 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
636 s->cr[0x17] |= 3; /* no CGA modes */
637 s->cr[0x13] = s->vbe_line_offset >> 3;
638 /* width */
639 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
640 /* height (only meaningful if < 1024) */
641 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
642 s->cr[0x12] = h;
643 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
644 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
645 /* line compare to 1023 */
646 s->cr[0x18] = 0xff;
647 s->cr[0x07] |= 0x10;
648 s->cr[0x09] |= 0x40;
649
650 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
651 shift_control = 0;
652 s->sr[0x01] &= ~8; /* no double line */
653 } else {
654 shift_control = 2;
655 s->sr[4] |= 0x08; /* set chain 4 mode */
656 s->sr[2] |= 0x0f; /* activate all planes */
657 }
658 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
659 s->cr[0x09] &= ~0x9f; /* no double scan */
660 } else {
661 /* XXX: the bios should do that */
662 s->bank_offset = 0;
663 }
664 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
665 s->vbe_regs[s->vbe_index] = val;
666 break;
667 case VBE_DISPI_INDEX_VIRT_WIDTH:
668 {
669 int w, h, line_offset;
670
671 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
672 return;
673 w = val;
674 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
675 line_offset = w >> 1;
676 else
677 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
678 h = s->vram_size / line_offset;
679 /* XXX: support weird bochs semantics ? */
680 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
681 return;
682 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
683 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
684 s->vbe_line_offset = line_offset;
685 }
686 break;
687 case VBE_DISPI_INDEX_X_OFFSET:
688 case VBE_DISPI_INDEX_Y_OFFSET:
689 {
690 int x;
691 s->vbe_regs[s->vbe_index] = val;
692 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
693 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
694 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
695 s->vbe_start_addr += x >> 1;
696 else
697 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr >>= 2;
699 }
700 break;
701 default:
702 break;
703 }
704 }
705 }
706 #endif
707
708 /* called for accesses between 0xa0000 and 0xc0000 */
709 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
710 {
711 VGAState *s = opaque;
712 int memory_map_mode, plane;
713 uint32_t ret;
714
715 /* convert to VGA memory offset */
716 memory_map_mode = (s->gr[6] >> 2) & 3;
717 addr &= 0x1ffff;
718 switch(memory_map_mode) {
719 case 0:
720 break;
721 case 1:
722 if (addr >= 0x10000)
723 return 0xff;
724 addr += s->bank_offset;
725 break;
726 case 2:
727 addr -= 0x10000;
728 if (addr >= 0x8000)
729 return 0xff;
730 break;
731 default:
732 case 3:
733 addr -= 0x18000;
734 if (addr >= 0x8000)
735 return 0xff;
736 break;
737 }
738
739 if (s->sr[4] & 0x08) {
740 /* chain 4 mode : simplest access */
741 ret = s->vram_ptr[addr];
742 } else if (s->gr[5] & 0x10) {
743 /* odd/even mode (aka text mode mapping) */
744 plane = (s->gr[4] & 2) | (addr & 1);
745 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
746 } else {
747 /* standard VGA latched access */
748 s->latch = ((uint32_t *)s->vram_ptr)[addr];
749
750 if (!(s->gr[5] & 0x08)) {
751 /* read mode 0 */
752 plane = s->gr[4];
753 ret = GET_PLANE(s->latch, plane);
754 } else {
755 /* read mode 1 */
756 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
757 ret |= ret >> 16;
758 ret |= ret >> 8;
759 ret = (~ret) & 0xff;
760 }
761 }
762 return ret;
763 }
764
765 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
766 {
767 uint32_t v;
768 #ifdef TARGET_WORDS_BIGENDIAN
769 v = vga_mem_readb(opaque, addr) << 8;
770 v |= vga_mem_readb(opaque, addr + 1);
771 #else
772 v = vga_mem_readb(opaque, addr);
773 v |= vga_mem_readb(opaque, addr + 1) << 8;
774 #endif
775 return v;
776 }
777
778 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
779 {
780 uint32_t v;
781 #ifdef TARGET_WORDS_BIGENDIAN
782 v = vga_mem_readb(opaque, addr) << 24;
783 v |= vga_mem_readb(opaque, addr + 1) << 16;
784 v |= vga_mem_readb(opaque, addr + 2) << 8;
785 v |= vga_mem_readb(opaque, addr + 3);
786 #else
787 v = vga_mem_readb(opaque, addr);
788 v |= vga_mem_readb(opaque, addr + 1) << 8;
789 v |= vga_mem_readb(opaque, addr + 2) << 16;
790 v |= vga_mem_readb(opaque, addr + 3) << 24;
791 #endif
792 return v;
793 }
794
795 /* called for accesses between 0xa0000 and 0xc0000 */
796 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
797 {
798 VGAState *s = opaque;
799 int memory_map_mode, plane, write_mode, b, func_select, mask;
800 uint32_t write_mask, bit_mask, set_mask;
801
802 #ifdef DEBUG_VGA_MEM
803 printf("vga: [0x%x] = 0x%02x\n", addr, val);
804 #endif
805 /* convert to VGA memory offset */
806 memory_map_mode = (s->gr[6] >> 2) & 3;
807 addr &= 0x1ffff;
808 switch(memory_map_mode) {
809 case 0:
810 break;
811 case 1:
812 if (addr >= 0x10000)
813 return;
814 addr += s->bank_offset;
815 break;
816 case 2:
817 addr -= 0x10000;
818 if (addr >= 0x8000)
819 return;
820 break;
821 default:
822 case 3:
823 addr -= 0x18000;
824 if (addr >= 0x8000)
825 return;
826 break;
827 }
828
829 if (s->sr[4] & 0x08) {
830 /* chain 4 mode : simplest access */
831 plane = addr & 3;
832 mask = (1 << plane);
833 if (s->sr[2] & mask) {
834 s->vram_ptr[addr] = val;
835 #ifdef DEBUG_VGA_MEM
836 printf("vga: chain4: [0x%x]\n", addr);
837 #endif
838 s->plane_updated |= mask; /* only used to detect font change */
839 cpu_physical_memory_set_dirty(s->vram_offset + addr);
840 }
841 } else if (s->gr[5] & 0x10) {
842 /* odd/even mode (aka text mode mapping) */
843 plane = (s->gr[4] & 2) | (addr & 1);
844 mask = (1 << plane);
845 if (s->sr[2] & mask) {
846 addr = ((addr & ~1) << 1) | plane;
847 s->vram_ptr[addr] = val;
848 #ifdef DEBUG_VGA_MEM
849 printf("vga: odd/even: [0x%x]\n", addr);
850 #endif
851 s->plane_updated |= mask; /* only used to detect font change */
852 cpu_physical_memory_set_dirty(s->vram_offset + addr);
853 }
854 } else {
855 /* standard VGA latched access */
856 write_mode = s->gr[5] & 3;
857 switch(write_mode) {
858 default:
859 case 0:
860 /* rotate */
861 b = s->gr[3] & 7;
862 val = ((val >> b) | (val << (8 - b))) & 0xff;
863 val |= val << 8;
864 val |= val << 16;
865
866 /* apply set/reset mask */
867 set_mask = mask16[s->gr[1]];
868 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
869 bit_mask = s->gr[8];
870 break;
871 case 1:
872 val = s->latch;
873 goto do_write;
874 case 2:
875 val = mask16[val & 0x0f];
876 bit_mask = s->gr[8];
877 break;
878 case 3:
879 /* rotate */
880 b = s->gr[3] & 7;
881 val = (val >> b) | (val << (8 - b));
882
883 bit_mask = s->gr[8] & val;
884 val = mask16[s->gr[0]];
885 break;
886 }
887
888 /* apply logical operation */
889 func_select = s->gr[3] >> 3;
890 switch(func_select) {
891 case 0:
892 default:
893 /* nothing to do */
894 break;
895 case 1:
896 /* and */
897 val &= s->latch;
898 break;
899 case 2:
900 /* or */
901 val |= s->latch;
902 break;
903 case 3:
904 /* xor */
905 val ^= s->latch;
906 break;
907 }
908
909 /* apply bit mask */
910 bit_mask |= bit_mask << 8;
911 bit_mask |= bit_mask << 16;
912 val = (val & bit_mask) | (s->latch & ~bit_mask);
913
914 do_write:
915 /* mask data according to sr[2] */
916 mask = s->sr[2];
917 s->plane_updated |= mask; /* only used to detect font change */
918 write_mask = mask16[mask];
919 ((uint32_t *)s->vram_ptr)[addr] =
920 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
921 (val & write_mask);
922 #ifdef DEBUG_VGA_MEM
923 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
924 addr * 4, write_mask, val);
925 #endif
926 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
927 }
928 }
929
930 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
931 {
932 #ifdef TARGET_WORDS_BIGENDIAN
933 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
934 vga_mem_writeb(opaque, addr + 1, val & 0xff);
935 #else
936 vga_mem_writeb(opaque, addr, val & 0xff);
937 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
938 #endif
939 }
940
941 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
942 {
943 #ifdef TARGET_WORDS_BIGENDIAN
944 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
945 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
946 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
947 vga_mem_writeb(opaque, addr + 3, val & 0xff);
948 #else
949 vga_mem_writeb(opaque, addr, val & 0xff);
950 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
951 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
952 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
953 #endif
954 }
955
956 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
957 const uint8_t *font_ptr, int h,
958 uint32_t fgcol, uint32_t bgcol);
959 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
960 const uint8_t *font_ptr, int h,
961 uint32_t fgcol, uint32_t bgcol, int dup9);
962 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
963 const uint8_t *s, int width);
964
965 #define DEPTH 8
966 #include "vga_template.h"
967
968 #define DEPTH 15
969 #include "vga_template.h"
970
971 #define BGR_FORMAT
972 #define DEPTH 15
973 #include "vga_template.h"
974
975 #define DEPTH 16
976 #include "vga_template.h"
977
978 #define BGR_FORMAT
979 #define DEPTH 16
980 #include "vga_template.h"
981
982 #define DEPTH 32
983 #include "vga_template.h"
984
985 #define BGR_FORMAT
986 #define DEPTH 32
987 #include "vga_template.h"
988
989 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
990 {
991 unsigned int col;
992 col = rgb_to_pixel8(r, g, b);
993 col |= col << 8;
994 col |= col << 16;
995 return col;
996 }
997
998 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
999 {
1000 unsigned int col;
1001 col = rgb_to_pixel15(r, g, b);
1002 col |= col << 16;
1003 return col;
1004 }
1005
1006 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1007 unsigned int b)
1008 {
1009 unsigned int col;
1010 col = rgb_to_pixel15bgr(r, g, b);
1011 col |= col << 16;
1012 return col;
1013 }
1014
1015 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1016 {
1017 unsigned int col;
1018 col = rgb_to_pixel16(r, g, b);
1019 col |= col << 16;
1020 return col;
1021 }
1022
1023 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025 {
1026 unsigned int col;
1027 col = rgb_to_pixel16bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030 }
1031
1032 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1033 {
1034 unsigned int col;
1035 col = rgb_to_pixel32(r, g, b);
1036 return col;
1037 }
1038
1039 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1040 {
1041 unsigned int col;
1042 col = rgb_to_pixel32bgr(r, g, b);
1043 return col;
1044 }
1045
1046 /* return true if the palette was modified */
1047 static int update_palette16(VGAState *s)
1048 {
1049 int full_update, i;
1050 uint32_t v, col, *palette;
1051
1052 full_update = 0;
1053 palette = s->last_palette;
1054 for(i = 0; i < 16; i++) {
1055 v = s->ar[i];
1056 if (s->ar[0x10] & 0x80)
1057 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1058 else
1059 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1060 v = v * 3;
1061 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1062 c6_to_8(s->palette[v + 1]),
1063 c6_to_8(s->palette[v + 2]));
1064 if (col != palette[i]) {
1065 full_update = 1;
1066 palette[i] = col;
1067 }
1068 }
1069 return full_update;
1070 }
1071
1072 /* return true if the palette was modified */
1073 static int update_palette256(VGAState *s)
1074 {
1075 int full_update, i;
1076 uint32_t v, col, *palette;
1077
1078 full_update = 0;
1079 palette = s->last_palette;
1080 v = 0;
1081 for(i = 0; i < 256; i++) {
1082 if (s->dac_8bit) {
1083 col = s->rgb_to_pixel(s->palette[v],
1084 s->palette[v + 1],
1085 s->palette[v + 2]);
1086 } else {
1087 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1088 c6_to_8(s->palette[v + 1]),
1089 c6_to_8(s->palette[v + 2]));
1090 }
1091 if (col != palette[i]) {
1092 full_update = 1;
1093 palette[i] = col;
1094 }
1095 v += 3;
1096 }
1097 return full_update;
1098 }
1099
1100 static void vga_get_offsets(VGAState *s,
1101 uint32_t *pline_offset,
1102 uint32_t *pstart_addr,
1103 uint32_t *pline_compare)
1104 {
1105 uint32_t start_addr, line_offset, line_compare;
1106 #ifdef CONFIG_BOCHS_VBE
1107 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1108 line_offset = s->vbe_line_offset;
1109 start_addr = s->vbe_start_addr;
1110 line_compare = 65535;
1111 } else
1112 #endif
1113 {
1114 /* compute line_offset in bytes */
1115 line_offset = s->cr[0x13];
1116 line_offset <<= 3;
1117
1118 /* starting address */
1119 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1120
1121 /* line compare */
1122 line_compare = s->cr[0x18] |
1123 ((s->cr[0x07] & 0x10) << 4) |
1124 ((s->cr[0x09] & 0x40) << 3);
1125 }
1126 *pline_offset = line_offset;
1127 *pstart_addr = start_addr;
1128 *pline_compare = line_compare;
1129 }
1130
1131 /* update start_addr and line_offset. Return TRUE if modified */
1132 static int update_basic_params(VGAState *s)
1133 {
1134 int full_update;
1135 uint32_t start_addr, line_offset, line_compare;
1136
1137 full_update = 0;
1138
1139 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1140
1141 if (line_offset != s->line_offset ||
1142 start_addr != s->start_addr ||
1143 line_compare != s->line_compare) {
1144 s->line_offset = line_offset;
1145 s->start_addr = start_addr;
1146 s->line_compare = line_compare;
1147 full_update = 1;
1148 }
1149 return full_update;
1150 }
1151
1152 #define NB_DEPTHS 7
1153
1154 static inline int get_depth_index(DisplayState *s)
1155 {
1156 switch(ds_get_bits_per_pixel(s)) {
1157 default:
1158 case 8:
1159 return 0;
1160 case 15:
1161 if (s->bgr)
1162 return 5;
1163 else
1164 return 1;
1165 case 16:
1166 if (s->bgr)
1167 return 6;
1168 else
1169 return 2;
1170 case 32:
1171 if (s->bgr)
1172 return 4;
1173 else
1174 return 3;
1175 }
1176 }
1177
1178 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1179 vga_draw_glyph8_8,
1180 vga_draw_glyph8_16,
1181 vga_draw_glyph8_16,
1182 vga_draw_glyph8_32,
1183 vga_draw_glyph8_32,
1184 vga_draw_glyph8_16,
1185 vga_draw_glyph8_16,
1186 };
1187
1188 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1189 vga_draw_glyph16_8,
1190 vga_draw_glyph16_16,
1191 vga_draw_glyph16_16,
1192 vga_draw_glyph16_32,
1193 vga_draw_glyph16_32,
1194 vga_draw_glyph16_16,
1195 vga_draw_glyph16_16,
1196 };
1197
1198 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1199 vga_draw_glyph9_8,
1200 vga_draw_glyph9_16,
1201 vga_draw_glyph9_16,
1202 vga_draw_glyph9_32,
1203 vga_draw_glyph9_32,
1204 vga_draw_glyph9_16,
1205 vga_draw_glyph9_16,
1206 };
1207
1208 static const uint8_t cursor_glyph[32 * 4] = {
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1219 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1220 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1221 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1225 };
1226
1227 static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
1228 int *pcwidth, int *pcheight)
1229 {
1230 int width, cwidth, height, cheight;
1231
1232 /* total width & height */
1233 cheight = (s->cr[9] & 0x1f) + 1;
1234 cwidth = 8;
1235 if (!(s->sr[1] & 0x01))
1236 cwidth = 9;
1237 if (s->sr[1] & 0x08)
1238 cwidth = 16; /* NOTE: no 18 pixel wide */
1239 width = (s->cr[0x01] + 1);
1240 if (s->cr[0x06] == 100) {
1241 /* ugly hack for CGA 160x100x16 - explain me the logic */
1242 height = 100;
1243 } else {
1244 height = s->cr[0x12] |
1245 ((s->cr[0x07] & 0x02) << 7) |
1246 ((s->cr[0x07] & 0x40) << 3);
1247 height = (height + 1) / cheight;
1248 }
1249
1250 *pwidth = width;
1251 *pheight = height;
1252 *pcwidth = cwidth;
1253 *pcheight = cheight;
1254 }
1255
1256 /*
1257 * Text mode update
1258 * Missing:
1259 * - double scan
1260 * - double width
1261 * - underline
1262 * - flashing
1263 */
1264 static void vga_draw_text(VGAState *s, int full_update)
1265 {
1266 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1267 int cx_min, cx_max, linesize, x_incr;
1268 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1269 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1270 const uint8_t *font_ptr, *font_base[2];
1271 int dup9, line_offset, depth_index;
1272 uint32_t *palette;
1273 uint32_t *ch_attr_ptr;
1274 vga_draw_glyph8_func *vga_draw_glyph8;
1275 vga_draw_glyph9_func *vga_draw_glyph9;
1276
1277 vga_dirty_log_stop(s);
1278
1279 full_update |= update_palette16(s);
1280 palette = s->last_palette;
1281
1282 /* compute font data address (in plane 2) */
1283 v = s->sr[3];
1284 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1285 if (offset != s->font_offsets[0]) {
1286 s->font_offsets[0] = offset;
1287 full_update = 1;
1288 }
1289 font_base[0] = s->vram_ptr + offset;
1290
1291 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1292 font_base[1] = s->vram_ptr + offset;
1293 if (offset != s->font_offsets[1]) {
1294 s->font_offsets[1] = offset;
1295 full_update = 1;
1296 }
1297 if (s->plane_updated & (1 << 2)) {
1298 /* if the plane 2 was modified since the last display, it
1299 indicates the font may have been modified */
1300 s->plane_updated = 0;
1301 full_update = 1;
1302 }
1303 full_update |= update_basic_params(s);
1304
1305 line_offset = s->line_offset;
1306 s1 = s->vram_ptr + (s->start_addr * 4);
1307
1308 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1309 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1310 if ((height * width) > CH_ATTR_SIZE) {
1311 /* better than nothing: exit if transient size is too big */
1312 return;
1313 }
1314
1315 if (width != s->last_width || height != s->last_height ||
1316 cw != s->last_cw || cheight != s->last_ch) {
1317 s->last_scr_width = width * cw;
1318 s->last_scr_height = height * cheight;
1319 qemu_console_resize(s->console, s->last_scr_width, s->last_scr_height);
1320 s->last_width = width;
1321 s->last_height = height;
1322 s->last_ch = cheight;
1323 s->last_cw = cw;
1324 full_update = 1;
1325 }
1326 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1327 if (cursor_offset != s->cursor_offset ||
1328 s->cr[0xa] != s->cursor_start ||
1329 s->cr[0xb] != s->cursor_end) {
1330 /* if the cursor position changed, we update the old and new
1331 chars */
1332 if (s->cursor_offset < CH_ATTR_SIZE)
1333 s->last_ch_attr[s->cursor_offset] = -1;
1334 if (cursor_offset < CH_ATTR_SIZE)
1335 s->last_ch_attr[cursor_offset] = -1;
1336 s->cursor_offset = cursor_offset;
1337 s->cursor_start = s->cr[0xa];
1338 s->cursor_end = s->cr[0xb];
1339 }
1340 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1341
1342 depth_index = get_depth_index(s->ds);
1343 if (cw == 16)
1344 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1345 else
1346 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1347 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1348
1349 dest = ds_get_data(s->ds);
1350 linesize = ds_get_linesize(s->ds);
1351 ch_attr_ptr = s->last_ch_attr;
1352 for(cy = 0; cy < height; cy++) {
1353 d1 = dest;
1354 src = s1;
1355 cx_min = width;
1356 cx_max = -1;
1357 for(cx = 0; cx < width; cx++) {
1358 ch_attr = *(uint16_t *)src;
1359 if (full_update || ch_attr != *ch_attr_ptr) {
1360 if (cx < cx_min)
1361 cx_min = cx;
1362 if (cx > cx_max)
1363 cx_max = cx;
1364 *ch_attr_ptr = ch_attr;
1365 #ifdef WORDS_BIGENDIAN
1366 ch = ch_attr >> 8;
1367 cattr = ch_attr & 0xff;
1368 #else
1369 ch = ch_attr & 0xff;
1370 cattr = ch_attr >> 8;
1371 #endif
1372 font_ptr = font_base[(cattr >> 3) & 1];
1373 font_ptr += 32 * 4 * ch;
1374 bgcol = palette[cattr >> 4];
1375 fgcol = palette[cattr & 0x0f];
1376 if (cw != 9) {
1377 vga_draw_glyph8(d1, linesize,
1378 font_ptr, cheight, fgcol, bgcol);
1379 } else {
1380 dup9 = 0;
1381 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1382 dup9 = 1;
1383 vga_draw_glyph9(d1, linesize,
1384 font_ptr, cheight, fgcol, bgcol, dup9);
1385 }
1386 if (src == cursor_ptr &&
1387 !(s->cr[0x0a] & 0x20)) {
1388 int line_start, line_last, h;
1389 /* draw the cursor */
1390 line_start = s->cr[0x0a] & 0x1f;
1391 line_last = s->cr[0x0b] & 0x1f;
1392 /* XXX: check that */
1393 if (line_last > cheight - 1)
1394 line_last = cheight - 1;
1395 if (line_last >= line_start && line_start < cheight) {
1396 h = line_last - line_start + 1;
1397 d = d1 + linesize * line_start;
1398 if (cw != 9) {
1399 vga_draw_glyph8(d, linesize,
1400 cursor_glyph, h, fgcol, bgcol);
1401 } else {
1402 vga_draw_glyph9(d, linesize,
1403 cursor_glyph, h, fgcol, bgcol, 1);
1404 }
1405 }
1406 }
1407 }
1408 d1 += x_incr;
1409 src += 4;
1410 ch_attr_ptr++;
1411 }
1412 if (cx_max != -1) {
1413 dpy_update(s->ds, cx_min * cw, cy * cheight,
1414 (cx_max - cx_min + 1) * cw, cheight);
1415 }
1416 dest += linesize * cheight;
1417 s1 += line_offset;
1418 }
1419 }
1420
1421 enum {
1422 VGA_DRAW_LINE2,
1423 VGA_DRAW_LINE2D2,
1424 VGA_DRAW_LINE4,
1425 VGA_DRAW_LINE4D2,
1426 VGA_DRAW_LINE8D2,
1427 VGA_DRAW_LINE8,
1428 VGA_DRAW_LINE15,
1429 VGA_DRAW_LINE16,
1430 VGA_DRAW_LINE24,
1431 VGA_DRAW_LINE32,
1432 VGA_DRAW_LINE_NB,
1433 };
1434
1435 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1436 vga_draw_line2_8,
1437 vga_draw_line2_16,
1438 vga_draw_line2_16,
1439 vga_draw_line2_32,
1440 vga_draw_line2_32,
1441 vga_draw_line2_16,
1442 vga_draw_line2_16,
1443
1444 vga_draw_line2d2_8,
1445 vga_draw_line2d2_16,
1446 vga_draw_line2d2_16,
1447 vga_draw_line2d2_32,
1448 vga_draw_line2d2_32,
1449 vga_draw_line2d2_16,
1450 vga_draw_line2d2_16,
1451
1452 vga_draw_line4_8,
1453 vga_draw_line4_16,
1454 vga_draw_line4_16,
1455 vga_draw_line4_32,
1456 vga_draw_line4_32,
1457 vga_draw_line4_16,
1458 vga_draw_line4_16,
1459
1460 vga_draw_line4d2_8,
1461 vga_draw_line4d2_16,
1462 vga_draw_line4d2_16,
1463 vga_draw_line4d2_32,
1464 vga_draw_line4d2_32,
1465 vga_draw_line4d2_16,
1466 vga_draw_line4d2_16,
1467
1468 vga_draw_line8d2_8,
1469 vga_draw_line8d2_16,
1470 vga_draw_line8d2_16,
1471 vga_draw_line8d2_32,
1472 vga_draw_line8d2_32,
1473 vga_draw_line8d2_16,
1474 vga_draw_line8d2_16,
1475
1476 vga_draw_line8_8,
1477 vga_draw_line8_16,
1478 vga_draw_line8_16,
1479 vga_draw_line8_32,
1480 vga_draw_line8_32,
1481 vga_draw_line8_16,
1482 vga_draw_line8_16,
1483
1484 vga_draw_line15_8,
1485 vga_draw_line15_15,
1486 vga_draw_line15_16,
1487 vga_draw_line15_32,
1488 vga_draw_line15_32bgr,
1489 vga_draw_line15_15bgr,
1490 vga_draw_line15_16bgr,
1491
1492 vga_draw_line16_8,
1493 vga_draw_line16_15,
1494 vga_draw_line16_16,
1495 vga_draw_line16_32,
1496 vga_draw_line16_32bgr,
1497 vga_draw_line16_15bgr,
1498 vga_draw_line16_16bgr,
1499
1500 vga_draw_line24_8,
1501 vga_draw_line24_15,
1502 vga_draw_line24_16,
1503 vga_draw_line24_32,
1504 vga_draw_line24_32bgr,
1505 vga_draw_line24_15bgr,
1506 vga_draw_line24_16bgr,
1507
1508 vga_draw_line32_8,
1509 vga_draw_line32_15,
1510 vga_draw_line32_16,
1511 vga_draw_line32_32,
1512 vga_draw_line32_32bgr,
1513 vga_draw_line32_15bgr,
1514 vga_draw_line32_16bgr,
1515 };
1516
1517 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1518
1519 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1520 rgb_to_pixel8_dup,
1521 rgb_to_pixel15_dup,
1522 rgb_to_pixel16_dup,
1523 rgb_to_pixel32_dup,
1524 rgb_to_pixel32bgr_dup,
1525 rgb_to_pixel15bgr_dup,
1526 rgb_to_pixel16bgr_dup,
1527 };
1528
1529 static int vga_get_bpp(VGAState *s)
1530 {
1531 int ret;
1532 #ifdef CONFIG_BOCHS_VBE
1533 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1534 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1535 } else
1536 #endif
1537 {
1538 ret = 0;
1539 }
1540 return ret;
1541 }
1542
1543 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1544 {
1545 int width, height;
1546
1547 #ifdef CONFIG_BOCHS_VBE
1548 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1549 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1550 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1551 } else
1552 #endif
1553 {
1554 width = (s->cr[0x01] + 1) * 8;
1555 height = s->cr[0x12] |
1556 ((s->cr[0x07] & 0x02) << 7) |
1557 ((s->cr[0x07] & 0x40) << 3);
1558 height = (height + 1);
1559 }
1560 *pwidth = width;
1561 *pheight = height;
1562 }
1563
1564 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1565 {
1566 int y;
1567 if (y1 >= VGA_MAX_HEIGHT)
1568 return;
1569 if (y2 >= VGA_MAX_HEIGHT)
1570 y2 = VGA_MAX_HEIGHT;
1571 for(y = y1; y < y2; y++) {
1572 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1573 }
1574 }
1575
1576 static void vga_sync_dirty_bitmap(VGAState *s)
1577 {
1578 if (s->map_addr)
1579 cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
1580
1581 if (s->lfb_vram_mapped) {
1582 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
1583 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
1584 }
1585 vga_dirty_log_start(s);
1586 }
1587
1588 /*
1589 * graphic modes
1590 */
1591 static void vga_draw_graphic(VGAState *s, int full_update)
1592 {
1593 int y1, y, update, linesize, y_start, double_scan, mask;
1594 int width, height, shift_control, line_offset, bwidth, bits;
1595 int disp_width, multi_scan, multi_run;
1596 uint8_t *d;
1597 uint32_t v, addr1, addr;
1598 long page0, page1, page_min, page_max;
1599 vga_draw_line_func *vga_draw_line;
1600
1601 full_update |= update_basic_params(s);
1602
1603 if (!full_update)
1604 vga_sync_dirty_bitmap(s);
1605
1606 s->get_resolution(s, &width, &height);
1607 disp_width = width;
1608
1609 shift_control = (s->gr[0x05] >> 5) & 3;
1610 double_scan = (s->cr[0x09] >> 7);
1611 if (shift_control != 1) {
1612 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1613 } else {
1614 /* in CGA modes, multi_scan is ignored */
1615 /* XXX: is it correct ? */
1616 multi_scan = double_scan;
1617 }
1618 multi_run = multi_scan;
1619 if (shift_control != s->shift_control ||
1620 double_scan != s->double_scan) {
1621 full_update = 1;
1622 s->shift_control = shift_control;
1623 s->double_scan = double_scan;
1624 }
1625
1626 if (shift_control == 0) {
1627 full_update |= update_palette16(s);
1628 if (s->sr[0x01] & 8) {
1629 v = VGA_DRAW_LINE4D2;
1630 disp_width <<= 1;
1631 } else {
1632 v = VGA_DRAW_LINE4;
1633 }
1634 bits = 4;
1635 } else if (shift_control == 1) {
1636 full_update |= update_palette16(s);
1637 if (s->sr[0x01] & 8) {
1638 v = VGA_DRAW_LINE2D2;
1639 disp_width <<= 1;
1640 } else {
1641 v = VGA_DRAW_LINE2;
1642 }
1643 bits = 4;
1644 } else {
1645 switch(s->get_bpp(s)) {
1646 default:
1647 case 0:
1648 full_update |= update_palette256(s);
1649 v = VGA_DRAW_LINE8D2;
1650 bits = 4;
1651 break;
1652 case 8:
1653 full_update |= update_palette256(s);
1654 v = VGA_DRAW_LINE8;
1655 bits = 8;
1656 break;
1657 case 15:
1658 v = VGA_DRAW_LINE15;
1659 bits = 16;
1660 break;
1661 case 16:
1662 v = VGA_DRAW_LINE16;
1663 bits = 16;
1664 break;
1665 case 24:
1666 v = VGA_DRAW_LINE24;
1667 bits = 24;
1668 break;
1669 case 32:
1670 v = VGA_DRAW_LINE32;
1671 bits = 32;
1672 break;
1673 }
1674 }
1675 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1676
1677 if (disp_width != s->last_width ||
1678 height != s->last_height) {
1679 qemu_console_resize(s->console, disp_width, height);
1680 s->last_scr_width = disp_width;
1681 s->last_scr_height = height;
1682 s->last_width = disp_width;
1683 s->last_height = height;
1684 full_update = 1;
1685 }
1686 if (s->cursor_invalidate)
1687 s->cursor_invalidate(s);
1688
1689 line_offset = s->line_offset;
1690 #if 0
1691 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1692 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1693 #endif
1694 addr1 = (s->start_addr * 4);
1695 bwidth = (width * bits + 7) / 8;
1696 y_start = -1;
1697 page_min = 0x7fffffff;
1698 page_max = -1;
1699 d = ds_get_data(s->ds);
1700 linesize = ds_get_linesize(s->ds);
1701 y1 = 0;
1702 for(y = 0; y < height; y++) {
1703 addr = addr1;
1704 if (!(s->cr[0x17] & 1)) {
1705 int shift;
1706 /* CGA compatibility handling */
1707 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1708 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1709 }
1710 if (!(s->cr[0x17] & 2)) {
1711 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1712 }
1713 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1714 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1715 update = full_update |
1716 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1717 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1718 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1719 /* if wide line, can use another page */
1720 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1721 VGA_DIRTY_FLAG);
1722 }
1723 /* explicit invalidation for the hardware cursor */
1724 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1725 if (update) {
1726 if (y_start < 0)
1727 y_start = y;
1728 if (page0 < page_min)
1729 page_min = page0;
1730 if (page1 > page_max)
1731 page_max = page1;
1732 vga_draw_line(s, d, s->vram_ptr + addr, width);
1733 if (s->cursor_draw_line)
1734 s->cursor_draw_line(s, d, y);
1735 } else {
1736 if (y_start >= 0) {
1737 /* flush to display */
1738 dpy_update(s->ds, 0, y_start,
1739 disp_width, y - y_start);
1740 y_start = -1;
1741 }
1742 }
1743 if (!multi_run) {
1744 mask = (s->cr[0x17] & 3) ^ 3;
1745 if ((y1 & mask) == mask)
1746 addr1 += line_offset;
1747 y1++;
1748 multi_run = multi_scan;
1749 } else {
1750 multi_run--;
1751 }
1752 /* line compare acts on the displayed lines */
1753 if (y == s->line_compare)
1754 addr1 = 0;
1755 d += linesize;
1756 }
1757 if (y_start >= 0) {
1758 /* flush to display */
1759 dpy_update(s->ds, 0, y_start,
1760 disp_width, y - y_start);
1761 }
1762 /* reset modified pages */
1763 if (page_max != -1) {
1764 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1765 VGA_DIRTY_FLAG);
1766 }
1767 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1768 }
1769
1770 static void vga_draw_blank(VGAState *s, int full_update)
1771 {
1772 int i, w, val;
1773 uint8_t *d;
1774
1775 if (!full_update)
1776 return;
1777 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1778 return;
1779 vga_dirty_log_stop(s);
1780
1781 if (ds_get_bits_per_pixel(s->ds) == 8)
1782 val = s->rgb_to_pixel(0, 0, 0);
1783 else
1784 val = 0;
1785 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1786 d = ds_get_data(s->ds);
1787 for(i = 0; i < s->last_scr_height; i++) {
1788 memset(d, val, w);
1789 d += ds_get_linesize(s->ds);
1790 }
1791 dpy_update(s->ds, 0, 0,
1792 s->last_scr_width, s->last_scr_height);
1793 }
1794
1795 #define GMODE_TEXT 0
1796 #define GMODE_GRAPH 1
1797 #define GMODE_BLANK 2
1798
1799 static void vga_update_display(void *opaque)
1800 {
1801 VGAState *s = (VGAState *)opaque;
1802 int full_update, graphic_mode;
1803
1804 if (ds_get_bits_per_pixel(s->ds) == 0) {
1805 /* nothing to do */
1806 } else {
1807 s->rgb_to_pixel =
1808 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1809
1810 full_update = 0;
1811 if (!(s->ar_index & 0x20)) {
1812 graphic_mode = GMODE_BLANK;
1813 } else {
1814 graphic_mode = s->gr[6] & 1;
1815 }
1816 if (graphic_mode != s->graphic_mode) {
1817 s->graphic_mode = graphic_mode;
1818 full_update = 1;
1819 }
1820 switch(graphic_mode) {
1821 case GMODE_TEXT:
1822 vga_draw_text(s, full_update);
1823 break;
1824 case GMODE_GRAPH:
1825 #ifdef TARGET_IA64
1826 full_update = 1;
1827 #endif
1828 vga_draw_graphic(s, full_update);
1829 break;
1830 case GMODE_BLANK:
1831 default:
1832 vga_draw_blank(s, full_update);
1833 break;
1834 }
1835 }
1836 }
1837
1838 /* force a full display refresh */
1839 static void vga_invalidate_display(void *opaque)
1840 {
1841 VGAState *s = (VGAState *)opaque;
1842
1843 s->last_width = -1;
1844 s->last_height = -1;
1845 }
1846
1847 void vga_reset(void *opaque)
1848 {
1849 VGAState *s = (VGAState *) opaque;
1850
1851 s->lfb_addr = 0;
1852 s->lfb_end = 0;
1853 s->map_addr = 0;
1854 s->map_end = 0;
1855 s->lfb_vram_mapped = 0;
1856 s->bios_offset = 0;
1857 s->bios_size = 0;
1858 s->sr_index = 0;
1859 memset(s->sr, '\0', sizeof(s->sr));
1860 s->gr_index = 0;
1861 memset(s->gr, '\0', sizeof(s->gr));
1862 s->ar_index = 0;
1863 memset(s->ar, '\0', sizeof(s->ar));
1864 s->ar_flip_flop = 0;
1865 s->cr_index = 0;
1866 memset(s->cr, '\0', sizeof(s->cr));
1867 s->msr = 0;
1868 s->fcr = 0;
1869 s->st00 = 0;
1870 s->st01 = 0;
1871 s->dac_state = 0;
1872 s->dac_sub_index = 0;
1873 s->dac_read_index = 0;
1874 s->dac_write_index = 0;
1875 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1876 s->dac_8bit = 0;
1877 memset(s->palette, '\0', sizeof(s->palette));
1878 s->bank_offset = 0;
1879 #ifdef CONFIG_BOCHS_VBE
1880 s->vbe_index = 0;
1881 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1882 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1883 s->vbe_start_addr = 0;
1884 s->vbe_line_offset = 0;
1885 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1886 #endif
1887 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1888 s->graphic_mode = -1; /* force full update */
1889 s->shift_control = 0;
1890 s->double_scan = 0;
1891 s->line_offset = 0;
1892 s->line_compare = 0;
1893 s->start_addr = 0;
1894 s->plane_updated = 0;
1895 s->last_cw = 0;
1896 s->last_ch = 0;
1897 s->last_width = 0;
1898 s->last_height = 0;
1899 s->last_scr_width = 0;
1900 s->last_scr_height = 0;
1901 s->cursor_start = 0;
1902 s->cursor_end = 0;
1903 s->cursor_offset = 0;
1904 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1905 memset(s->last_palette, '\0', sizeof(s->last_palette));
1906 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1907 switch (vga_retrace_method) {
1908 case VGA_RETRACE_DUMB:
1909 break;
1910 case VGA_RETRACE_PRECISE:
1911 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1912 break;
1913 }
1914 }
1915
1916 #define TEXTMODE_X(x) ((x) % width)
1917 #define TEXTMODE_Y(x) ((x) / width)
1918 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1919 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1920 /* relay text rendering to the display driver
1921 * instead of doing a full vga_update_display() */
1922 static void vga_update_text(void *opaque, console_ch_t *chardata)
1923 {
1924 VGAState *s = (VGAState *) opaque;
1925 int graphic_mode, i, cursor_offset, cursor_visible;
1926 int cw, cheight, width, height, size, c_min, c_max;
1927 uint32_t *src;
1928 console_ch_t *dst, val;
1929 char msg_buffer[80];
1930 int full_update = 0;
1931
1932 if (!(s->ar_index & 0x20)) {
1933 graphic_mode = GMODE_BLANK;
1934 } else {
1935 graphic_mode = s->gr[6] & 1;
1936 }
1937 if (graphic_mode != s->graphic_mode) {
1938 s->graphic_mode = graphic_mode;
1939 full_update = 1;
1940 }
1941 if (s->last_width == -1) {
1942 s->last_width = 0;
1943 full_update = 1;
1944 }
1945
1946 switch (graphic_mode) {
1947 case GMODE_TEXT:
1948 /* TODO: update palette */
1949 full_update |= update_basic_params(s);
1950
1951 /* total width & height */
1952 cheight = (s->cr[9] & 0x1f) + 1;
1953 cw = 8;
1954 if (!(s->sr[1] & 0x01))
1955 cw = 9;
1956 if (s->sr[1] & 0x08)
1957 cw = 16; /* NOTE: no 18 pixel wide */
1958 width = (s->cr[0x01] + 1);
1959 if (s->cr[0x06] == 100) {
1960 /* ugly hack for CGA 160x100x16 - explain me the logic */
1961 height = 100;
1962 } else {
1963 height = s->cr[0x12] |
1964 ((s->cr[0x07] & 0x02) << 7) |
1965 ((s->cr[0x07] & 0x40) << 3);
1966 height = (height + 1) / cheight;
1967 }
1968
1969 size = (height * width);
1970 if (size > CH_ATTR_SIZE) {
1971 if (!full_update)
1972 return;
1973
1974 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1975 width, height);
1976 break;
1977 }
1978
1979 if (width != s->last_width || height != s->last_height ||
1980 cw != s->last_cw || cheight != s->last_ch) {
1981 s->last_scr_width = width * cw;
1982 s->last_scr_height = height * cheight;
1983 qemu_console_resize(s->console, width, height);
1984 s->last_width = width;
1985 s->last_height = height;
1986 s->last_ch = cheight;
1987 s->last_cw = cw;
1988 full_update = 1;
1989 }
1990
1991 /* Update "hardware" cursor */
1992 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1993 if (cursor_offset != s->cursor_offset ||
1994 s->cr[0xa] != s->cursor_start ||
1995 s->cr[0xb] != s->cursor_end || full_update) {
1996 cursor_visible = !(s->cr[0xa] & 0x20);
1997 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1998 dpy_cursor(s->ds,
1999 TEXTMODE_X(cursor_offset),
2000 TEXTMODE_Y(cursor_offset));
2001 else
2002 dpy_cursor(s->ds, -1, -1);
2003 s->cursor_offset = cursor_offset;
2004 s->cursor_start = s->cr[0xa];
2005 s->cursor_end = s->cr[0xb];
2006 }
2007
2008 src = (uint32_t *) s->vram_ptr + s->start_addr;
2009 dst = chardata;
2010
2011 if (full_update) {
2012 for (i = 0; i < size; src ++, dst ++, i ++)
2013 console_write_ch(dst, VMEM2CHTYPE(*src));
2014
2015 dpy_update(s->ds, 0, 0, width, height);
2016 } else {
2017 c_max = 0;
2018
2019 for (i = 0; i < size; src ++, dst ++, i ++) {
2020 console_write_ch(&val, VMEM2CHTYPE(*src));
2021 if (*dst != val) {
2022 *dst = val;
2023 c_max = i;
2024 break;
2025 }
2026 }
2027 c_min = i;
2028 for (; i < size; src ++, dst ++, i ++) {
2029 console_write_ch(&val, VMEM2CHTYPE(*src));
2030 if (*dst != val) {
2031 *dst = val;
2032 c_max = i;
2033 }
2034 }
2035
2036 if (c_min <= c_max) {
2037 i = TEXTMODE_Y(c_min);
2038 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2039 }
2040 }
2041
2042 return;
2043 case GMODE_GRAPH:
2044 if (!full_update)
2045 return;
2046
2047 s->get_resolution(s, &width, &height);
2048 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2049 width, height);
2050 break;
2051 case GMODE_BLANK:
2052 default:
2053 if (!full_update)
2054 return;
2055
2056 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2057 break;
2058 }
2059
2060 /* Display a message */
2061 s->last_width = 60;
2062 s->last_height = height = 3;
2063 dpy_cursor(s->ds, -1, -1);
2064 qemu_console_resize(s->console, s->last_width, height);
2065
2066 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2067 console_write_ch(dst ++, ' ');
2068
2069 size = strlen(msg_buffer);
2070 width = (s->last_width - size) / 2;
2071 dst = chardata + s->last_width + width;
2072 for (i = 0; i < size; i ++)
2073 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2074
2075 dpy_update(s->ds, 0, 0, s->last_width, height);
2076 }
2077
2078 static CPUReadMemoryFunc *vga_mem_read[3] = {
2079 vga_mem_readb,
2080 vga_mem_readw,
2081 vga_mem_readl,
2082 };
2083
2084 static CPUWriteMemoryFunc *vga_mem_write[3] = {
2085 vga_mem_writeb,
2086 vga_mem_writew,
2087 vga_mem_writel,
2088 };
2089
2090 static void vga_save(QEMUFile *f, void *opaque)
2091 {
2092 VGAState *s = opaque;
2093 int i;
2094
2095 if (s->pci_dev)
2096 pci_device_save(s->pci_dev, f);
2097
2098 qemu_put_be32s(f, &s->latch);
2099 qemu_put_8s(f, &s->sr_index);
2100 qemu_put_buffer(f, s->sr, 8);
2101 qemu_put_8s(f, &s->gr_index);
2102 qemu_put_buffer(f, s->gr, 16);
2103 qemu_put_8s(f, &s->ar_index);
2104 qemu_put_buffer(f, s->ar, 21);
2105 qemu_put_be32(f, s->ar_flip_flop);
2106 qemu_put_8s(f, &s->cr_index);
2107 qemu_put_buffer(f, s->cr, 256);
2108 qemu_put_8s(f, &s->msr);
2109 qemu_put_8s(f, &s->fcr);
2110 qemu_put_byte(f, s->st00);
2111 qemu_put_8s(f, &s->st01);
2112
2113 qemu_put_8s(f, &s->dac_state);
2114 qemu_put_8s(f, &s->dac_sub_index);
2115 qemu_put_8s(f, &s->dac_read_index);
2116 qemu_put_8s(f, &s->dac_write_index);
2117 qemu_put_buffer(f, s->dac_cache, 3);
2118 qemu_put_buffer(f, s->palette, 768);
2119
2120 qemu_put_be32(f, s->bank_offset);
2121 #ifdef CONFIG_BOCHS_VBE
2122 qemu_put_byte(f, 1);
2123 qemu_put_be16s(f, &s->vbe_index);
2124 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2125 qemu_put_be16s(f, &s->vbe_regs[i]);
2126 qemu_put_be32s(f, &s->vbe_start_addr);
2127 qemu_put_be32s(f, &s->vbe_line_offset);
2128 qemu_put_be32s(f, &s->vbe_bank_mask);
2129 #else
2130 qemu_put_byte(f, 0);
2131 #endif
2132 }
2133
2134 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2135 {
2136 VGAState *s = opaque;
2137 int is_vbe, i, ret;
2138
2139 if (version_id > 2)
2140 return -EINVAL;
2141
2142 if (s->pci_dev && version_id >= 2) {
2143 ret = pci_device_load(s->pci_dev, f);
2144 if (ret < 0)
2145 return ret;
2146 }
2147
2148 qemu_get_be32s(f, &s->latch);
2149 qemu_get_8s(f, &s->sr_index);
2150 qemu_get_buffer(f, s->sr, 8);
2151 qemu_get_8s(f, &s->gr_index);
2152 qemu_get_buffer(f, s->gr, 16);
2153 qemu_get_8s(f, &s->ar_index);
2154 qemu_get_buffer(f, s->ar, 21);
2155 s->ar_flip_flop=qemu_get_be32(f);
2156 qemu_get_8s(f, &s->cr_index);
2157 qemu_get_buffer(f, s->cr, 256);
2158 qemu_get_8s(f, &s->msr);
2159 qemu_get_8s(f, &s->fcr);
2160 qemu_get_8s(f, &s->st00);
2161 qemu_get_8s(f, &s->st01);
2162
2163 qemu_get_8s(f, &s->dac_state);
2164 qemu_get_8s(f, &s->dac_sub_index);
2165 qemu_get_8s(f, &s->dac_read_index);
2166 qemu_get_8s(f, &s->dac_write_index);
2167 qemu_get_buffer(f, s->dac_cache, 3);
2168 qemu_get_buffer(f, s->palette, 768);
2169
2170 s->bank_offset=qemu_get_be32(f);
2171 is_vbe = qemu_get_byte(f);
2172 #ifdef CONFIG_BOCHS_VBE
2173 if (!is_vbe)
2174 return -EINVAL;
2175 qemu_get_be16s(f, &s->vbe_index);
2176 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2177 qemu_get_be16s(f, &s->vbe_regs[i]);
2178 qemu_get_be32s(f, &s->vbe_start_addr);
2179 qemu_get_be32s(f, &s->vbe_line_offset);
2180 qemu_get_be32s(f, &s->vbe_bank_mask);
2181 #else
2182 if (is_vbe)
2183 return -EINVAL;
2184 #endif
2185
2186 /* force refresh */
2187 s->graphic_mode = -1;
2188 return 0;
2189 }
2190
2191 typedef struct PCIVGAState {
2192 PCIDevice dev;
2193 VGAState vga_state;
2194 } PCIVGAState;
2195
2196 static int s1, s2;
2197
2198 static void mark_dirty(target_phys_addr_t start, target_phys_addr_t len)
2199 {
2200 target_phys_addr_t end = start + len;
2201
2202 while (start < end) {
2203 cpu_physical_memory_set_dirty(cpu_get_physical_page_desc(start));
2204 start += TARGET_PAGE_SIZE;
2205 }
2206 }
2207
2208 void vga_dirty_log_start(VGAState *s)
2209 {
2210 if (kvm_enabled() && s->map_addr)
2211 if (!s1) {
2212 kvm_log_start(s->map_addr, s->map_end - s->map_addr);
2213 mark_dirty(s->map_addr, s->map_end - s->map_addr);
2214 s1 = 1;
2215 }
2216 if (kvm_enabled() && s->lfb_vram_mapped) {
2217 if (!s2) {
2218 kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
2219 kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
2220 mark_dirty(isa_mem_base + 0xa0000, 0x10000);
2221 }
2222 s2 = 1;
2223 }
2224 }
2225
2226 void vga_dirty_log_stop(VGAState *s)
2227 {
2228 if (kvm_enabled() && s->map_addr && s1)
2229 kvm_log_stop(s->map_addr, s->map_end - s->map_addr);
2230
2231 if (kvm_enabled() && s->lfb_vram_mapped && s2) {
2232 kvm_log_stop(isa_mem_base + 0xa0000, 0x8000);
2233 kvm_log_stop(isa_mem_base + 0xa8000, 0x8000);
2234 }
2235 s1 = s2 = 0;
2236 }
2237
2238 static void vga_map(PCIDevice *pci_dev, int region_num,
2239 uint32_t addr, uint32_t size, int type)
2240 {
2241 PCIVGAState *d = (PCIVGAState *)pci_dev;
2242 VGAState *s = &d->vga_state;
2243 if (region_num == PCI_ROM_SLOT) {
2244 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2245 } else {
2246 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2247 }
2248
2249 s->map_addr = addr;
2250 s->map_end = addr + VGA_RAM_SIZE;
2251
2252 vga_dirty_log_start(s);
2253 }
2254
2255 #ifdef TARGET_IA64
2256 /* do the same job as vgabios before vgabios get ready - yeah */
2257 void vga_bios_init(VGAState *s)
2258 {
2259 uint8_t palette_model[192] = {
2260 0, 0, 0, 0, 0, 170, 0, 170,
2261 0, 0, 170, 170, 170, 0, 0, 170,
2262 0, 170, 170, 85, 0, 170, 170, 170,
2263 85, 85, 85, 85, 85, 255, 85, 255,
2264 85, 85, 255, 255, 255, 85, 85, 255,
2265 85, 255, 255, 255, 85, 255, 255, 255,
2266 0, 21, 0, 0, 21, 42, 0, 63,
2267 0, 0, 63, 42, 42, 21, 0, 42,
2268 21, 42, 42, 63, 0, 42, 63, 42,
2269 0, 21, 21, 0, 21, 63, 0, 63,
2270 21, 0, 63, 63, 42, 21, 21, 42,
2271 21, 63, 42, 63, 21, 42, 63, 63,
2272 21, 0, 0, 21, 0, 42, 21, 42,
2273 0, 21, 42, 42, 63, 0, 0, 63,
2274 0, 42, 63, 42, 0, 63, 42, 42,
2275 21, 0, 21, 21, 0, 63, 21, 42,
2276 21, 21, 42, 63, 63, 0, 21, 63,
2277 0, 63, 63, 42, 21, 63, 42, 63,
2278 21, 21, 0, 21, 21, 42, 21, 63,
2279 0, 21, 63, 42, 63, 21, 0, 63,
2280 21, 42, 63, 63, 0, 63, 63, 42,
2281 21, 21, 21, 21, 21, 63, 21, 63,
2282 21, 21, 63, 63, 63, 21, 21, 63,
2283 21, 63, 63, 63, 21, 63, 63, 63
2284 };
2285
2286 s->latch = 0;
2287
2288 s->sr_index = 3;
2289 s->sr[0] = 3;
2290 s->sr[1] = 0;
2291 s->sr[2] = 3;
2292 s->sr[3] = 0;
2293 s->sr[4] = 2;
2294 s->sr[5] = 0;
2295 s->sr[6] = 0;
2296 s->sr[7] = 0;
2297
2298 s->gr_index = 5;
2299 s->gr[0] = 0;
2300 s->gr[1] = 0;
2301 s->gr[2] = 0;
2302 s->gr[3] = 0;
2303 s->gr[4] = 0;
2304 s->gr[5] = 16;
2305 s->gr[6] = 14;
2306 s->gr[7] = 15;
2307 s->gr[8] = 255;
2308
2309 /* changed by out 0x03c0 */
2310 s->ar_index = 32;
2311 s->ar[0] = 0;
2312 s->ar[1] = 1;
2313 s->ar[2] = 2;
2314 s->ar[3] = 3;
2315 s->ar[4] = 4;
2316 s->ar[5] = 5;
2317 s->ar[6] = 6;
2318 s->ar[7] = 7;
2319 s->ar[8] = 8;
2320 s->ar[9] = 9;
2321 s->ar[10] = 10;
2322 s->ar[11] = 11;
2323 s->ar[12] = 12;
2324 s->ar[13] = 13;
2325 s->ar[14] = 14;
2326 s->ar[15] = 15;
2327 s->ar[16] = 12;
2328 s->ar[17] = 0;
2329 s->ar[18] = 15;
2330 s->ar[19] = 8;
2331 s->ar[20] = 0;
2332
2333 s->ar_flip_flop = 1;
2334
2335 s->cr_index = 15;
2336 s->cr[0] = 95;
2337 s->cr[1] = 79;
2338 s->cr[2] = 80;
2339 s->cr[3] = 130;
2340 s->cr[4] = 85;
2341 s->cr[5] = 129;
2342 s->cr[6] = 191;
2343 s->cr[7] = 31;
2344 s->cr[8] = 0;
2345 s->cr[9] = 79;
2346 s->cr[10] = 14;
2347 s->cr[11] = 15;
2348 s->cr[12] = 0;
2349 s->cr[13] = 0;
2350 s->cr[14] = 5;
2351 s->cr[15] = 160;
2352 s->cr[16] = 156;
2353 s->cr[17] = 142;
2354 s->cr[18] = 143;
2355 s->cr[19] = 40;
2356 s->cr[20] = 31;
2357 s->cr[21] = 150;
2358 s->cr[22] = 185;
2359 s->cr[23] = 163;
2360 s->cr[24] = 255;
2361
2362 s->msr = 103;
2363 s->fcr = 0;
2364 s->st00 = 0;
2365 s->st01 = 0;
2366
2367 /* dac_* & palette will be initialized by os through out 0x03c8 &
2368 * out 0c03c9(1:3) */
2369 s->dac_state = 0;
2370 s->dac_sub_index = 0;
2371 s->dac_read_index = 0;
2372 s->dac_write_index = 16;
2373 s->dac_cache[0] = 255;
2374 s->dac_cache[1] = 255;
2375 s->dac_cache[2] = 255;
2376
2377 /* palette */
2378 memcpy(s->palette, palette_model, 192);
2379
2380 s->bank_offset = 0;
2381 s->graphic_mode = -1;
2382
2383 /* TODO: add vbe support if enabled */
2384 }
2385 #endif
2386
2387 /* when used on xen/kvm environment, the vga_ram_base is not used */
2388 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2389 ram_addr_t vga_ram_offset, int vga_ram_size)
2390 {
2391 int i, j, v, b;
2392
2393 for(i = 0;i < 256; i++) {
2394 v = 0;
2395 for(j = 0; j < 8; j++) {
2396 v |= ((i >> j) & 1) << (j * 4);
2397 }
2398 expand4[i] = v;
2399
2400 v = 0;
2401 for(j = 0; j < 4; j++) {
2402 v |= ((i >> (2 * j)) & 3) << (j * 4);
2403 }
2404 expand2[i] = v;
2405 }
2406 for(i = 0; i < 16; i++) {
2407 v = 0;
2408 for(j = 0; j < 4; j++) {
2409 b = ((i >> j) & 1);
2410 v |= b << (2 * j);
2411 v |= b << (2 * j + 1);
2412 }
2413 expand4to8[i] = v;
2414 }
2415
2416 s->vram_ptr = vga_ram_base;
2417 s->vram_offset = vga_ram_offset;
2418 s->vram_size = vga_ram_size;
2419 s->ds = ds;
2420 s->get_bpp = vga_get_bpp;
2421 s->get_offsets = vga_get_offsets;
2422 s->get_resolution = vga_get_resolution;
2423 s->update = vga_update_display;
2424 s->invalidate = vga_invalidate_display;
2425 s->screen_dump = vga_screen_dump;
2426 s->text_update = vga_update_text;
2427 switch (vga_retrace_method) {
2428 case VGA_RETRACE_DUMB:
2429 s->retrace = vga_dumb_retrace;
2430 s->update_retrace_info = vga_dumb_update_retrace_info;
2431 break;
2432
2433 case VGA_RETRACE_PRECISE:
2434 s->retrace = vga_precise_retrace;
2435 s->update_retrace_info = vga_precise_update_retrace_info;
2436 break;
2437 }
2438 vga_reset(s);
2439 #ifdef TARGET_IA64
2440 vga_bios_init(s);
2441 #endif
2442 }
2443
2444 /* used by both ISA and PCI */
2445 void vga_init(VGAState *s)
2446 {
2447 int vga_io_memory;
2448
2449 qemu_register_reset(vga_reset, s);
2450 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2451
2452 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2453
2454 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2455 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2456 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2457 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2458
2459 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2460
2461 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2462 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2463 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2464 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2465 s->bank_offset = 0;
2466
2467 #ifdef CONFIG_BOCHS_VBE
2468 #if defined (TARGET_I386)
2469 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2470 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2471
2472 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2473 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2474
2475 /* old Bochs IO ports */
2476 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2477 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2478
2479 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2480 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2481 #else
2482 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2483 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2484
2485 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2486 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2487 #endif
2488 #endif /* CONFIG_BOCHS_VBE */
2489
2490 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2491 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2492 vga_io_memory);
2493 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2494 }
2495
2496 /* Memory mapped interface */
2497 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2498 {
2499 VGAState *s = opaque;
2500
2501 return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
2502 }
2503
2504 static void vga_mm_writeb (void *opaque,
2505 target_phys_addr_t addr, uint32_t value)
2506 {
2507 VGAState *s = opaque;
2508
2509 vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
2510 }
2511
2512 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2513 {
2514 VGAState *s = opaque;
2515
2516 return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
2517 }
2518
2519 static void vga_mm_writew (void *opaque,
2520 target_phys_addr_t addr, uint32_t value)
2521 {
2522 VGAState *s = opaque;
2523
2524 vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
2525 }
2526
2527 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2528 {
2529 VGAState *s = opaque;
2530
2531 return vga_ioport_read(s, addr >> s->it_shift);
2532 }
2533
2534 static void vga_mm_writel (void *opaque,
2535 target_phys_addr_t addr, uint32_t value)
2536 {
2537 VGAState *s = opaque;
2538
2539 vga_ioport_write(s, addr >> s->it_shift, value);
2540 }
2541
2542 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2543 &vga_mm_readb,
2544 &vga_mm_readw,
2545 &vga_mm_readl,
2546 };
2547
2548 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2549 &vga_mm_writeb,
2550 &vga_mm_writew,
2551 &vga_mm_writel,
2552 };
2553
2554 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2555 target_phys_addr_t ctrl_base, int it_shift)
2556 {
2557 int s_ioport_ctrl, vga_io_memory;
2558
2559 s->it_shift = it_shift;
2560 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2561 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2562
2563 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2564
2565 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2566 s->bank_offset = 0;
2567 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2568 qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
2569 }
2570
2571 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2572 unsigned long vga_ram_offset, int vga_ram_size)
2573 {
2574 VGAState *s;
2575
2576 s = qemu_mallocz(sizeof(VGAState));
2577 if (!s)
2578 return -1;
2579
2580 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2581 vga_init(s);
2582
2583 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2584 s->screen_dump, s->text_update, s);
2585
2586 #ifdef CONFIG_BOCHS_VBE
2587 /* XXX: use optimized standard vga accesses */
2588 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2589 vga_ram_size, vga_ram_offset);
2590 #endif
2591 return 0;
2592 }
2593
2594 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
2595 unsigned long vga_ram_offset, int vga_ram_size,
2596 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2597 int it_shift)
2598 {
2599 VGAState *s;
2600
2601 s = qemu_mallocz(sizeof(VGAState));
2602 if (!s)
2603 return -1;
2604
2605 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2606 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2607
2608 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2609 s->screen_dump, s->text_update, s);
2610
2611 #ifdef CONFIG_BOCHS_VBE
2612 /* XXX: use optimized standard vga accesses */
2613 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2614 vga_ram_size, vga_ram_offset);
2615 #endif
2616 return 0;
2617 }
2618
2619 static void pci_vga_write_config(PCIDevice *d,
2620 uint32_t address, uint32_t val, int len)
2621 {
2622 PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
2623 VGAState *s = &pvs->vga_state;
2624
2625 vga_dirty_log_stop(s);
2626 pci_default_write_config(d, address, val, len);
2627 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
2628 s->map_addr = 0;
2629 vga_dirty_log_start(s);
2630 }
2631
2632 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
2633 unsigned long vga_ram_offset, int vga_ram_size,
2634 unsigned long vga_bios_offset, int vga_bios_size)
2635 {
2636 PCIVGAState *d;
2637 VGAState *s;
2638 uint8_t *pci_conf;
2639
2640 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2641 sizeof(PCIVGAState),
2642 -1, NULL, pci_vga_write_config);
2643 if (!d)
2644 return -1;
2645 s = &d->vga_state;
2646
2647 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2648 vga_init(s);
2649
2650 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
2651 s->screen_dump, s->text_update, s);
2652
2653 s->pci_dev = &d->dev;
2654
2655 pci_conf = d->dev.config;
2656 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2657 pci_conf[0x01] = 0x12;
2658 pci_conf[0x02] = 0x11;
2659 pci_conf[0x03] = 0x11;
2660 pci_conf[0x0a] = 0x00; // VGA controller
2661 pci_conf[0x0b] = 0x03;
2662 pci_conf[0x0e] = 0x00; // header_type
2663
2664 /* XXX: vga_ram_size must be a power of two */
2665 pci_register_io_region(&d->dev, 0, vga_ram_size,
2666 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2667 if (vga_bios_size != 0) {
2668 unsigned int bios_total_size;
2669 s->bios_offset = vga_bios_offset;
2670 s->bios_size = vga_bios_size;
2671 /* must be a power of two */
2672 bios_total_size = 1;
2673 while (bios_total_size < vga_bios_size)
2674 bios_total_size <<= 1;
2675 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2676 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2677 }
2678 return 0;
2679 }
2680
2681 /********************************************************/
2682 /* vga screen dump */
2683
2684 static int vga_save_w, vga_save_h;
2685
2686 static void vga_save_dpy_update(DisplayState *s,
2687 int x, int y, int w, int h)
2688 {
2689 }
2690
2691 static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2692 {
2693 s->linesize = w * 4;
2694 s->data = qemu_mallocz(h * s->linesize);
2695 vga_save_w = w;
2696 vga_save_h = h;
2697 }
2698
2699 static void vga_save_dpy_refresh(DisplayState *s)
2700 {
2701 }
2702
2703 int ppm_save(const char *filename, uint8_t *data,
2704 int w, int h, int linesize)
2705 {
2706 FILE *f;
2707 uint8_t *d, *d1;
2708 unsigned int v;
2709 int y, x;
2710
2711 f = fopen(filename, "wb");
2712 if (!f)
2713 return -1;
2714 fprintf(f, "P6\n%d %d\n%d\n",
2715 w, h, 255);
2716 d1 = data;
2717 for(y = 0; y < h; y++) {
2718 d = d1;
2719 for(x = 0; x < w; x++) {
2720 v = *(uint32_t *)d;
2721 fputc((v >> 16) & 0xff, f);
2722 fputc((v >> 8) & 0xff, f);
2723 fputc((v) & 0xff, f);
2724 d += 4;
2725 }
2726 d1 += linesize;
2727 }
2728 fclose(f);
2729 return 0;
2730 }
2731
2732 static void vga_screen_dump_blank(VGAState *s, const char *filename)
2733 {
2734 FILE *f;
2735 unsigned int y, x, w, h;
2736
2737 w = s->last_scr_width * sizeof(uint32_t);
2738 h = s->last_scr_height;
2739
2740 f = fopen(filename, "wb");
2741 if (!f)
2742 return;
2743 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
2744 for (y = 0; y < h; y++) {
2745 for (x = 0; x < w; x++) {
2746 fputc(0, f);
2747 }
2748 }
2749 fclose(f);
2750 }
2751
2752 static void vga_screen_dump_common(VGAState *s, const char *filename,
2753 int w, int h)
2754 {
2755 DisplayState *saved_ds, ds1, *ds = &ds1;
2756
2757 /* XXX: this is a little hackish */
2758 vga_invalidate_display(s);
2759 saved_ds = s->ds;
2760
2761 memset(ds, 0, sizeof(DisplayState));
2762 ds->dpy_update = vga_save_dpy_update;
2763 ds->dpy_resize = vga_save_dpy_resize;
2764 ds->dpy_refresh = vga_save_dpy_refresh;
2765 ds->depth = 32;
2766
2767 ds->linesize = w * sizeof(uint32_t);
2768 ds->data = qemu_mallocz(h * ds->linesize);
2769 s->ds = ds;
2770 s->graphic_mode = -1;
2771 vga_update_display(s);
2772 ppm_save(filename, ds->data, w, h, ds->linesize);
2773 qemu_free(ds->data);
2774 s->ds = saved_ds;
2775 }
2776
2777 static void vga_screen_dump_graphic(VGAState *s, const char *filename)
2778 {
2779 int w, h;
2780
2781 s->get_resolution(s, &w, &h);
2782 vga_screen_dump_common(s, filename, w, h);
2783 }
2784
2785 static void vga_screen_dump_text(VGAState *s, const char *filename)
2786 {
2787 int w, h, cwidth, cheight;
2788
2789 vga_get_text_resolution(s, &w, &h, &cwidth, &cheight);
2790 vga_screen_dump_common(s, filename, w * cwidth, h * cheight);
2791 }
2792
2793 /* save the vga display in a PPM image even if no display is
2794 available */
2795 static void vga_screen_dump(void *opaque, const char *filename)
2796 {
2797 VGAState *s = (VGAState *)opaque;
2798
2799 if (!(s->ar_index & 0x20))
2800 vga_screen_dump_blank(s, filename);
2801 else if (s->gr[6] & 1)
2802 vga_screen_dump_graphic(s, filename);
2803 else
2804 vga_screen_dump_text(s, filename);
2805 }
Patches shipped by Fedora