Kill redundant declarion of perror()
[qemu-kvm/fedora.git] / hw / soc_dma.h
blob47bc4ea2690d28cd67472a8d0174b220c7121c1f
1 /*
2 * On-chip DMA controller framework.
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 struct soc_dma_s;
23 struct soc_dma_ch_s;
24 typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
25 typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch);
27 enum soc_dma_port_type {
28 soc_dma_port_mem,
29 soc_dma_port_fifo,
30 soc_dma_port_other,
33 enum soc_dma_access_type {
34 soc_dma_access_const,
35 soc_dma_access_linear,
36 soc_dma_access_other,
39 struct soc_dma_ch_s {
40 /* Private */
41 struct soc_dma_s *dma;
42 int num;
43 QEMUTimer *timer;
45 /* Set by soc_dma.c */
46 int enable;
47 int update;
49 /* This should be set by dma->setup_fn(). */
50 int bytes;
51 /* Initialised by the DMA module, call soc_dma_ch_update after writing. */
52 enum soc_dma_access_type type[2];
53 target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */
54 /* Private */
55 void *paddr[2];
56 soc_dma_io_t io_fn[2];
57 void *io_opaque[2];
59 int running;
60 soc_dma_transfer_t transfer_fn;
62 /* Set and used by the DMA module. */
63 void *opaque;
66 struct soc_dma_s {
67 /* Following fields are set by the SoC DMA module and can be used
68 * by anybody. */
69 uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
70 qemu_irq *drq;
71 void *opaque;
72 int64_t freq;
73 soc_dma_transfer_t transfer_fn;
74 soc_dma_transfer_t setup_fn;
75 /* Set by soc_dma_init() for use by the DMA module. */
76 struct soc_dma_ch_s *ch;
79 /* Call to activate or stop a DMA channel. */
80 void soc_dma_set_request(struct soc_dma_ch_s *ch, int level);
81 /* Call after every write to one of the following fields and before
82 * calling soc_dma_set_request(ch, 1):
83 * ch->type[0...1],
84 * ch->vaddr[0...1],
85 * ch->paddr[0...1],
86 * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */
87 void soc_dma_ch_update(struct soc_dma_ch_s *ch);
89 /* The SoC should call this when the DMA module is being reset. */
90 void soc_dma_reset(struct soc_dma_s *s);
91 struct soc_dma_s *soc_dma_init(int n);
93 void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
94 soc_dma_io_t fn, void *opaque, int out);
95 void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
96 target_phys_addr_t virt_base, size_t size);
98 static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
99 target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
101 return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
104 static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
105 target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
107 return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
110 static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma,
111 ram_addr_t offset, target_phys_addr_t virt_base, size_t size)
113 return soc_dma_port_add_mem(dma, phys_ram_base + offset, virt_base, size);