4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "virtio-net.h"
31 #include "device-assignment.h"
38 pci_set_irq_fn set_irq
;
39 pci_map_irq_fn map_irq
;
40 uint32_t config_reg
; /* XXX: suppress */
42 SetIRQFunc
*low_set_irq
;
44 PCIDevice
*devices
[256];
45 PCIDevice
*parent_dev
;
47 /* The bus IRQ state is the logical OR of the connected devices.
48 Keep a count of the number of devices with raised IRQs. */
53 static void pci_update_mappings(PCIDevice
*d
);
54 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
56 target_phys_addr_t pci_mem_base
;
57 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
58 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
59 static int pci_irq_index
;
60 static PCIBus
*first_bus
;
62 static void pcibus_save(QEMUFile
*f
, void *opaque
)
64 PCIBus
*bus
= (PCIBus
*)opaque
;
67 qemu_put_be32(f
, bus
->nirq
);
68 for (i
= 0; i
< bus
->nirq
; i
++)
69 qemu_put_be32(f
, bus
->irq_count
[i
]);
72 static int pcibus_load(QEMUFile
*f
, void *opaque
, int version_id
)
74 PCIBus
*bus
= (PCIBus
*)opaque
;
80 nirq
= qemu_get_be32(f
);
81 if (bus
->nirq
!= nirq
) {
82 fprintf(stderr
, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
87 for (i
= 0; i
< nirq
; i
++)
88 bus
->irq_count
[i
] = qemu_get_be32(f
);
93 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
94 qemu_irq
*pic
, int devfn_min
, int nirq
)
99 bus
= qemu_mallocz(sizeof(PCIBus
) + (nirq
* sizeof(int)));
100 bus
->set_irq
= set_irq
;
101 bus
->map_irq
= map_irq
;
102 bus
->irq_opaque
= pic
;
103 bus
->devfn_min
= devfn_min
;
106 register_savevm("PCIBUS", nbus
++, 1, pcibus_save
, pcibus_load
, bus
);
110 static PCIBus
*pci_register_secondary_bus(PCIDevice
*dev
, pci_map_irq_fn map_irq
)
113 bus
= qemu_mallocz(sizeof(PCIBus
));
114 bus
->map_irq
= map_irq
;
115 bus
->parent_dev
= dev
;
116 bus
->next
= dev
->bus
->next
;
117 dev
->bus
->next
= bus
;
121 int pci_bus_num(PCIBus
*s
)
126 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
130 qemu_put_be32(f
, 2); /* PCI device version */
131 qemu_put_buffer(f
, s
->config
, 256);
132 for (i
= 0; i
< 4; i
++)
133 qemu_put_be32(f
, s
->irq_state
[i
]);
136 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
141 version_id
= qemu_get_be32(f
);
144 qemu_get_buffer(f
, s
->config
, 256);
145 pci_update_mappings(s
);
148 for (i
= 0; i
< 4; i
++)
149 s
->irq_state
[i
] = qemu_get_be32(f
);
154 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
158 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
159 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
160 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
164 /* -1 for devfn means auto assign */
165 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
166 int instance_size
, int devfn
,
167 PCIConfigReadFunc
*config_read
,
168 PCIConfigWriteFunc
*config_write
)
172 if (pci_irq_index
>= PCI_DEVICES_MAX
)
176 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
177 if (!bus
->devices
[devfn
])
183 pci_dev
= qemu_mallocz(instance_size
);
187 pci_dev
->devfn
= devfn
;
188 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
189 memset(pci_dev
->irq_state
, 0, sizeof(pci_dev
->irq_state
));
190 pci_set_default_subsystem_id(pci_dev
);
193 config_read
= pci_default_read_config
;
195 config_write
= pci_default_write_config
;
196 pci_dev
->config_read
= config_read
;
197 pci_dev
->config_write
= config_write
;
198 pci_dev
->irq_index
= pci_irq_index
++;
199 bus
->devices
[devfn
] = pci_dev
;
200 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, 4);
204 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
206 return addr
+ pci_mem_base
;
209 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
214 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
215 r
= &pci_dev
->io_regions
[i
];
218 if (r
->type
== PCI_ADDRESS_SPACE_IO
) {
219 isa_unassign_ioport(r
->addr
, r
->size
);
221 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
228 int pci_unregister_device(PCIDevice
*pci_dev
)
232 if (pci_dev
->unregister
)
233 ret
= pci_dev
->unregister(pci_dev
);
237 pci_unregister_io_regions(pci_dev
);
239 qemu_free_irqs(pci_dev
->irq
);
241 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
246 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
247 uint32_t size
, int type
,
248 PCIMapIORegionFunc
*map_func
)
253 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
257 term_printf("WARNING: PCI region size must be pow2 "
258 "type=0x%x, size=0x%x\n", type
, size
);
260 r
= &pci_dev
->io_regions
[region_num
];
264 r
->map_func
= map_func
;
265 if (region_num
== PCI_ROM_SLOT
) {
268 addr
= 0x10 + region_num
* 4;
270 *(uint32_t *)(pci_dev
->config
+ addr
) = cpu_to_le32(type
);
274 static void pci_update_mappings(PCIDevice
*d
)
278 uint32_t last_addr
, new_addr
, config_ofs
;
280 cmd
= le16_to_cpu(*(uint16_t *)(d
->config
+ PCI_COMMAND
));
281 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
282 r
= &d
->io_regions
[i
];
283 if (i
== PCI_ROM_SLOT
) {
286 config_ofs
= 0x10 + i
* 4;
289 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
290 if (cmd
& PCI_COMMAND_IO
) {
291 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
293 new_addr
= new_addr
& ~(r
->size
- 1);
294 last_addr
= new_addr
+ r
->size
- 1;
295 /* NOTE: we have only 64K ioports on PC */
296 if (last_addr
<= new_addr
|| new_addr
== 0 ||
297 last_addr
>= 0x10000) {
304 if (cmd
& PCI_COMMAND_MEMORY
) {
305 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
307 /* the ROM slot has a specific enable bit */
308 if (i
== PCI_ROM_SLOT
&& !(new_addr
& 1))
310 new_addr
= new_addr
& ~(r
->size
- 1);
311 last_addr
= new_addr
+ r
->size
- 1;
312 /* NOTE: we do not support wrapping */
313 /* XXX: as we cannot support really dynamic
314 mappings, we handle specific values as invalid
316 if (last_addr
<= new_addr
|| new_addr
== 0 ||
325 /* now do the real mapping */
326 if (new_addr
!= r
->addr
) {
328 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
330 /* NOTE: specific hack for IDE in PC case:
331 only one byte must be mapped. */
332 class = d
->config
[0x0a] | (d
->config
[0x0b] << 8);
333 if (class == 0x0101 && r
->size
== 4) {
334 isa_unassign_ioport(r
->addr
+ 2, 1);
336 isa_unassign_ioport(r
->addr
, r
->size
);
339 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
342 qemu_unregister_coalesced_mmio(r
->addr
, r
->size
);
347 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
354 uint32_t pci_default_read_config(PCIDevice
*d
,
355 uint32_t address
, int len
)
362 if (address
<= 0xfc) {
363 val
= le32_to_cpu(*(uint32_t *)(d
->config
+ address
));
368 if (address
<= 0xfe) {
369 val
= le16_to_cpu(*(uint16_t *)(d
->config
+ address
));
374 val
= d
->config
[address
];
380 void pci_default_write_config(PCIDevice
*d
,
381 uint32_t address
, uint32_t val
, int len
)
386 if (len
== 4 && ((address
>= 0x10 && address
< 0x10 + 4 * 6) ||
387 (address
>= 0x30 && address
< 0x34))) {
391 if ( address
>= 0x30 ) {
394 reg
= (address
- 0x10) >> 2;
396 r
= &d
->io_regions
[reg
];
399 /* compute the stored value */
400 if (reg
== PCI_ROM_SLOT
) {
401 /* keep ROM enable bit */
402 val
&= (~(r
->size
- 1)) | 1;
404 val
&= ~(r
->size
- 1);
407 *(uint32_t *)(d
->config
+ address
) = cpu_to_le32(val
);
408 pci_update_mappings(d
);
412 /* not efficient, but simple */
414 for(i
= 0; i
< len
; i
++) {
415 /* default read/write accesses */
416 switch(d
->config
[0x0e]) {
429 case 0x10 ... 0x27: /* base */
430 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
431 case 0x30 ... 0x33: /* rom */
452 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
453 case 0x38 ... 0x3b: /* rom */
464 /* Mask out writes to reserved bits in registers */
467 val
&= ~PCI_COMMAND_RESERVED_MASK_HI
;
470 val
&= ~PCI_STATUS_RESERVED_MASK_LO
;
473 val
&= ~PCI_STATUS_RESERVED_MASK_HI
;
476 d
->config
[addr
] = val
;
483 #ifdef USE_KVM_DEVICE_ASSIGNMENT
484 if (kvm_enabled() && qemu_kvm_irqchip_in_kernel() &&
485 address
>= PIIX_CONFIG_IRQ_ROUTE
&&
486 address
< PIIX_CONFIG_IRQ_ROUTE
+ 4)
487 assigned_dev_update_irq(d
);
488 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
491 if (end
> PCI_COMMAND
&& address
< (PCI_COMMAND
+ 2)) {
492 /* if the command register is modified, we must modify the mappings */
493 pci_update_mappings(d
);
497 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
501 int config_addr
, bus_num
;
503 #if defined(DEBUG_PCI) && 0
504 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
507 bus_num
= (addr
>> 16) & 0xff;
508 while (s
&& s
->bus_num
!= bus_num
)
512 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
515 config_addr
= addr
& 0xff;
516 #if defined(DEBUG_PCI)
517 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
518 pci_dev
->name
, config_addr
, val
, len
);
520 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
523 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
527 int config_addr
, bus_num
;
530 bus_num
= (addr
>> 16) & 0xff;
531 while (s
&& s
->bus_num
!= bus_num
)
535 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
552 config_addr
= addr
& 0xff;
553 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
554 #if defined(DEBUG_PCI)
555 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
556 pci_dev
->name
, config_addr
, val
, len
);
559 #if defined(DEBUG_PCI) && 0
560 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
566 /***********************************************************/
567 /* generic PCI irq support */
569 /* 0 <= irq_num <= 3. level must be 0 or 1 */
570 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
572 PCIDevice
*pci_dev
= (PCIDevice
*)opaque
;
576 change
= level
- pci_dev
->irq_state
[irq_num
];
580 pci_dev
->irq_state
[irq_num
] = level
;
582 #if defined(TARGET_IA64)
583 ioapic_set_irq(pci_dev
, irq_num
, level
);
588 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
591 pci_dev
= bus
->parent_dev
;
593 bus
->irq_count
[irq_num
] += change
;
594 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
597 int pci_map_irq(PCIDevice
*pci_dev
, int pin
)
599 return pci_dev
->bus
->map_irq(pci_dev
, pin
);
602 /***********************************************************/
603 /* monitor info on PCI */
610 static const pci_class_desc pci_class_descriptions
[] =
612 { 0x0100, "SCSI controller"},
613 { 0x0101, "IDE controller"},
614 { 0x0102, "Floppy controller"},
615 { 0x0103, "IPI controller"},
616 { 0x0104, "RAID controller"},
617 { 0x0106, "SATA controller"},
618 { 0x0107, "SAS controller"},
619 { 0x0180, "Storage controller"},
620 { 0x0200, "Ethernet controller"},
621 { 0x0201, "Token Ring controller"},
622 { 0x0202, "FDDI controller"},
623 { 0x0203, "ATM controller"},
624 { 0x0280, "Network controller"},
625 { 0x0300, "VGA controller"},
626 { 0x0301, "XGA controller"},
627 { 0x0302, "3D controller"},
628 { 0x0380, "Display controller"},
629 { 0x0400, "Video controller"},
630 { 0x0401, "Audio controller"},
632 { 0x0480, "Multimedia controller"},
633 { 0x0500, "RAM controller"},
634 { 0x0501, "Flash controller"},
635 { 0x0580, "Memory controller"},
636 { 0x0600, "Host bridge"},
637 { 0x0601, "ISA bridge"},
638 { 0x0602, "EISA bridge"},
639 { 0x0603, "MC bridge"},
640 { 0x0604, "PCI bridge"},
641 { 0x0605, "PCMCIA bridge"},
642 { 0x0606, "NUBUS bridge"},
643 { 0x0607, "CARDBUS bridge"},
644 { 0x0608, "RACEWAY bridge"},
646 { 0x0c03, "USB controller"},
650 static void pci_info_device(PCIDevice
*d
)
654 const pci_class_desc
*desc
;
656 term_printf(" Bus %2d, device %3d, function %d:\n",
657 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7);
658 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
660 desc
= pci_class_descriptions
;
661 while (desc
->desc
&& class != desc
->class)
664 term_printf("%s", desc
->desc
);
666 term_printf("Class %04x", class);
668 term_printf(": PCI device %04x:%04x\n",
669 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
670 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))));
672 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
673 term_printf(" IRQ %d.\n", d
->config
[PCI_INTERRUPT_LINE
]);
675 if (class == 0x0604) {
676 term_printf(" BUS %d.\n", d
->config
[0x19]);
678 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
679 r
= &d
->io_regions
[i
];
681 term_printf(" BAR%d: ", i
);
682 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
683 term_printf("I/O at 0x%04x [0x%04x].\n",
684 r
->addr
, r
->addr
+ r
->size
- 1);
686 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
687 r
->addr
, r
->addr
+ r
->size
- 1);
691 if (class == 0x0604 && d
->config
[0x19] != 0) {
692 pci_for_each_device(d
->config
[0x19], pci_info_device
);
696 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
))
698 PCIBus
*bus
= first_bus
;
702 while (bus
&& bus
->bus_num
!= bus_num
)
705 for(devfn
= 0; devfn
< 256; devfn
++) {
706 d
= bus
->devices
[devfn
];
715 pci_for_each_device(0, pci_info_device
);
718 static const char * const pci_nic_models
[] = {
730 typedef PCIDevice
*(*PCINICInitFn
)(PCIBus
*, NICInfo
*, int);
732 static PCINICInitFn pci_nic_init_fns
[] = {
744 /* Initialize a PCI NIC. */
745 PCIDevice
*pci_nic_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
,
746 const char *default_model
)
751 qemu_check_nic_model_list(nd
, pci_nic_models
, default_model
);
753 for (i
= 0; pci_nic_models
[i
]; i
++)
754 if (strcmp(nd
->model
, pci_nic_models
[i
]) == 0) {
755 pci_dev
= pci_nic_init_fns
[i
](bus
, nd
, devfn
);
757 nd
->devfn
= pci_dev
->devfn
;
770 static void pci_bridge_write_config(PCIDevice
*d
,
771 uint32_t address
, uint32_t val
, int len
)
773 PCIBridge
*s
= (PCIBridge
*)d
;
775 if (address
== 0x19 || (address
== 0x18 && len
> 1)) {
777 s
->bus
->bus_num
= val
& 0xff;
779 s
->bus
->bus_num
= (val
>> 8) & 0xff;
780 #if defined(DEBUG_PCI)
781 printf ("pci-bridge: %s: Assigned bus %d\n", d
->name
, s
->bus
->bus_num
);
784 pci_default_write_config(d
, address
, val
, len
);
787 PCIBus
*pci_find_bus(int bus_num
)
789 PCIBus
*bus
= first_bus
;
791 while (bus
&& bus
->bus_num
!= bus_num
)
797 PCIDevice
*pci_find_device(int bus_num
, int slot
)
801 PCIBus
*bus
= pci_find_bus(bus_num
);
806 for(devfn
= 0; devfn
< 256; devfn
++) {
807 d
= bus
->devices
[devfn
];
808 if (d
&& PCI_SLOT(devfn
) == slot
)
814 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint32_t id
,
815 pci_map_irq_fn map_irq
, const char *name
)
818 s
= (PCIBridge
*)pci_register_device(bus
, name
, sizeof(PCIBridge
),
819 devfn
, NULL
, pci_bridge_write_config
);
820 s
->dev
.config
[0x00] = id
>> 16;
821 s
->dev
.config
[0x01] = id
>> 24;
822 s
->dev
.config
[0x02] = id
; // device_id
823 s
->dev
.config
[0x03] = id
>> 8;
824 s
->dev
.config
[0x04] = 0x06; // command = bus master, pci mem
825 s
->dev
.config
[0x05] = 0x00;
826 s
->dev
.config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
827 s
->dev
.config
[0x07] = 0x00; // status = fast devsel
828 s
->dev
.config
[0x08] = 0x00; // revision
829 s
->dev
.config
[0x09] = 0x00; // programming i/f
830 s
->dev
.config
[0x0A] = 0x04; // class_sub = PCI to PCI bridge
831 s
->dev
.config
[0x0B] = 0x06; // class_base = PCI_bridge
832 s
->dev
.config
[0x0D] = 0x10; // latency_timer
833 s
->dev
.config
[0x0E] = 0x81; // header_type
834 s
->dev
.config
[0x1E] = 0xa0; // secondary status
836 s
->bus
= pci_register_secondary_bus(&s
->dev
, map_irq
);