Kill redundant declarion of perror()
[qemu-kvm/fedora.git] / hw / iommu.c
blob82a49328841b2b9a8ef330e58f954abd681f35ba
1 /*
2 * QEMU SPARC iommu emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw.h"
25 #include "sun4m.h"
27 /* debug iommu */
28 //#define DEBUG_IOMMU
30 #ifdef DEBUG_IOMMU
31 #define DPRINTF(fmt, args...) \
32 do { printf("IOMMU: " fmt , ##args); } while (0)
33 #else
34 #define DPRINTF(fmt, args...)
35 #endif
37 #define IOMMU_NREGS (4*4096/4)
38 #define IOMMU_CTRL (0x0000 >> 2)
39 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
40 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
41 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
42 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
43 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
44 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
45 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
46 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
47 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
48 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
49 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
50 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
51 #define IOMMU_CTRL_MASK 0x0000001d
53 #define IOMMU_BASE (0x0004 >> 2)
54 #define IOMMU_BASE_MASK 0x07fffc00
56 #define IOMMU_TLBFLUSH (0x0014 >> 2)
57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
59 #define IOMMU_PGFLUSH (0x0018 >> 2)
60 #define IOMMU_PGFLUSH_MASK 0xffffffff
62 #define IOMMU_AFSR (0x1000 >> 2)
63 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
64 #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
65 transaction */
66 #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
67 12.8 us. */
68 #define IOMMU_AFSR_BE 0x10000000 /* Write access received error
69 acknowledge */
70 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
71 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
72 #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
73 hardware */
74 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
75 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
76 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
77 #define IOMMU_AFSR_MASK 0xff0fffff
79 #define IOMMU_AFAR (0x1004 >> 2)
81 #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
82 #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
83 #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
84 #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
85 #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
86 #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
87 #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
88 #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
89 #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
90 #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
91 #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
92 #define IOMMU_AER_MASK 0x801f000f
94 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
95 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
96 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
97 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
98 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
99 bypass enabled */
100 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
101 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
102 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
103 produced by this device as pure
104 physical. */
105 #define IOMMU_SBCFG_MASK 0x00010003
107 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
108 #define IOMMU_ARBEN_MASK 0x001f0000
109 #define IOMMU_MID 0x00000008
111 #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
112 #define IOMMU_MASK_ID_MASK 0x00ffffff
114 #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
115 #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
117 /* The format of an iopte in the page tables */
118 #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
119 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
120 Viking/MXCC) */
121 #define IOPTE_WRITE 0x00000004 /* Writeable */
122 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
123 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
125 #define IOMMU_PAGE_SHIFT 12
126 #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
127 #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
129 typedef struct IOMMUState {
130 uint32_t regs[IOMMU_NREGS];
131 target_phys_addr_t iostart;
132 uint32_t version;
133 qemu_irq irq;
134 } IOMMUState;
136 static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
138 IOMMUState *s = opaque;
139 target_phys_addr_t saddr;
140 uint32_t ret;
142 saddr = addr >> 2;
143 switch (saddr) {
144 default:
145 ret = s->regs[saddr];
146 break;
147 case IOMMU_AFAR:
148 case IOMMU_AFSR:
149 ret = s->regs[saddr];
150 qemu_irq_lower(s->irq);
151 break;
153 DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
154 return ret;
157 static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
158 uint32_t val)
160 IOMMUState *s = opaque;
161 target_phys_addr_t saddr;
163 saddr = addr >> 2;
164 DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
165 switch (saddr) {
166 case IOMMU_CTRL:
167 switch (val & IOMMU_CTRL_RNGE) {
168 case IOMMU_RNGE_16MB:
169 s->iostart = 0xffffffffff000000ULL;
170 break;
171 case IOMMU_RNGE_32MB:
172 s->iostart = 0xfffffffffe000000ULL;
173 break;
174 case IOMMU_RNGE_64MB:
175 s->iostart = 0xfffffffffc000000ULL;
176 break;
177 case IOMMU_RNGE_128MB:
178 s->iostart = 0xfffffffff8000000ULL;
179 break;
180 case IOMMU_RNGE_256MB:
181 s->iostart = 0xfffffffff0000000ULL;
182 break;
183 case IOMMU_RNGE_512MB:
184 s->iostart = 0xffffffffe0000000ULL;
185 break;
186 case IOMMU_RNGE_1GB:
187 s->iostart = 0xffffffffc0000000ULL;
188 break;
189 default:
190 case IOMMU_RNGE_2GB:
191 s->iostart = 0xffffffff80000000ULL;
192 break;
194 DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
195 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
196 break;
197 case IOMMU_BASE:
198 s->regs[saddr] = val & IOMMU_BASE_MASK;
199 break;
200 case IOMMU_TLBFLUSH:
201 DPRINTF("tlb flush %x\n", val);
202 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
203 break;
204 case IOMMU_PGFLUSH:
205 DPRINTF("page flush %x\n", val);
206 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
207 break;
208 case IOMMU_AFAR:
209 s->regs[saddr] = val;
210 qemu_irq_lower(s->irq);
211 break;
212 case IOMMU_AER:
213 s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
214 break;
215 case IOMMU_AFSR:
216 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
217 qemu_irq_lower(s->irq);
218 break;
219 case IOMMU_SBCFG0:
220 case IOMMU_SBCFG1:
221 case IOMMU_SBCFG2:
222 case IOMMU_SBCFG3:
223 s->regs[saddr] = val & IOMMU_SBCFG_MASK;
224 break;
225 case IOMMU_ARBEN:
226 // XXX implement SBus probing: fault when reading unmapped
227 // addresses, fault cause and address stored to MMU/IOMMU
228 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
229 break;
230 case IOMMU_MASK_ID:
231 s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
232 break;
233 default:
234 s->regs[saddr] = val;
235 break;
239 static CPUReadMemoryFunc *iommu_mem_read[3] = {
240 NULL,
241 NULL,
242 iommu_mem_readl,
245 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
246 NULL,
247 NULL,
248 iommu_mem_writel,
251 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
253 uint32_t ret;
254 target_phys_addr_t iopte;
255 #ifdef DEBUG_IOMMU
256 target_phys_addr_t pa = addr;
257 #endif
259 iopte = s->regs[IOMMU_BASE] << 4;
260 addr &= ~s->iostart;
261 iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
262 cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
263 tswap32s(&ret);
264 DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
265 ", *pte = %x\n", pa, iopte, ret);
267 return ret;
270 static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
271 uint32_t pte)
273 uint32_t tmppte;
274 target_phys_addr_t pa;
276 tmppte = pte;
277 pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
278 DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
279 " (iopte = %x)\n", addr, pa, tmppte);
281 return pa;
284 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
285 int is_write)
287 DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
288 s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
289 IOMMU_AFSR_FAV;
290 if (!is_write)
291 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
292 s->regs[IOMMU_AFAR] = addr;
293 qemu_irq_raise(s->irq);
296 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
297 uint8_t *buf, int len, int is_write)
299 int l;
300 uint32_t flags;
301 target_phys_addr_t page, phys_addr;
303 while (len > 0) {
304 page = addr & IOMMU_PAGE_MASK;
305 l = (page + IOMMU_PAGE_SIZE) - addr;
306 if (l > len)
307 l = len;
308 flags = iommu_page_get_flags(opaque, page);
309 if (!(flags & IOPTE_VALID)) {
310 iommu_bad_addr(opaque, page, is_write);
311 return;
313 phys_addr = iommu_translate_pa(addr, flags);
314 if (is_write) {
315 if (!(flags & IOPTE_WRITE)) {
316 iommu_bad_addr(opaque, page, is_write);
317 return;
319 cpu_physical_memory_write(phys_addr, buf, l);
320 } else {
321 cpu_physical_memory_read(phys_addr, buf, l);
323 len -= l;
324 buf += l;
325 addr += l;
329 static void iommu_save(QEMUFile *f, void *opaque)
331 IOMMUState *s = opaque;
332 int i;
334 for (i = 0; i < IOMMU_NREGS; i++)
335 qemu_put_be32s(f, &s->regs[i]);
336 qemu_put_be64s(f, &s->iostart);
339 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
341 IOMMUState *s = opaque;
342 int i;
344 if (version_id != 2)
345 return -EINVAL;
347 for (i = 0; i < IOMMU_NREGS; i++)
348 qemu_get_be32s(f, &s->regs[i]);
349 qemu_get_be64s(f, &s->iostart);
351 return 0;
354 static void iommu_reset(void *opaque)
356 IOMMUState *s = opaque;
358 memset(s->regs, 0, IOMMU_NREGS * 4);
359 s->iostart = 0;
360 s->regs[IOMMU_CTRL] = s->version;
361 s->regs[IOMMU_ARBEN] = IOMMU_MID;
362 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
363 s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
364 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
365 qemu_irq_lower(s->irq);
368 void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
370 IOMMUState *s;
371 int iommu_io_memory;
373 s = qemu_mallocz(sizeof(IOMMUState));
374 if (!s)
375 return NULL;
377 s->version = version;
378 s->irq = irq;
380 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
381 iommu_mem_write, s);
382 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
384 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
385 qemu_register_reset(iommu_reset, s);
386 iommu_reset(s);
387 return s;