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Kill redundant declarion of perror()
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blobfc55b6facf780a16a830fc548eef12ce855a5264
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35 #include "qemu-kvm.h"
36
37 /*
38 * TODO:
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
46
47 /***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
53 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 // PCI 0x00: vendor, 0x02: device
178 #define PCI_VENDOR_CIRRUS 0x1013
179 #define PCI_DEVICE_CLGD5462 0x00d0
180 #define PCI_DEVICE_CLGD5465 0x00d6
181
182 // PCI 0x04: command(word), 0x06(word): status
183 #define PCI_COMMAND_IOACCESS 0x0001
184 #define PCI_COMMAND_MEMACCESS 0x0002
185 #define PCI_COMMAND_BUSMASTER 0x0004
186 #define PCI_COMMAND_SPECIALCYCLE 0x0008
187 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
188 #define PCI_COMMAND_PALETTESNOOPING 0x0020
189 #define PCI_COMMAND_PARITYDETECTION 0x0040
190 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
191 #define PCI_COMMAND_SERR 0x0100
192 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
193 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
194 #define PCI_CLASS_BASE_DISPLAY 0x03
195 // PCI 0x08, 0x00ff0000
196 #define PCI_CLASS_SUB_VGA 0x00
197 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
198 #define PCI_CLASS_HEADERTYPE_00h 0x00
199 // 0x10-0x3f (headertype 00h)
200 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
201 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
202 #define PCI_MAP_MEM 0x0
203 #define PCI_MAP_IO 0x1
204 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
205 #define PCI_MAP_IO_ADDR_MASK (~0x3)
206 #define PCI_MAP_MEMFLAGS_32BIT 0x0
207 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
208 #define PCI_MAP_MEMFLAGS_64BIT 0x4
209 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
210 // PCI 0x28: cardbus CIS pointer
211 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
212 // PCI 0x30: expansion ROM base address
213 #define PCI_ROMBIOS_ENABLED 0x1
214 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
215 // PCI 0x38: reserved
216 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
217
218 #define CIRRUS_PNPMMIO_SIZE 0x1000
219
220
221 /* I/O and memory hook */
222 #define CIRRUS_HOOK_NOT_HANDLED 0
223 #define CIRRUS_HOOK_HANDLED 1
224
225 #define ABS(a) ((signed)(a) > 0 ? a : -a)
226
227 #define BLTUNSAFE(s) \
228 ( \
229 ( /* check dst is within bounds */ \
230 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
231 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
232 (s)->vram_size \
233 ) || \
234 ( /* check src is within bounds */ \
235 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
236 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
237 (s)->vram_size \
238 ) \
239 )
240
241 struct CirrusVGAState;
242 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
243 uint8_t * dst, const uint8_t * src,
244 int dstpitch, int srcpitch,
245 int bltwidth, int bltheight);
246 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
247 uint8_t *dst, int dst_pitch, int width, int height);
248
249 typedef struct CirrusVGAState {
250 VGA_STATE_COMMON
251
252 int cirrus_linear_io_addr;
253 int cirrus_linear_bitblt_io_addr;
254 int cirrus_mmio_io_addr;
255 uint32_t cirrus_addr_mask;
256 uint32_t linear_mmio_mask;
257 uint8_t cirrus_shadow_gr0;
258 uint8_t cirrus_shadow_gr1;
259 uint8_t cirrus_hidden_dac_lockindex;
260 uint8_t cirrus_hidden_dac_data;
261 uint32_t cirrus_bank_base[2];
262 uint32_t cirrus_bank_limit[2];
263 uint8_t cirrus_hidden_palette[48];
264 uint32_t hw_cursor_x;
265 uint32_t hw_cursor_y;
266 int cirrus_blt_pixelwidth;
267 int cirrus_blt_width;
268 int cirrus_blt_height;
269 int cirrus_blt_dstpitch;
270 int cirrus_blt_srcpitch;
271 uint32_t cirrus_blt_fgcol;
272 uint32_t cirrus_blt_bgcol;
273 uint32_t cirrus_blt_dstaddr;
274 uint32_t cirrus_blt_srcaddr;
275 uint8_t cirrus_blt_mode;
276 uint8_t cirrus_blt_modeext;
277 cirrus_bitblt_rop_t cirrus_rop;
278 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
279 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
280 uint8_t *cirrus_srcptr;
281 uint8_t *cirrus_srcptr_end;
282 uint32_t cirrus_srccounter;
283 /* hwcursor display state */
284 int last_hw_cursor_size;
285 int last_hw_cursor_x;
286 int last_hw_cursor_y;
287 int last_hw_cursor_y_start;
288 int last_hw_cursor_y_end;
289 int real_vram_size; /* XXX: suppress that */
290 CPUWriteMemoryFunc **cirrus_linear_write;
291 int device_id;
292 int bustype;
293 } CirrusVGAState;
294
295 typedef struct PCICirrusVGAState {
296 PCIDevice dev;
297 CirrusVGAState cirrus_vga;
298 } PCICirrusVGAState;
299
300 static uint8_t rop_to_index[256];
301
302 /***************************************
303 *
304 * prototypes.
305 *
306 ***************************************/
307
308
309 static void cirrus_bitblt_reset(CirrusVGAState *s);
310 static void cirrus_update_memory_access(CirrusVGAState *s);
311
312 /***************************************
313 *
314 * raster operations
315 *
316 ***************************************/
317
318 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
319 uint8_t *dst,const uint8_t *src,
320 int dstpitch,int srcpitch,
321 int bltwidth,int bltheight)
322 {
323 }
324
325 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
326 uint8_t *dst,
327 int dstpitch, int bltwidth,int bltheight)
328 {
329 }
330
331 #define ROP_NAME 0
332 #define ROP_OP(d, s) d = 0
333 #include "cirrus_vga_rop.h"
334
335 #define ROP_NAME src_and_dst
336 #define ROP_OP(d, s) d = (s) & (d)
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_and_notdst
340 #define ROP_OP(d, s) d = (s) & (~(d))
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME notdst
344 #define ROP_OP(d, s) d = ~(d)
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME src
348 #define ROP_OP(d, s) d = s
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME 1
352 #define ROP_OP(d, s) d = ~0
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME notsrc_and_dst
356 #define ROP_OP(d, s) d = (~(s)) & (d)
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME src_xor_dst
360 #define ROP_OP(d, s) d = (s) ^ (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME src_or_dst
364 #define ROP_OP(d, s) d = (s) | (d)
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME notsrc_or_notdst
368 #define ROP_OP(d, s) d = (~(s)) | (~(d))
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME src_notxor_dst
372 #define ROP_OP(d, s) d = ~((s) ^ (d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME src_or_notdst
376 #define ROP_OP(d, s) d = (s) | (~(d))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME notsrc
380 #define ROP_OP(d, s) d = (~(s))
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc_or_dst
384 #define ROP_OP(d, s) d = (~(s)) | (d)
385 #include "cirrus_vga_rop.h"
386
387 #define ROP_NAME notsrc_and_notdst
388 #define ROP_OP(d, s) d = (~(s)) & (~(d))
389 #include "cirrus_vga_rop.h"
390
391 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
392 cirrus_bitblt_rop_fwd_0,
393 cirrus_bitblt_rop_fwd_src_and_dst,
394 cirrus_bitblt_rop_nop,
395 cirrus_bitblt_rop_fwd_src_and_notdst,
396 cirrus_bitblt_rop_fwd_notdst,
397 cirrus_bitblt_rop_fwd_src,
398 cirrus_bitblt_rop_fwd_1,
399 cirrus_bitblt_rop_fwd_notsrc_and_dst,
400 cirrus_bitblt_rop_fwd_src_xor_dst,
401 cirrus_bitblt_rop_fwd_src_or_dst,
402 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
403 cirrus_bitblt_rop_fwd_src_notxor_dst,
404 cirrus_bitblt_rop_fwd_src_or_notdst,
405 cirrus_bitblt_rop_fwd_notsrc,
406 cirrus_bitblt_rop_fwd_notsrc_or_dst,
407 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
408 };
409
410 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
411 cirrus_bitblt_rop_bkwd_0,
412 cirrus_bitblt_rop_bkwd_src_and_dst,
413 cirrus_bitblt_rop_nop,
414 cirrus_bitblt_rop_bkwd_src_and_notdst,
415 cirrus_bitblt_rop_bkwd_notdst,
416 cirrus_bitblt_rop_bkwd_src,
417 cirrus_bitblt_rop_bkwd_1,
418 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
419 cirrus_bitblt_rop_bkwd_src_xor_dst,
420 cirrus_bitblt_rop_bkwd_src_or_dst,
421 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
422 cirrus_bitblt_rop_bkwd_src_notxor_dst,
423 cirrus_bitblt_rop_bkwd_src_or_notdst,
424 cirrus_bitblt_rop_bkwd_notsrc,
425 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
426 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
427 };
428
429 #define TRANSP_ROP(name) {\
430 name ## _8,\
431 name ## _16,\
432 }
433 #define TRANSP_NOP(func) {\
434 func,\
435 func,\
436 }
437
438 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
441 TRANSP_NOP(cirrus_bitblt_rop_nop),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
455 };
456
457 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
460 TRANSP_NOP(cirrus_bitblt_rop_nop),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
474 };
475
476 #define ROP2(name) {\
477 name ## _8,\
478 name ## _16,\
479 name ## _24,\
480 name ## _32,\
481 }
482
483 #define ROP_NOP2(func) {\
484 func,\
485 func,\
486 func,\
487 func,\
488 }
489
490 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
491 ROP2(cirrus_patternfill_0),
492 ROP2(cirrus_patternfill_src_and_dst),
493 ROP_NOP2(cirrus_bitblt_rop_nop),
494 ROP2(cirrus_patternfill_src_and_notdst),
495 ROP2(cirrus_patternfill_notdst),
496 ROP2(cirrus_patternfill_src),
497 ROP2(cirrus_patternfill_1),
498 ROP2(cirrus_patternfill_notsrc_and_dst),
499 ROP2(cirrus_patternfill_src_xor_dst),
500 ROP2(cirrus_patternfill_src_or_dst),
501 ROP2(cirrus_patternfill_notsrc_or_notdst),
502 ROP2(cirrus_patternfill_src_notxor_dst),
503 ROP2(cirrus_patternfill_src_or_notdst),
504 ROP2(cirrus_patternfill_notsrc),
505 ROP2(cirrus_patternfill_notsrc_or_dst),
506 ROP2(cirrus_patternfill_notsrc_and_notdst),
507 };
508
509 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
510 ROP2(cirrus_colorexpand_transp_0),
511 ROP2(cirrus_colorexpand_transp_src_and_dst),
512 ROP_NOP2(cirrus_bitblt_rop_nop),
513 ROP2(cirrus_colorexpand_transp_src_and_notdst),
514 ROP2(cirrus_colorexpand_transp_notdst),
515 ROP2(cirrus_colorexpand_transp_src),
516 ROP2(cirrus_colorexpand_transp_1),
517 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
518 ROP2(cirrus_colorexpand_transp_src_xor_dst),
519 ROP2(cirrus_colorexpand_transp_src_or_dst),
520 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
521 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
522 ROP2(cirrus_colorexpand_transp_src_or_notdst),
523 ROP2(cirrus_colorexpand_transp_notsrc),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
525 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
526 };
527
528 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
529 ROP2(cirrus_colorexpand_0),
530 ROP2(cirrus_colorexpand_src_and_dst),
531 ROP_NOP2(cirrus_bitblt_rop_nop),
532 ROP2(cirrus_colorexpand_src_and_notdst),
533 ROP2(cirrus_colorexpand_notdst),
534 ROP2(cirrus_colorexpand_src),
535 ROP2(cirrus_colorexpand_1),
536 ROP2(cirrus_colorexpand_notsrc_and_dst),
537 ROP2(cirrus_colorexpand_src_xor_dst),
538 ROP2(cirrus_colorexpand_src_or_dst),
539 ROP2(cirrus_colorexpand_notsrc_or_notdst),
540 ROP2(cirrus_colorexpand_src_notxor_dst),
541 ROP2(cirrus_colorexpand_src_or_notdst),
542 ROP2(cirrus_colorexpand_notsrc),
543 ROP2(cirrus_colorexpand_notsrc_or_dst),
544 ROP2(cirrus_colorexpand_notsrc_and_notdst),
545 };
546
547 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
548 ROP2(cirrus_colorexpand_pattern_transp_0),
549 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
550 ROP_NOP2(cirrus_bitblt_rop_nop),
551 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_src),
554 ROP2(cirrus_colorexpand_pattern_transp_1),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
559 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
560 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
563 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
564 };
565
566 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
567 ROP2(cirrus_colorexpand_pattern_0),
568 ROP2(cirrus_colorexpand_pattern_src_and_dst),
569 ROP_NOP2(cirrus_bitblt_rop_nop),
570 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
571 ROP2(cirrus_colorexpand_pattern_notdst),
572 ROP2(cirrus_colorexpand_pattern_src),
573 ROP2(cirrus_colorexpand_pattern_1),
574 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
575 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
576 ROP2(cirrus_colorexpand_pattern_src_or_dst),
577 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
578 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
579 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
580 ROP2(cirrus_colorexpand_pattern_notsrc),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
582 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
583 };
584
585 static const cirrus_fill_t cirrus_fill[16][4] = {
586 ROP2(cirrus_fill_0),
587 ROP2(cirrus_fill_src_and_dst),
588 ROP_NOP2(cirrus_bitblt_fill_nop),
589 ROP2(cirrus_fill_src_and_notdst),
590 ROP2(cirrus_fill_notdst),
591 ROP2(cirrus_fill_src),
592 ROP2(cirrus_fill_1),
593 ROP2(cirrus_fill_notsrc_and_dst),
594 ROP2(cirrus_fill_src_xor_dst),
595 ROP2(cirrus_fill_src_or_dst),
596 ROP2(cirrus_fill_notsrc_or_notdst),
597 ROP2(cirrus_fill_src_notxor_dst),
598 ROP2(cirrus_fill_src_or_notdst),
599 ROP2(cirrus_fill_notsrc),
600 ROP2(cirrus_fill_notsrc_or_dst),
601 ROP2(cirrus_fill_notsrc_and_notdst),
602 };
603
604 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
605 {
606 unsigned int color;
607 switch (s->cirrus_blt_pixelwidth) {
608 case 1:
609 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
610 break;
611 case 2:
612 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
613 s->cirrus_blt_fgcol = le16_to_cpu(color);
614 break;
615 case 3:
616 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
617 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
618 break;
619 default:
620 case 4:
621 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
622 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
623 s->cirrus_blt_fgcol = le32_to_cpu(color);
624 break;
625 }
626 }
627
628 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
629 {
630 unsigned int color;
631 switch (s->cirrus_blt_pixelwidth) {
632 case 1:
633 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
634 break;
635 case 2:
636 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
637 s->cirrus_blt_bgcol = le16_to_cpu(color);
638 break;
639 case 3:
640 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
641 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
642 break;
643 default:
644 case 4:
645 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
646 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
647 s->cirrus_blt_bgcol = le32_to_cpu(color);
648 break;
649 }
650 }
651
652 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
653 int off_pitch, int bytesperline,
654 int lines)
655 {
656 int y;
657 int off_cur;
658 int off_cur_end;
659
660 for (y = 0; y < lines; y++) {
661 off_cur = off_begin;
662 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
663 off_cur &= TARGET_PAGE_MASK;
664 while (off_cur < off_cur_end) {
665 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
666 off_cur += TARGET_PAGE_SIZE;
667 }
668 off_begin += off_pitch;
669 }
670 }
671
672 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
673 const uint8_t * src)
674 {
675 uint8_t *dst;
676
677 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
678
679 if (BLTUNSAFE(s))
680 return 0;
681
682 (*s->cirrus_rop) (s, dst, src,
683 s->cirrus_blt_dstpitch, 0,
684 s->cirrus_blt_width, s->cirrus_blt_height);
685 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
686 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
687 s->cirrus_blt_height);
688 return 1;
689 }
690
691 /* fill */
692
693 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
694 {
695 cirrus_fill_t rop_func;
696
697 if (BLTUNSAFE(s))
698 return 0;
699 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
700 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
701 s->cirrus_blt_dstpitch,
702 s->cirrus_blt_width, s->cirrus_blt_height);
703 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
704 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
705 s->cirrus_blt_height);
706 cirrus_bitblt_reset(s);
707 return 1;
708 }
709
710 /***************************************
711 *
712 * bitblt (video-to-video)
713 *
714 ***************************************/
715
716 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
717 {
718 return cirrus_bitblt_common_patterncopy(s,
719 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
720 s->cirrus_addr_mask));
721 }
722
723 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
724 {
725 int sx, sy;
726 int dx, dy;
727 int width, height;
728 int depth;
729 int notify = 0;
730
731 depth = s->get_bpp((VGAState *)s) / 8;
732 s->get_resolution((VGAState *)s, &width, &height);
733
734 /* extra x, y */
735 sx = (src % (width * depth)) / depth;
736 sy = (src / (width * depth));
737 dx = (dst % (width *depth)) / depth;
738 dy = (dst / (width * depth));
739
740 /* normalize width */
741 w /= depth;
742
743 /* if we're doing a backward copy, we have to adjust
744 our x/y to be the upper left corner (instead of the lower
745 right corner) */
746 if (s->cirrus_blt_dstpitch < 0) {
747 sx -= (s->cirrus_blt_width / depth) - 1;
748 dx -= (s->cirrus_blt_width / depth) - 1;
749 sy -= s->cirrus_blt_height - 1;
750 dy -= s->cirrus_blt_height - 1;
751 }
752
753 /* are we in the visible portion of memory? */
754 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
755 (sx + w) <= width && (sy + h) <= height &&
756 (dx + w) <= width && (dy + h) <= height) {
757 notify = 1;
758 }
759
760 /* make to sure only copy if it's a plain copy ROP */
761 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
762 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
763 notify = 0;
764
765 /* we have to flush all pending changes so that the copy
766 is generated at the appropriate moment in time */
767 if (notify)
768 vga_hw_update();
769
770 (*s->cirrus_rop) (s, s->vram_ptr +
771 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
772 s->vram_ptr +
773 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
774 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
775 s->cirrus_blt_width, s->cirrus_blt_height);
776
777 if (notify)
778 qemu_console_copy(s->console,
779 sx, sy, dx, dy,
780 s->cirrus_blt_width / depth,
781 s->cirrus_blt_height);
782
783 /* we don't have to notify the display that this portion has
784 changed since qemu_console_copy implies this */
785
786 if (!notify)
787 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
788 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
789 s->cirrus_blt_height);
790 }
791
792 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
793 {
794 if (BLTUNSAFE(s))
795 return 0;
796
797 if (s->ds->dpy_copy) {
798 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
799 s->cirrus_blt_srcaddr - s->start_addr,
800 s->cirrus_blt_width, s->cirrus_blt_height);
801 } else {
802 (*s->cirrus_rop) (s, s->vram_ptr +
803 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
804 s->vram_ptr +
805 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
806 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
807 s->cirrus_blt_width, s->cirrus_blt_height);
808
809 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
810 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
811 s->cirrus_blt_height);
812 }
813
814 return 1;
815 }
816
817 /***************************************
818 *
819 * bitblt (cpu-to-video)
820 *
821 ***************************************/
822
823 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
824 {
825 int copy_count;
826 uint8_t *end_ptr;
827
828 if (s->cirrus_srccounter > 0) {
829 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
830 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
831 the_end:
832 s->cirrus_srccounter = 0;
833 cirrus_bitblt_reset(s);
834 } else {
835 /* at least one scan line */
836 do {
837 (*s->cirrus_rop)(s, s->vram_ptr +
838 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
839 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
840 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
841 s->cirrus_blt_width, 1);
842 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
843 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
844 if (s->cirrus_srccounter <= 0)
845 goto the_end;
846 /* more bytes than needed can be transfered because of
847 word alignment, so we keep them for the next line */
848 /* XXX: keep alignment to speed up transfer */
849 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
850 copy_count = s->cirrus_srcptr_end - end_ptr;
851 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
852 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
853 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
854 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
855 }
856 }
857 }
858
859 /***************************************
860 *
861 * bitblt wrapper
862 *
863 ***************************************/
864
865 static void cirrus_bitblt_reset(CirrusVGAState * s)
866 {
867 int need_update;
868
869 s->gr[0x31] &=
870 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
871 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
872 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
873 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
874 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
875 s->cirrus_srccounter = 0;
876 if (!need_update)
877 return;
878 cirrus_update_memory_access(s);
879 }
880
881 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
882 {
883 int w;
884
885 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
886 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
887 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
888
889 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
890 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
891 s->cirrus_blt_srcpitch = 8;
892 } else {
893 /* XXX: check for 24 bpp */
894 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
895 }
896 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
897 } else {
898 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
899 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
900 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
901 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
902 else
903 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
904 } else {
905 /* always align input size to 32 bits */
906 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
907 }
908 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
909 }
910 s->cirrus_srcptr = s->cirrus_bltbuf;
911 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
912 cirrus_update_memory_access(s);
913 return 1;
914 }
915
916 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
917 {
918 /* XXX */
919 #ifdef DEBUG_BITBLT
920 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
921 #endif
922 return 0;
923 }
924
925 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
926 {
927 int ret;
928
929 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
930 ret = cirrus_bitblt_videotovideo_patterncopy(s);
931 } else {
932 ret = cirrus_bitblt_videotovideo_copy(s);
933 }
934 if (ret)
935 cirrus_bitblt_reset(s);
936 return ret;
937 }
938
939 static void cirrus_bitblt_start(CirrusVGAState * s)
940 {
941 uint8_t blt_rop;
942
943 s->gr[0x31] |= CIRRUS_BLT_BUSY;
944
945 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
946 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
947 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
948 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
949 s->cirrus_blt_dstaddr =
950 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
951 s->cirrus_blt_srcaddr =
952 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
953 s->cirrus_blt_mode = s->gr[0x30];
954 s->cirrus_blt_modeext = s->gr[0x33];
955 blt_rop = s->gr[0x32];
956
957 #ifdef DEBUG_BITBLT
958 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
959 blt_rop,
960 s->cirrus_blt_mode,
961 s->cirrus_blt_modeext,
962 s->cirrus_blt_width,
963 s->cirrus_blt_height,
964 s->cirrus_blt_dstpitch,
965 s->cirrus_blt_srcpitch,
966 s->cirrus_blt_dstaddr,
967 s->cirrus_blt_srcaddr,
968 s->gr[0x2f]);
969 #endif
970
971 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
972 case CIRRUS_BLTMODE_PIXELWIDTH8:
973 s->cirrus_blt_pixelwidth = 1;
974 break;
975 case CIRRUS_BLTMODE_PIXELWIDTH16:
976 s->cirrus_blt_pixelwidth = 2;
977 break;
978 case CIRRUS_BLTMODE_PIXELWIDTH24:
979 s->cirrus_blt_pixelwidth = 3;
980 break;
981 case CIRRUS_BLTMODE_PIXELWIDTH32:
982 s->cirrus_blt_pixelwidth = 4;
983 break;
984 default:
985 #ifdef DEBUG_BITBLT
986 printf("cirrus: bitblt - pixel width is unknown\n");
987 #endif
988 goto bitblt_ignore;
989 }
990 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
991
992 if ((s->
993 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
994 CIRRUS_BLTMODE_MEMSYSDEST))
995 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
996 #ifdef DEBUG_BITBLT
997 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
998 #endif
999 goto bitblt_ignore;
1000 }
1001
1002 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1003 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1004 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1005 CIRRUS_BLTMODE_PATTERNCOPY |
1006 CIRRUS_BLTMODE_COLOREXPAND)) ==
1007 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1008 cirrus_bitblt_fgcol(s);
1009 cirrus_bitblt_solidfill(s, blt_rop);
1010 } else {
1011 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1012 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1013 CIRRUS_BLTMODE_COLOREXPAND) {
1014
1015 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1016 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1017 cirrus_bitblt_bgcol(s);
1018 else
1019 cirrus_bitblt_fgcol(s);
1020 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1021 } else {
1022 cirrus_bitblt_fgcol(s);
1023 cirrus_bitblt_bgcol(s);
1024 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1025 }
1026 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1027 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1028 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1029 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1030 cirrus_bitblt_bgcol(s);
1031 else
1032 cirrus_bitblt_fgcol(s);
1033 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1034 } else {
1035 cirrus_bitblt_fgcol(s);
1036 cirrus_bitblt_bgcol(s);
1037 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1038 }
1039 } else {
1040 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1041 }
1042 } else {
1043 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1044 if (s->cirrus_blt_pixelwidth > 2) {
1045 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1046 goto bitblt_ignore;
1047 }
1048 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1049 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1050 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1051 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1052 } else {
1053 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1054 }
1055 } else {
1056 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1057 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1058 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1059 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1060 } else {
1061 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1062 }
1063 }
1064 }
1065 // setup bitblt engine.
1066 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1067 if (!cirrus_bitblt_cputovideo(s))
1068 goto bitblt_ignore;
1069 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1070 if (!cirrus_bitblt_videotocpu(s))
1071 goto bitblt_ignore;
1072 } else {
1073 if (!cirrus_bitblt_videotovideo(s))
1074 goto bitblt_ignore;
1075 }
1076 }
1077 return;
1078 bitblt_ignore:;
1079 cirrus_bitblt_reset(s);
1080 }
1081
1082 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1083 {
1084 unsigned old_value;
1085
1086 old_value = s->gr[0x31];
1087 s->gr[0x31] = reg_value;
1088
1089 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1090 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1091 cirrus_bitblt_reset(s);
1092 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1093 ((reg_value & CIRRUS_BLT_START) != 0)) {
1094 cirrus_bitblt_start(s);
1095 }
1096 }
1097
1098
1099 /***************************************
1100 *
1101 * basic parameters
1102 *
1103 ***************************************/
1104
1105 static void cirrus_get_offsets(VGAState *s1,
1106 uint32_t *pline_offset,
1107 uint32_t *pstart_addr,
1108 uint32_t *pline_compare)
1109 {
1110 CirrusVGAState * s = (CirrusVGAState *)s1;
1111 uint32_t start_addr, line_offset, line_compare;
1112
1113 line_offset = s->cr[0x13]
1114 | ((s->cr[0x1b] & 0x10) << 4);
1115 line_offset <<= 3;
1116 *pline_offset = line_offset;
1117
1118 start_addr = (s->cr[0x0c] << 8)
1119 | s->cr[0x0d]
1120 | ((s->cr[0x1b] & 0x01) << 16)
1121 | ((s->cr[0x1b] & 0x0c) << 15)
1122 | ((s->cr[0x1d] & 0x80) << 12);
1123 *pstart_addr = start_addr;
1124
1125 line_compare = s->cr[0x18] |
1126 ((s->cr[0x07] & 0x10) << 4) |
1127 ((s->cr[0x09] & 0x40) << 3);
1128 *pline_compare = line_compare;
1129 }
1130
1131 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1132 {
1133 uint32_t ret = 16;
1134
1135 switch (s->cirrus_hidden_dac_data & 0xf) {
1136 case 0:
1137 ret = 15;
1138 break; /* Sierra HiColor */
1139 case 1:
1140 ret = 16;
1141 break; /* XGA HiColor */
1142 default:
1143 #ifdef DEBUG_CIRRUS
1144 printf("cirrus: invalid DAC value %x in 16bpp\n",
1145 (s->cirrus_hidden_dac_data & 0xf));
1146 #endif
1147 ret = 15; /* XXX */
1148 break;
1149 }
1150 return ret;
1151 }
1152
1153 static int cirrus_get_bpp(VGAState *s1)
1154 {
1155 CirrusVGAState * s = (CirrusVGAState *)s1;
1156 uint32_t ret = 8;
1157
1158 if ((s->sr[0x07] & 0x01) != 0) {
1159 /* Cirrus SVGA */
1160 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1161 case CIRRUS_SR7_BPP_8:
1162 ret = 8;
1163 break;
1164 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1165 ret = cirrus_get_bpp16_depth(s);
1166 break;
1167 case CIRRUS_SR7_BPP_24:
1168 ret = 24;
1169 break;
1170 case CIRRUS_SR7_BPP_16:
1171 ret = cirrus_get_bpp16_depth(s);
1172 break;
1173 case CIRRUS_SR7_BPP_32:
1174 ret = 32;
1175 break;
1176 default:
1177 #ifdef DEBUG_CIRRUS
1178 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1179 #endif
1180 ret = 8;
1181 break;
1182 }
1183 } else {
1184 /* VGA */
1185 ret = 0;
1186 }
1187
1188 return ret;
1189 }
1190
1191 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1192 {
1193 int width, height;
1194
1195 width = (s->cr[0x01] + 1) * 8;
1196 height = s->cr[0x12] |
1197 ((s->cr[0x07] & 0x02) << 7) |
1198 ((s->cr[0x07] & 0x40) << 3);
1199 height = (height + 1);
1200 /* interlace support */
1201 if (s->cr[0x1a] & 0x01)
1202 height = height * 2;
1203 *pwidth = width;
1204 *pheight = height;
1205 }
1206
1207 /***************************************
1208 *
1209 * bank memory
1210 *
1211 ***************************************/
1212
1213 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1214 {
1215 unsigned offset;
1216 unsigned limit;
1217
1218 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1219 offset = s->gr[0x09 + bank_index];
1220 else /* single bank */
1221 offset = s->gr[0x09];
1222
1223 if ((s->gr[0x0b] & 0x20) != 0)
1224 offset <<= 14;
1225 else
1226 offset <<= 12;
1227
1228 if (s->real_vram_size <= offset)
1229 limit = 0;
1230 else
1231 limit = s->real_vram_size - offset;
1232
1233 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1234 if (limit > 0x8000) {
1235 offset += 0x8000;
1236 limit -= 0x8000;
1237 } else {
1238 limit = 0;
1239 }
1240 }
1241
1242 if (limit > 0) {
1243 /* Thinking about changing bank base? First, drop the dirty bitmap information
1244 * on the current location, otherwise we lose this pointer forever */
1245 if (s->lfb_vram_mapped) {
1246 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1247 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1248 }
1249 s->cirrus_bank_base[bank_index] = offset;
1250 s->cirrus_bank_limit[bank_index] = limit;
1251 } else {
1252 s->cirrus_bank_base[bank_index] = 0;
1253 s->cirrus_bank_limit[bank_index] = 0;
1254 }
1255 }
1256
1257 /***************************************
1258 *
1259 * I/O access between 0x3c4-0x3c5
1260 *
1261 ***************************************/
1262
1263 static int
1264 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1265 {
1266 switch (reg_index) {
1267 case 0x00: // Standard VGA
1268 case 0x01: // Standard VGA
1269 case 0x02: // Standard VGA
1270 case 0x03: // Standard VGA
1271 case 0x04: // Standard VGA
1272 return CIRRUS_HOOK_NOT_HANDLED;
1273 case 0x06: // Unlock Cirrus extensions
1274 *reg_value = s->sr[reg_index];
1275 break;
1276 case 0x10:
1277 case 0x30:
1278 case 0x50:
1279 case 0x70: // Graphics Cursor X
1280 case 0x90:
1281 case 0xb0:
1282 case 0xd0:
1283 case 0xf0: // Graphics Cursor X
1284 *reg_value = s->sr[0x10];
1285 break;
1286 case 0x11:
1287 case 0x31:
1288 case 0x51:
1289 case 0x71: // Graphics Cursor Y
1290 case 0x91:
1291 case 0xb1:
1292 case 0xd1:
1293 case 0xf1: // Graphics Cursor Y
1294 *reg_value = s->sr[0x11];
1295 break;
1296 case 0x05: // ???
1297 case 0x07: // Extended Sequencer Mode
1298 case 0x08: // EEPROM Control
1299 case 0x09: // Scratch Register 0
1300 case 0x0a: // Scratch Register 1
1301 case 0x0b: // VCLK 0
1302 case 0x0c: // VCLK 1
1303 case 0x0d: // VCLK 2
1304 case 0x0e: // VCLK 3
1305 case 0x0f: // DRAM Control
1306 case 0x12: // Graphics Cursor Attribute
1307 case 0x13: // Graphics Cursor Pattern Address
1308 case 0x14: // Scratch Register 2
1309 case 0x15: // Scratch Register 3
1310 case 0x16: // Performance Tuning Register
1311 case 0x17: // Configuration Readback and Extended Control
1312 case 0x18: // Signature Generator Control
1313 case 0x19: // Signal Generator Result
1314 case 0x1a: // Signal Generator Result
1315 case 0x1b: // VCLK 0 Denominator & Post
1316 case 0x1c: // VCLK 1 Denominator & Post
1317 case 0x1d: // VCLK 2 Denominator & Post
1318 case 0x1e: // VCLK 3 Denominator & Post
1319 case 0x1f: // BIOS Write Enable and MCLK select
1320 #ifdef DEBUG_CIRRUS
1321 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1322 #endif
1323 *reg_value = s->sr[reg_index];
1324 break;
1325 default:
1326 #ifdef DEBUG_CIRRUS
1327 printf("cirrus: inport sr_index %02x\n", reg_index);
1328 #endif
1329 *reg_value = 0xff;
1330 break;
1331 }
1332
1333 return CIRRUS_HOOK_HANDLED;
1334 }
1335
1336 static int
1337 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1338 {
1339 switch (reg_index) {
1340 case 0x00: // Standard VGA
1341 case 0x01: // Standard VGA
1342 case 0x02: // Standard VGA
1343 case 0x03: // Standard VGA
1344 case 0x04: // Standard VGA
1345 return CIRRUS_HOOK_NOT_HANDLED;
1346 case 0x06: // Unlock Cirrus extensions
1347 reg_value &= 0x17;
1348 if (reg_value == 0x12) {
1349 s->sr[reg_index] = 0x12;
1350 } else {
1351 s->sr[reg_index] = 0x0f;
1352 }
1353 break;
1354 case 0x10:
1355 case 0x30:
1356 case 0x50:
1357 case 0x70: // Graphics Cursor X
1358 case 0x90:
1359 case 0xb0:
1360 case 0xd0:
1361 case 0xf0: // Graphics Cursor X
1362 s->sr[0x10] = reg_value;
1363 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1364 break;
1365 case 0x11:
1366 case 0x31:
1367 case 0x51:
1368 case 0x71: // Graphics Cursor Y
1369 case 0x91:
1370 case 0xb1:
1371 case 0xd1:
1372 case 0xf1: // Graphics Cursor Y
1373 s->sr[0x11] = reg_value;
1374 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1375 break;
1376 case 0x07: // Extended Sequencer Mode
1377 cirrus_update_memory_access(s);
1378 case 0x08: // EEPROM Control
1379 case 0x09: // Scratch Register 0
1380 case 0x0a: // Scratch Register 1
1381 case 0x0b: // VCLK 0
1382 case 0x0c: // VCLK 1
1383 case 0x0d: // VCLK 2
1384 case 0x0e: // VCLK 3
1385 case 0x0f: // DRAM Control
1386 case 0x12: // Graphics Cursor Attribute
1387 case 0x13: // Graphics Cursor Pattern Address
1388 case 0x14: // Scratch Register 2
1389 case 0x15: // Scratch Register 3
1390 case 0x16: // Performance Tuning Register
1391 case 0x18: // Signature Generator Control
1392 case 0x19: // Signature Generator Result
1393 case 0x1a: // Signature Generator Result
1394 case 0x1b: // VCLK 0 Denominator & Post
1395 case 0x1c: // VCLK 1 Denominator & Post
1396 case 0x1d: // VCLK 2 Denominator & Post
1397 case 0x1e: // VCLK 3 Denominator & Post
1398 case 0x1f: // BIOS Write Enable and MCLK select
1399 s->sr[reg_index] = reg_value;
1400 #ifdef DEBUG_CIRRUS
1401 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1402 reg_index, reg_value);
1403 #endif
1404 if (reg_index == 0x07)
1405 cirrus_update_memory_access(s);
1406 break;
1407 case 0x17: // Configuration Readback and Extended Control
1408 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1409 cirrus_update_memory_access(s);
1410 break;
1411 default:
1412 #ifdef DEBUG_CIRRUS
1413 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1414 reg_value);
1415 #endif
1416 break;
1417 }
1418
1419 return CIRRUS_HOOK_HANDLED;
1420 }
1421
1422 /***************************************
1423 *
1424 * I/O access at 0x3c6
1425 *
1426 ***************************************/
1427
1428 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1429 {
1430 *reg_value = 0xff;
1431 if (++s->cirrus_hidden_dac_lockindex == 5) {
1432 *reg_value = s->cirrus_hidden_dac_data;
1433 s->cirrus_hidden_dac_lockindex = 0;
1434 }
1435 }
1436
1437 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1438 {
1439 if (s->cirrus_hidden_dac_lockindex == 4) {
1440 s->cirrus_hidden_dac_data = reg_value;
1441 #if defined(DEBUG_CIRRUS)
1442 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1443 #endif
1444 }
1445 s->cirrus_hidden_dac_lockindex = 0;
1446 }
1447
1448 /***************************************
1449 *
1450 * I/O access at 0x3c9
1451 *
1452 ***************************************/
1453
1454 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1455 {
1456 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1457 return CIRRUS_HOOK_NOT_HANDLED;
1458 *reg_value =
1459 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1460 s->dac_sub_index];
1461 if (++s->dac_sub_index == 3) {
1462 s->dac_sub_index = 0;
1463 s->dac_read_index++;
1464 }
1465 return CIRRUS_HOOK_HANDLED;
1466 }
1467
1468 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1469 {
1470 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1471 return CIRRUS_HOOK_NOT_HANDLED;
1472 s->dac_cache[s->dac_sub_index] = reg_value;
1473 if (++s->dac_sub_index == 3) {
1474 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1475 s->dac_cache, 3);
1476 /* XXX update cursor */
1477 s->dac_sub_index = 0;
1478 s->dac_write_index++;
1479 }
1480 return CIRRUS_HOOK_HANDLED;
1481 }
1482
1483 /***************************************
1484 *
1485 * I/O access between 0x3ce-0x3cf
1486 *
1487 ***************************************/
1488
1489 static int
1490 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1491 {
1492 switch (reg_index) {
1493 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1494 *reg_value = s->cirrus_shadow_gr0;
1495 return CIRRUS_HOOK_HANDLED;
1496 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1497 *reg_value = s->cirrus_shadow_gr1;
1498 return CIRRUS_HOOK_HANDLED;
1499 case 0x02: // Standard VGA
1500 case 0x03: // Standard VGA
1501 case 0x04: // Standard VGA
1502 case 0x06: // Standard VGA
1503 case 0x07: // Standard VGA
1504 case 0x08: // Standard VGA
1505 return CIRRUS_HOOK_NOT_HANDLED;
1506 case 0x05: // Standard VGA, Cirrus extended mode
1507 default:
1508 break;
1509 }
1510
1511 if (reg_index < 0x3a) {
1512 *reg_value = s->gr[reg_index];
1513 } else {
1514 #ifdef DEBUG_CIRRUS
1515 printf("cirrus: inport gr_index %02x\n", reg_index);
1516 #endif
1517 *reg_value = 0xff;
1518 }
1519
1520 return CIRRUS_HOOK_HANDLED;
1521 }
1522
1523 static int
1524 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1525 {
1526 #if defined(DEBUG_BITBLT) && 0
1527 printf("gr%02x: %02x\n", reg_index, reg_value);
1528 #endif
1529 switch (reg_index) {
1530 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1531 s->cirrus_shadow_gr0 = reg_value;
1532 return CIRRUS_HOOK_NOT_HANDLED;
1533 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1534 s->cirrus_shadow_gr1 = reg_value;
1535 return CIRRUS_HOOK_NOT_HANDLED;
1536 case 0x02: // Standard VGA
1537 case 0x03: // Standard VGA
1538 case 0x04: // Standard VGA
1539 case 0x06: // Standard VGA
1540 case 0x07: // Standard VGA
1541 case 0x08: // Standard VGA
1542 return CIRRUS_HOOK_NOT_HANDLED;
1543 case 0x05: // Standard VGA, Cirrus extended mode
1544 s->gr[reg_index] = reg_value & 0x7f;
1545 cirrus_update_memory_access(s);
1546 break;
1547 case 0x09: // bank offset #0
1548 case 0x0A: // bank offset #1
1549 s->gr[reg_index] = reg_value;
1550 cirrus_update_bank_ptr(s, 0);
1551 cirrus_update_bank_ptr(s, 1);
1552 cirrus_update_memory_access(s);
1553 break;
1554 case 0x0B:
1555 s->gr[reg_index] = reg_value;
1556 cirrus_update_bank_ptr(s, 0);
1557 cirrus_update_bank_ptr(s, 1);
1558 cirrus_update_memory_access(s);
1559 break;
1560 case 0x10: // BGCOLOR 0x0000ff00
1561 case 0x11: // FGCOLOR 0x0000ff00
1562 case 0x12: // BGCOLOR 0x00ff0000
1563 case 0x13: // FGCOLOR 0x00ff0000
1564 case 0x14: // BGCOLOR 0xff000000
1565 case 0x15: // FGCOLOR 0xff000000
1566 case 0x20: // BLT WIDTH 0x0000ff
1567 case 0x22: // BLT HEIGHT 0x0000ff
1568 case 0x24: // BLT DEST PITCH 0x0000ff
1569 case 0x26: // BLT SRC PITCH 0x0000ff
1570 case 0x28: // BLT DEST ADDR 0x0000ff
1571 case 0x29: // BLT DEST ADDR 0x00ff00
1572 case 0x2c: // BLT SRC ADDR 0x0000ff
1573 case 0x2d: // BLT SRC ADDR 0x00ff00
1574 case 0x2f: // BLT WRITEMASK
1575 case 0x30: // BLT MODE
1576 case 0x32: // RASTER OP
1577 case 0x33: // BLT MODEEXT
1578 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1579 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1580 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1581 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1582 s->gr[reg_index] = reg_value;
1583 break;
1584 case 0x21: // BLT WIDTH 0x001f00
1585 case 0x23: // BLT HEIGHT 0x001f00
1586 case 0x25: // BLT DEST PITCH 0x001f00
1587 case 0x27: // BLT SRC PITCH 0x001f00
1588 s->gr[reg_index] = reg_value & 0x1f;
1589 break;
1590 case 0x2a: // BLT DEST ADDR 0x3f0000
1591 s->gr[reg_index] = reg_value & 0x3f;
1592 /* if auto start mode, starts bit blt now */
1593 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1594 cirrus_bitblt_start(s);
1595 }
1596 break;
1597 case 0x2e: // BLT SRC ADDR 0x3f0000
1598 s->gr[reg_index] = reg_value & 0x3f;
1599 break;
1600 case 0x31: // BLT STATUS/START
1601 cirrus_write_bitblt(s, reg_value);
1602 break;
1603 default:
1604 #ifdef DEBUG_CIRRUS
1605 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1606 reg_value);
1607 #endif
1608 break;
1609 }
1610
1611 return CIRRUS_HOOK_HANDLED;
1612 }
1613
1614 /***************************************
1615 *
1616 * I/O access between 0x3d4-0x3d5
1617 *
1618 ***************************************/
1619
1620 static int
1621 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1622 {
1623 switch (reg_index) {
1624 case 0x00: // Standard VGA
1625 case 0x01: // Standard VGA
1626 case 0x02: // Standard VGA
1627 case 0x03: // Standard VGA
1628 case 0x04: // Standard VGA
1629 case 0x05: // Standard VGA
1630 case 0x06: // Standard VGA
1631 case 0x07: // Standard VGA
1632 case 0x08: // Standard VGA
1633 case 0x09: // Standard VGA
1634 case 0x0a: // Standard VGA
1635 case 0x0b: // Standard VGA
1636 case 0x0c: // Standard VGA
1637 case 0x0d: // Standard VGA
1638 case 0x0e: // Standard VGA
1639 case 0x0f: // Standard VGA
1640 case 0x10: // Standard VGA
1641 case 0x11: // Standard VGA
1642 case 0x12: // Standard VGA
1643 case 0x13: // Standard VGA
1644 case 0x14: // Standard VGA
1645 case 0x15: // Standard VGA
1646 case 0x16: // Standard VGA
1647 case 0x17: // Standard VGA
1648 case 0x18: // Standard VGA
1649 return CIRRUS_HOOK_NOT_HANDLED;
1650 case 0x24: // Attribute Controller Toggle Readback (R)
1651 *reg_value = (s->ar_flip_flop << 7);
1652 break;
1653 case 0x19: // Interlace End
1654 case 0x1a: // Miscellaneous Control
1655 case 0x1b: // Extended Display Control
1656 case 0x1c: // Sync Adjust and Genlock
1657 case 0x1d: // Overlay Extended Control
1658 case 0x22: // Graphics Data Latches Readback (R)
1659 case 0x25: // Part Status
1660 case 0x27: // Part ID (R)
1661 *reg_value = s->cr[reg_index];
1662 break;
1663 case 0x26: // Attribute Controller Index Readback (R)
1664 *reg_value = s->ar_index & 0x3f;
1665 break;
1666 default:
1667 #ifdef DEBUG_CIRRUS
1668 printf("cirrus: inport cr_index %02x\n", reg_index);
1669 *reg_value = 0xff;
1670 #endif
1671 break;
1672 }
1673
1674 return CIRRUS_HOOK_HANDLED;
1675 }
1676
1677 static int
1678 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1679 {
1680 switch (reg_index) {
1681 case 0x00: // Standard VGA
1682 case 0x01: // Standard VGA
1683 case 0x02: // Standard VGA
1684 case 0x03: // Standard VGA
1685 case 0x04: // Standard VGA
1686 case 0x05: // Standard VGA
1687 case 0x06: // Standard VGA
1688 case 0x07: // Standard VGA
1689 case 0x08: // Standard VGA
1690 case 0x09: // Standard VGA
1691 case 0x0a: // Standard VGA
1692 case 0x0b: // Standard VGA
1693 case 0x0c: // Standard VGA
1694 case 0x0d: // Standard VGA
1695 case 0x0e: // Standard VGA
1696 case 0x0f: // Standard VGA
1697 case 0x10: // Standard VGA
1698 case 0x11: // Standard VGA
1699 case 0x12: // Standard VGA
1700 case 0x13: // Standard VGA
1701 case 0x14: // Standard VGA
1702 case 0x15: // Standard VGA
1703 case 0x16: // Standard VGA
1704 case 0x17: // Standard VGA
1705 case 0x18: // Standard VGA
1706 return CIRRUS_HOOK_NOT_HANDLED;
1707 case 0x19: // Interlace End
1708 case 0x1a: // Miscellaneous Control
1709 case 0x1b: // Extended Display Control
1710 case 0x1c: // Sync Adjust and Genlock
1711 case 0x1d: // Overlay Extended Control
1712 s->cr[reg_index] = reg_value;
1713 #ifdef DEBUG_CIRRUS
1714 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1715 reg_index, reg_value);
1716 #endif
1717 break;
1718 case 0x22: // Graphics Data Latches Readback (R)
1719 case 0x24: // Attribute Controller Toggle Readback (R)
1720 case 0x26: // Attribute Controller Index Readback (R)
1721 case 0x27: // Part ID (R)
1722 break;
1723 case 0x25: // Part Status
1724 default:
1725 #ifdef DEBUG_CIRRUS
1726 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1727 reg_value);
1728 #endif
1729 break;
1730 }
1731
1732 return CIRRUS_HOOK_HANDLED;
1733 }
1734
1735 /***************************************
1736 *
1737 * memory-mapped I/O (bitblt)
1738 *
1739 ***************************************/
1740
1741 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1742 {
1743 int value = 0xff;
1744
1745 switch (address) {
1746 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1747 cirrus_hook_read_gr(s, 0x00, &value);
1748 break;
1749 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1750 cirrus_hook_read_gr(s, 0x10, &value);
1751 break;
1752 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1753 cirrus_hook_read_gr(s, 0x12, &value);
1754 break;
1755 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1756 cirrus_hook_read_gr(s, 0x14, &value);
1757 break;
1758 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1759 cirrus_hook_read_gr(s, 0x01, &value);
1760 break;
1761 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1762 cirrus_hook_read_gr(s, 0x11, &value);
1763 break;
1764 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1765 cirrus_hook_read_gr(s, 0x13, &value);
1766 break;
1767 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1768 cirrus_hook_read_gr(s, 0x15, &value);
1769 break;
1770 case (CIRRUS_MMIO_BLTWIDTH + 0):
1771 cirrus_hook_read_gr(s, 0x20, &value);
1772 break;
1773 case (CIRRUS_MMIO_BLTWIDTH + 1):
1774 cirrus_hook_read_gr(s, 0x21, &value);
1775 break;
1776 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1777 cirrus_hook_read_gr(s, 0x22, &value);
1778 break;
1779 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1780 cirrus_hook_read_gr(s, 0x23, &value);
1781 break;
1782 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1783 cirrus_hook_read_gr(s, 0x24, &value);
1784 break;
1785 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1786 cirrus_hook_read_gr(s, 0x25, &value);
1787 break;
1788 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1789 cirrus_hook_read_gr(s, 0x26, &value);
1790 break;
1791 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1792 cirrus_hook_read_gr(s, 0x27, &value);
1793 break;
1794 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1795 cirrus_hook_read_gr(s, 0x28, &value);
1796 break;
1797 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1798 cirrus_hook_read_gr(s, 0x29, &value);
1799 break;
1800 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1801 cirrus_hook_read_gr(s, 0x2a, &value);
1802 break;
1803 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1804 cirrus_hook_read_gr(s, 0x2c, &value);
1805 break;
1806 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1807 cirrus_hook_read_gr(s, 0x2d, &value);
1808 break;
1809 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1810 cirrus_hook_read_gr(s, 0x2e, &value);
1811 break;
1812 case CIRRUS_MMIO_BLTWRITEMASK:
1813 cirrus_hook_read_gr(s, 0x2f, &value);
1814 break;
1815 case CIRRUS_MMIO_BLTMODE:
1816 cirrus_hook_read_gr(s, 0x30, &value);
1817 break;
1818 case CIRRUS_MMIO_BLTROP:
1819 cirrus_hook_read_gr(s, 0x32, &value);
1820 break;
1821 case CIRRUS_MMIO_BLTMODEEXT:
1822 cirrus_hook_read_gr(s, 0x33, &value);
1823 break;
1824 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1825 cirrus_hook_read_gr(s, 0x34, &value);
1826 break;
1827 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1828 cirrus_hook_read_gr(s, 0x35, &value);
1829 break;
1830 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1831 cirrus_hook_read_gr(s, 0x38, &value);
1832 break;
1833 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1834 cirrus_hook_read_gr(s, 0x39, &value);
1835 break;
1836 case CIRRUS_MMIO_BLTSTATUS:
1837 cirrus_hook_read_gr(s, 0x31, &value);
1838 break;
1839 default:
1840 #ifdef DEBUG_CIRRUS
1841 printf("cirrus: mmio read - address 0x%04x\n", address);
1842 #endif
1843 break;
1844 }
1845
1846 return (uint8_t) value;
1847 }
1848
1849 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1850 uint8_t value)
1851 {
1852 switch (address) {
1853 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1854 cirrus_hook_write_gr(s, 0x00, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1857 cirrus_hook_write_gr(s, 0x10, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1860 cirrus_hook_write_gr(s, 0x12, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1863 cirrus_hook_write_gr(s, 0x14, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1866 cirrus_hook_write_gr(s, 0x01, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1869 cirrus_hook_write_gr(s, 0x11, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1872 cirrus_hook_write_gr(s, 0x13, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1875 cirrus_hook_write_gr(s, 0x15, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTWIDTH + 0):
1878 cirrus_hook_write_gr(s, 0x20, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTWIDTH + 1):
1881 cirrus_hook_write_gr(s, 0x21, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1884 cirrus_hook_write_gr(s, 0x22, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1887 cirrus_hook_write_gr(s, 0x23, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1890 cirrus_hook_write_gr(s, 0x24, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1893 cirrus_hook_write_gr(s, 0x25, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1896 cirrus_hook_write_gr(s, 0x26, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1899 cirrus_hook_write_gr(s, 0x27, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1902 cirrus_hook_write_gr(s, 0x28, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1905 cirrus_hook_write_gr(s, 0x29, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1908 cirrus_hook_write_gr(s, 0x2a, value);
1909 break;
1910 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1911 /* ignored */
1912 break;
1913 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1914 cirrus_hook_write_gr(s, 0x2c, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1917 cirrus_hook_write_gr(s, 0x2d, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1920 cirrus_hook_write_gr(s, 0x2e, value);
1921 break;
1922 case CIRRUS_MMIO_BLTWRITEMASK:
1923 cirrus_hook_write_gr(s, 0x2f, value);
1924 break;
1925 case CIRRUS_MMIO_BLTMODE:
1926 cirrus_hook_write_gr(s, 0x30, value);
1927 break;
1928 case CIRRUS_MMIO_BLTROP:
1929 cirrus_hook_write_gr(s, 0x32, value);
1930 break;
1931 case CIRRUS_MMIO_BLTMODEEXT:
1932 cirrus_hook_write_gr(s, 0x33, value);
1933 break;
1934 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1935 cirrus_hook_write_gr(s, 0x34, value);
1936 break;
1937 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1938 cirrus_hook_write_gr(s, 0x35, value);
1939 break;
1940 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1941 cirrus_hook_write_gr(s, 0x38, value);
1942 break;
1943 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1944 cirrus_hook_write_gr(s, 0x39, value);
1945 break;
1946 case CIRRUS_MMIO_BLTSTATUS:
1947 cirrus_hook_write_gr(s, 0x31, value);
1948 break;
1949 default:
1950 #ifdef DEBUG_CIRRUS
1951 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1952 address, value);
1953 #endif
1954 break;
1955 }
1956 }
1957
1958 /***************************************
1959 *
1960 * write mode 4/5
1961 *
1962 * assume TARGET_PAGE_SIZE >= 16
1963 *
1964 ***************************************/
1965
1966 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1967 unsigned mode,
1968 unsigned offset,
1969 uint32_t mem_value)
1970 {
1971 int x;
1972 unsigned val = mem_value;
1973 uint8_t *dst;
1974
1975 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1976 for (x = 0; x < 8; x++) {
1977 if (val & 0x80) {
1978 *dst = s->cirrus_shadow_gr1;
1979 } else if (mode == 5) {
1980 *dst = s->cirrus_shadow_gr0;
1981 }
1982 val <<= 1;
1983 dst++;
1984 }
1985 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1986 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1987 }
1988
1989 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1990 unsigned mode,
1991 unsigned offset,
1992 uint32_t mem_value)
1993 {
1994 int x;
1995 unsigned val = mem_value;
1996 uint8_t *dst;
1997
1998 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1999 for (x = 0; x < 8; x++) {
2000 if (val & 0x80) {
2001 *dst = s->cirrus_shadow_gr1;
2002 *(dst + 1) = s->gr[0x11];
2003 } else if (mode == 5) {
2004 *dst = s->cirrus_shadow_gr0;
2005 *(dst + 1) = s->gr[0x10];
2006 }
2007 val <<= 1;
2008 dst += 2;
2009 }
2010 cpu_physical_memory_set_dirty(s->vram_offset + offset);
2011 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
2012 }
2013
2014 /***************************************
2015 *
2016 * memory access between 0xa0000-0xbffff
2017 *
2018 ***************************************/
2019
2020 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2021 {
2022 CirrusVGAState *s = opaque;
2023 unsigned bank_index;
2024 unsigned bank_offset;
2025 uint32_t val;
2026
2027 if ((s->sr[0x07] & 0x01) == 0) {
2028 return vga_mem_readb(s, addr);
2029 }
2030
2031 addr &= 0x1ffff;
2032
2033 if (addr < 0x10000) {
2034 /* XXX handle bitblt */
2035 /* video memory */
2036 bank_index = addr >> 15;
2037 bank_offset = addr & 0x7fff;
2038 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2039 bank_offset += s->cirrus_bank_base[bank_index];
2040 if ((s->gr[0x0B] & 0x14) == 0x14) {
2041 bank_offset <<= 4;
2042 } else if (s->gr[0x0B] & 0x02) {
2043 bank_offset <<= 3;
2044 }
2045 bank_offset &= s->cirrus_addr_mask;
2046 val = *(s->vram_ptr + bank_offset);
2047 } else
2048 val = 0xff;
2049 } else if (addr >= 0x18000 && addr < 0x18100) {
2050 /* memory-mapped I/O */
2051 val = 0xff;
2052 if ((s->sr[0x17] & 0x44) == 0x04) {
2053 val = cirrus_mmio_blt_read(s, addr & 0xff);
2054 }
2055 } else {
2056 val = 0xff;
2057 #ifdef DEBUG_CIRRUS
2058 printf("cirrus: mem_readb %06x\n", addr);
2059 #endif
2060 }
2061 return val;
2062 }
2063
2064 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2065 {
2066 uint32_t v;
2067 #ifdef TARGET_WORDS_BIGENDIAN
2068 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2069 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2070 #else
2071 v = cirrus_vga_mem_readb(opaque, addr);
2072 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2073 #endif
2074 return v;
2075 }
2076
2077 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2078 {
2079 uint32_t v;
2080 #ifdef TARGET_WORDS_BIGENDIAN
2081 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2082 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2083 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2084 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2085 #else
2086 v = cirrus_vga_mem_readb(opaque, addr);
2087 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2088 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2089 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2090 #endif
2091 return v;
2092 }
2093
2094 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2095 uint32_t mem_value)
2096 {
2097 CirrusVGAState *s = opaque;
2098 unsigned bank_index;
2099 unsigned bank_offset;
2100 unsigned mode;
2101
2102 if ((s->sr[0x07] & 0x01) == 0) {
2103 vga_mem_writeb(s, addr, mem_value);
2104 return;
2105 }
2106
2107 addr &= 0x1ffff;
2108
2109 if (addr < 0x10000) {
2110 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2111 /* bitblt */
2112 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2113 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2114 cirrus_bitblt_cputovideo_next(s);
2115 }
2116 } else {
2117 /* video memory */
2118 bank_index = addr >> 15;
2119 bank_offset = addr & 0x7fff;
2120 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2121 bank_offset += s->cirrus_bank_base[bank_index];
2122 if ((s->gr[0x0B] & 0x14) == 0x14) {
2123 bank_offset <<= 4;
2124 } else if (s->gr[0x0B] & 0x02) {
2125 bank_offset <<= 3;
2126 }
2127 bank_offset &= s->cirrus_addr_mask;
2128 mode = s->gr[0x05] & 0x7;
2129 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2130 *(s->vram_ptr + bank_offset) = mem_value;
2131 cpu_physical_memory_set_dirty(s->vram_offset +
2132 bank_offset);
2133 } else {
2134 if ((s->gr[0x0B] & 0x14) != 0x14) {
2135 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2136 bank_offset,
2137 mem_value);
2138 } else {
2139 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2140 bank_offset,
2141 mem_value);
2142 }
2143 }
2144 }
2145 }
2146 } else if (addr >= 0x18000 && addr < 0x18100) {
2147 /* memory-mapped I/O */
2148 if ((s->sr[0x17] & 0x44) == 0x04) {
2149 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2150 }
2151 } else {
2152 #ifdef DEBUG_CIRRUS
2153 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2154 #endif
2155 }
2156 }
2157
2158 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2159 {
2160 #ifdef TARGET_WORDS_BIGENDIAN
2161 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2163 #else
2164 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2165 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2166 #endif
2167 }
2168
2169 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2170 {
2171 #ifdef TARGET_WORDS_BIGENDIAN
2172 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2173 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2174 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2175 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2176 #else
2177 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2178 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2179 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2180 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2181 #endif
2182 }
2183
2184 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2185 cirrus_vga_mem_readb,
2186 cirrus_vga_mem_readw,
2187 cirrus_vga_mem_readl,
2188 };
2189
2190 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2191 cirrus_vga_mem_writeb,
2192 cirrus_vga_mem_writew,
2193 cirrus_vga_mem_writel,
2194 };
2195
2196 /***************************************
2197 *
2198 * hardware cursor
2199 *
2200 ***************************************/
2201
2202 static inline void invalidate_cursor1(CirrusVGAState *s)
2203 {
2204 if (s->last_hw_cursor_size) {
2205 vga_invalidate_scanlines((VGAState *)s,
2206 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2207 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2208 }
2209 }
2210
2211 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2212 {
2213 const uint8_t *src;
2214 uint32_t content;
2215 int y, y_min, y_max;
2216
2217 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2218 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2219 src += (s->sr[0x13] & 0x3c) * 256;
2220 y_min = 64;
2221 y_max = -1;
2222 for(y = 0; y < 64; y++) {
2223 content = ((uint32_t *)src)[0] |
2224 ((uint32_t *)src)[1] |
2225 ((uint32_t *)src)[2] |
2226 ((uint32_t *)src)[3];
2227 if (content) {
2228 if (y < y_min)
2229 y_min = y;
2230 if (y > y_max)
2231 y_max = y;
2232 }
2233 src += 16;
2234 }
2235 } else {
2236 src += (s->sr[0x13] & 0x3f) * 256;
2237 y_min = 32;
2238 y_max = -1;
2239 for(y = 0; y < 32; y++) {
2240 content = ((uint32_t *)src)[0] |
2241 ((uint32_t *)(src + 128))[0];
2242 if (content) {
2243 if (y < y_min)
2244 y_min = y;
2245 if (y > y_max)
2246 y_max = y;
2247 }
2248 src += 4;
2249 }
2250 }
2251 if (y_min > y_max) {
2252 s->last_hw_cursor_y_start = 0;
2253 s->last_hw_cursor_y_end = 0;
2254 } else {
2255 s->last_hw_cursor_y_start = y_min;
2256 s->last_hw_cursor_y_end = y_max + 1;
2257 }
2258 }
2259
2260 /* NOTE: we do not currently handle the cursor bitmap change, so we
2261 update the cursor only if it moves. */
2262 static void cirrus_cursor_invalidate(VGAState *s1)
2263 {
2264 CirrusVGAState *s = (CirrusVGAState *)s1;
2265 int size;
2266
2267 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2268 size = 0;
2269 } else {
2270 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2271 size = 64;
2272 else
2273 size = 32;
2274 }
2275 /* invalidate last cursor and new cursor if any change */
2276 if (s->last_hw_cursor_size != size ||
2277 s->last_hw_cursor_x != s->hw_cursor_x ||
2278 s->last_hw_cursor_y != s->hw_cursor_y) {
2279
2280 invalidate_cursor1(s);
2281
2282 s->last_hw_cursor_size = size;
2283 s->last_hw_cursor_x = s->hw_cursor_x;
2284 s->last_hw_cursor_y = s->hw_cursor_y;
2285 /* compute the real cursor min and max y */
2286 cirrus_cursor_compute_yrange(s);
2287 invalidate_cursor1(s);
2288 }
2289 }
2290
2291 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2292 {
2293 CirrusVGAState *s = (CirrusVGAState *)s1;
2294 int w, h, bpp, x1, x2, poffset;
2295 unsigned int color0, color1;
2296 const uint8_t *palette, *src;
2297 uint32_t content;
2298
2299 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2300 return;
2301 /* fast test to see if the cursor intersects with the scan line */
2302 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2303 h = 64;
2304 } else {
2305 h = 32;
2306 }
2307 if (scr_y < s->hw_cursor_y ||
2308 scr_y >= (s->hw_cursor_y + h))
2309 return;
2310
2311 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2312 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2313 src += (s->sr[0x13] & 0x3c) * 256;
2314 src += (scr_y - s->hw_cursor_y) * 16;
2315 poffset = 8;
2316 content = ((uint32_t *)src)[0] |
2317 ((uint32_t *)src)[1] |
2318 ((uint32_t *)src)[2] |
2319 ((uint32_t *)src)[3];
2320 } else {
2321 src += (s->sr[0x13] & 0x3f) * 256;
2322 src += (scr_y - s->hw_cursor_y) * 4;
2323 poffset = 128;
2324 content = ((uint32_t *)src)[0] |
2325 ((uint32_t *)(src + 128))[0];
2326 }
2327 /* if nothing to draw, no need to continue */
2328 if (!content)
2329 return;
2330 w = h;
2331
2332 x1 = s->hw_cursor_x;
2333 if (x1 >= s->last_scr_width)
2334 return;
2335 x2 = s->hw_cursor_x + w;
2336 if (x2 > s->last_scr_width)
2337 x2 = s->last_scr_width;
2338 w = x2 - x1;
2339 palette = s->cirrus_hidden_palette;
2340 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2341 c6_to_8(palette[0x0 * 3 + 1]),
2342 c6_to_8(palette[0x0 * 3 + 2]));
2343 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2344 c6_to_8(palette[0xf * 3 + 1]),
2345 c6_to_8(palette[0xf * 3 + 2]));
2346 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2347 d1 += x1 * bpp;
2348 switch(ds_get_bits_per_pixel(s->ds)) {
2349 default:
2350 break;
2351 case 8:
2352 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2353 break;
2354 case 15:
2355 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2356 break;
2357 case 16:
2358 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2359 break;
2360 case 32:
2361 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2362 break;
2363 }
2364 }
2365
2366 /***************************************
2367 *
2368 * LFB memory access
2369 *
2370 ***************************************/
2371
2372 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2373 {
2374 CirrusVGAState *s = (CirrusVGAState *) opaque;
2375 uint32_t ret;
2376
2377 addr &= s->cirrus_addr_mask;
2378
2379 if (((s->sr[0x17] & 0x44) == 0x44) &&
2380 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2381 /* memory-mapped I/O */
2382 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2383 } else if (0) {
2384 /* XXX handle bitblt */
2385 ret = 0xff;
2386 } else {
2387 /* video memory */
2388 if ((s->gr[0x0B] & 0x14) == 0x14) {
2389 addr <<= 4;
2390 } else if (s->gr[0x0B] & 0x02) {
2391 addr <<= 3;
2392 }
2393 addr &= s->cirrus_addr_mask;
2394 ret = *(s->vram_ptr + addr);
2395 }
2396
2397 return ret;
2398 }
2399
2400 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2401 {
2402 uint32_t v;
2403 #ifdef TARGET_WORDS_BIGENDIAN
2404 v = cirrus_linear_readb(opaque, addr) << 8;
2405 v |= cirrus_linear_readb(opaque, addr + 1);
2406 #else
2407 v = cirrus_linear_readb(opaque, addr);
2408 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2409 #endif
2410 return v;
2411 }
2412
2413 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2414 {
2415 uint32_t v;
2416 #ifdef TARGET_WORDS_BIGENDIAN
2417 v = cirrus_linear_readb(opaque, addr) << 24;
2418 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2419 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2420 v |= cirrus_linear_readb(opaque, addr + 3);
2421 #else
2422 v = cirrus_linear_readb(opaque, addr);
2423 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2424 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2425 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2426 #endif
2427 return v;
2428 }
2429
2430 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2431 uint32_t val)
2432 {
2433 CirrusVGAState *s = (CirrusVGAState *) opaque;
2434 unsigned mode;
2435
2436 addr &= s->cirrus_addr_mask;
2437
2438 if (((s->sr[0x17] & 0x44) == 0x44) &&
2439 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2440 /* memory-mapped I/O */
2441 cirrus_mmio_blt_write(s, addr & 0xff, val);
2442 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2443 /* bitblt */
2444 *s->cirrus_srcptr++ = (uint8_t) val;
2445 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2446 cirrus_bitblt_cputovideo_next(s);
2447 }
2448 } else {
2449 /* video memory */
2450 if ((s->gr[0x0B] & 0x14) == 0x14) {
2451 addr <<= 4;
2452 } else if (s->gr[0x0B] & 0x02) {
2453 addr <<= 3;
2454 }
2455 addr &= s->cirrus_addr_mask;
2456
2457 mode = s->gr[0x05] & 0x7;
2458 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2459 *(s->vram_ptr + addr) = (uint8_t) val;
2460 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2461 } else {
2462 if ((s->gr[0x0B] & 0x14) != 0x14) {
2463 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2464 } else {
2465 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2466 }
2467 }
2468 }
2469 }
2470
2471 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2472 uint32_t val)
2473 {
2474 #ifdef TARGET_WORDS_BIGENDIAN
2475 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2476 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2477 #else
2478 cirrus_linear_writeb(opaque, addr, val & 0xff);
2479 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2480 #endif
2481 }
2482
2483 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2484 uint32_t val)
2485 {
2486 #ifdef TARGET_WORDS_BIGENDIAN
2487 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2488 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2489 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2490 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2491 #else
2492 cirrus_linear_writeb(opaque, addr, val & 0xff);
2493 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2494 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2495 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2496 #endif
2497 }
2498
2499
2500 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2501 cirrus_linear_readb,
2502 cirrus_linear_readw,
2503 cirrus_linear_readl,
2504 };
2505
2506 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2507 cirrus_linear_writeb,
2508 cirrus_linear_writew,
2509 cirrus_linear_writel,
2510 };
2511
2512 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2513 uint32_t val)
2514 {
2515 CirrusVGAState *s = (CirrusVGAState *) opaque;
2516
2517 addr &= s->cirrus_addr_mask;
2518 *(s->vram_ptr + addr) = val;
2519 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2520 }
2521
2522 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2523 uint32_t val)
2524 {
2525 CirrusVGAState *s = (CirrusVGAState *) opaque;
2526
2527 addr &= s->cirrus_addr_mask;
2528 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2529 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2530 }
2531
2532 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2533 uint32_t val)
2534 {
2535 CirrusVGAState *s = (CirrusVGAState *) opaque;
2536
2537 addr &= s->cirrus_addr_mask;
2538 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2539 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2540 }
2541
2542 /***************************************
2543 *
2544 * system to screen memory access
2545 *
2546 ***************************************/
2547
2548
2549 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2550 {
2551 uint32_t ret;
2552
2553 /* XXX handle bitblt */
2554 ret = 0xff;
2555 return ret;
2556 }
2557
2558 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2559 {
2560 uint32_t v;
2561 #ifdef TARGET_WORDS_BIGENDIAN
2562 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2563 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2564 #else
2565 v = cirrus_linear_bitblt_readb(opaque, addr);
2566 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2567 #endif
2568 return v;
2569 }
2570
2571 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2572 {
2573 uint32_t v;
2574 #ifdef TARGET_WORDS_BIGENDIAN
2575 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2576 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2577 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2578 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2579 #else
2580 v = cirrus_linear_bitblt_readb(opaque, addr);
2581 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2582 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2583 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2584 #endif
2585 return v;
2586 }
2587
2588 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2589 uint32_t val)
2590 {
2591 CirrusVGAState *s = (CirrusVGAState *) opaque;
2592
2593 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2594 /* bitblt */
2595 *s->cirrus_srcptr++ = (uint8_t) val;
2596 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2597 cirrus_bitblt_cputovideo_next(s);
2598 }
2599 }
2600 }
2601
2602 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2603 uint32_t val)
2604 {
2605 #ifdef TARGET_WORDS_BIGENDIAN
2606 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2608 #else
2609 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2610 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2611 #endif
2612 }
2613
2614 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2615 uint32_t val)
2616 {
2617 #ifdef TARGET_WORDS_BIGENDIAN
2618 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2619 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2620 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2621 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2622 #else
2623 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2624 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2625 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2626 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2627 #endif
2628 }
2629
2630
2631 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2632 cirrus_linear_bitblt_readb,
2633 cirrus_linear_bitblt_readw,
2634 cirrus_linear_bitblt_readl,
2635 };
2636
2637 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2638 cirrus_linear_bitblt_writeb,
2639 cirrus_linear_bitblt_writew,
2640 cirrus_linear_bitblt_writel,
2641 };
2642
2643 static void map_linear_vram(CirrusVGAState *s)
2644 {
2645
2646 vga_dirty_log_stop((VGAState *)s);
2647 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2648 s->map_addr = s->lfb_addr;
2649 s->map_end = s->lfb_end;
2650 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2651 vga_dirty_log_start((VGAState *)s);
2652 }
2653
2654 if (!s->map_addr)
2655 return;
2656
2657 #ifndef TARGET_IA64
2658 s->lfb_vram_mapped = 0;
2659
2660 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2661 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2662 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2663 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2664 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2665 && !((s->sr[0x07] & 0x01) == 0)
2666 && !((s->gr[0x0B] & 0x14) == 0x14)
2667 && !(s->gr[0x0B] & 0x02)) {
2668
2669 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2670 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2671 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2672 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2673
2674 s->lfb_vram_mapped = 1;
2675 }
2676 else {
2677 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, s->vga_io_memory);
2678 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, s->vga_io_memory);
2679 }
2680 #endif
2681 vga_dirty_log_start((VGAState *)s);
2682 }
2683
2684 static void unmap_linear_vram(CirrusVGAState *s)
2685 {
2686 vga_dirty_log_stop((VGAState *)s);
2687 if (s->map_addr && s->lfb_addr && s->lfb_end)
2688 s->map_addr = s->map_end = 0;
2689
2690 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2691 s->vga_io_memory);
2692 vga_dirty_log_start((VGAState *)s);
2693 }
2694
2695 /* Compute the memory access functions */
2696 static void cirrus_update_memory_access(CirrusVGAState *s)
2697 {
2698 unsigned mode;
2699
2700 if ((s->sr[0x17] & 0x44) == 0x44) {
2701 goto generic_io;
2702 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2703 goto generic_io;
2704 } else {
2705 if ((s->gr[0x0B] & 0x14) == 0x14) {
2706 goto generic_io;
2707 } else if (s->gr[0x0B] & 0x02) {
2708 goto generic_io;
2709 }
2710
2711 mode = s->gr[0x05] & 0x7;
2712 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2713 map_linear_vram(s);
2714 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2715 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2716 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2717 } else {
2718 generic_io:
2719 unmap_linear_vram(s);
2720 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2721 s->cirrus_linear_write[1] = cirrus_linear_writew;
2722 s->cirrus_linear_write[2] = cirrus_linear_writel;
2723 }
2724 }
2725 }
2726
2727
2728 /* I/O ports */
2729
2730 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2731 {
2732 CirrusVGAState *s = opaque;
2733 int val, index;
2734
2735 /* check port range access depending on color/monochrome mode */
2736 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2737 || (addr >= 0x3d0 && addr <= 0x3df
2738 && !(s->msr & MSR_COLOR_EMULATION))) {
2739 val = 0xff;
2740 } else {
2741 switch (addr) {
2742 case 0x3c0:
2743 if (s->ar_flip_flop == 0) {
2744 val = s->ar_index;
2745 } else {
2746 val = 0;
2747 }
2748 break;
2749 case 0x3c1:
2750 index = s->ar_index & 0x1f;
2751 if (index < 21)
2752 val = s->ar[index];
2753 else
2754 val = 0;
2755 break;
2756 case 0x3c2:
2757 val = s->st00;
2758 break;
2759 case 0x3c4:
2760 val = s->sr_index;
2761 break;
2762 case 0x3c5:
2763 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2764 break;
2765 val = s->sr[s->sr_index];
2766 #ifdef DEBUG_VGA_REG
2767 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2768 #endif
2769 break;
2770 case 0x3c6:
2771 cirrus_read_hidden_dac(s, &val);
2772 break;
2773 case 0x3c7:
2774 val = s->dac_state;
2775 break;
2776 case 0x3c8:
2777 val = s->dac_write_index;
2778 s->cirrus_hidden_dac_lockindex = 0;
2779 break;
2780 case 0x3c9:
2781 if (cirrus_hook_read_palette(s, &val))
2782 break;
2783 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2784 if (++s->dac_sub_index == 3) {
2785 s->dac_sub_index = 0;
2786 s->dac_read_index++;
2787 }
2788 break;
2789 case 0x3ca:
2790 val = s->fcr;
2791 break;
2792 case 0x3cc:
2793 val = s->msr;
2794 break;
2795 case 0x3ce:
2796 val = s->gr_index;
2797 break;
2798 case 0x3cf:
2799 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2800 break;
2801 val = s->gr[s->gr_index];
2802 #ifdef DEBUG_VGA_REG
2803 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2804 #endif
2805 break;
2806 case 0x3b4:
2807 case 0x3d4:
2808 val = s->cr_index;
2809 break;
2810 case 0x3b5:
2811 case 0x3d5:
2812 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2813 break;
2814 val = s->cr[s->cr_index];
2815 #ifdef DEBUG_VGA_REG
2816 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2817 #endif
2818 break;
2819 case 0x3ba:
2820 case 0x3da:
2821 /* just toggle to fool polling */
2822 val = s->st01 = s->retrace((VGAState *) s);
2823 s->ar_flip_flop = 0;
2824 break;
2825 default:
2826 val = 0x00;
2827 break;
2828 }
2829 }
2830 #if defined(DEBUG_VGA)
2831 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2832 #endif
2833 return val;
2834 }
2835
2836 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2837 {
2838 CirrusVGAState *s = opaque;
2839 int index;
2840
2841 /* check port range access depending on color/monochrome mode */
2842 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2843 || (addr >= 0x3d0 && addr <= 0x3df
2844 && !(s->msr & MSR_COLOR_EMULATION)))
2845 return;
2846
2847 #ifdef DEBUG_VGA
2848 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2849 #endif
2850
2851 switch (addr) {
2852 case 0x3c0:
2853 if (s->ar_flip_flop == 0) {
2854 val &= 0x3f;
2855 s->ar_index = val;
2856 } else {
2857 index = s->ar_index & 0x1f;
2858 switch (index) {
2859 case 0x00 ... 0x0f:
2860 s->ar[index] = val & 0x3f;
2861 break;
2862 case 0x10:
2863 s->ar[index] = val & ~0x10;
2864 break;
2865 case 0x11:
2866 s->ar[index] = val;
2867 break;
2868 case 0x12:
2869 s->ar[index] = val & ~0xc0;
2870 break;
2871 case 0x13:
2872 s->ar[index] = val & ~0xf0;
2873 break;
2874 case 0x14:
2875 s->ar[index] = val & ~0xf0;
2876 break;
2877 default:
2878 break;
2879 }
2880 }
2881 s->ar_flip_flop ^= 1;
2882 break;
2883 case 0x3c2:
2884 s->msr = val & ~0x10;
2885 s->update_retrace_info((VGAState *) s);
2886 break;
2887 case 0x3c4:
2888 s->sr_index = val;
2889 break;
2890 case 0x3c5:
2891 if (cirrus_hook_write_sr(s, s->sr_index, val))
2892 break;
2893 #ifdef DEBUG_VGA_REG
2894 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2895 #endif
2896 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2897 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2898 break;
2899 case 0x3c6:
2900 cirrus_write_hidden_dac(s, val);
2901 break;
2902 case 0x3c7:
2903 s->dac_read_index = val;
2904 s->dac_sub_index = 0;
2905 s->dac_state = 3;
2906 break;
2907 case 0x3c8:
2908 s->dac_write_index = val;
2909 s->dac_sub_index = 0;
2910 s->dac_state = 0;
2911 break;
2912 case 0x3c9:
2913 if (cirrus_hook_write_palette(s, val))
2914 break;
2915 s->dac_cache[s->dac_sub_index] = val;
2916 if (++s->dac_sub_index == 3) {
2917 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2918 s->dac_sub_index = 0;
2919 s->dac_write_index++;
2920 }
2921 break;
2922 case 0x3ce:
2923 s->gr_index = val;
2924 break;
2925 case 0x3cf:
2926 if (cirrus_hook_write_gr(s, s->gr_index, val))
2927 break;
2928 #ifdef DEBUG_VGA_REG
2929 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2930 #endif
2931 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2932 break;
2933 case 0x3b4:
2934 case 0x3d4:
2935 s->cr_index = val;
2936 break;
2937 case 0x3b5:
2938 case 0x3d5:
2939 if (cirrus_hook_write_cr(s, s->cr_index, val))
2940 break;
2941 #ifdef DEBUG_VGA_REG
2942 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2943 #endif
2944 /* handle CR0-7 protection */
2945 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2946 /* can always write bit 4 of CR7 */
2947 if (s->cr_index == 7)
2948 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2949 return;
2950 }
2951 switch (s->cr_index) {
2952 case 0x01: /* horizontal display end */
2953 case 0x07:
2954 case 0x09:
2955 case 0x0c:
2956 case 0x0d:
2957 case 0x12: /* vertical display end */
2958 s->cr[s->cr_index] = val;
2959 break;
2960
2961 default:
2962 s->cr[s->cr_index] = val;
2963 break;
2964 }
2965
2966 switch(s->cr_index) {
2967 case 0x00:
2968 case 0x04:
2969 case 0x05:
2970 case 0x06:
2971 case 0x07:
2972 case 0x11:
2973 case 0x17:
2974 s->update_retrace_info((VGAState *) s);
2975 break;
2976 }
2977 break;
2978 case 0x3ba:
2979 case 0x3da:
2980 s->fcr = val & 0x10;
2981 break;
2982 }
2983 }
2984
2985 /***************************************
2986 *
2987 * memory-mapped I/O access
2988 *
2989 ***************************************/
2990
2991 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2992 {
2993 CirrusVGAState *s = (CirrusVGAState *) opaque;
2994
2995 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2996
2997 if (addr >= 0x100) {
2998 return cirrus_mmio_blt_read(s, addr - 0x100);
2999 } else {
3000 return vga_ioport_read(s, addr + 0x3c0);
3001 }
3002 }
3003
3004 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
3005 {
3006 uint32_t v;
3007 #ifdef TARGET_WORDS_BIGENDIAN
3008 v = cirrus_mmio_readb(opaque, addr) << 8;
3009 v |= cirrus_mmio_readb(opaque, addr + 1);
3010 #else
3011 v = cirrus_mmio_readb(opaque, addr);
3012 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3013 #endif
3014 return v;
3015 }
3016
3017 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3018 {
3019 uint32_t v;
3020 #ifdef TARGET_WORDS_BIGENDIAN
3021 v = cirrus_mmio_readb(opaque, addr) << 24;
3022 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3023 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3024 v |= cirrus_mmio_readb(opaque, addr + 3);
3025 #else
3026 v = cirrus_mmio_readb(opaque, addr);
3027 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3028 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3029 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3030 #endif
3031 return v;
3032 }
3033
3034 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3035 uint32_t val)
3036 {
3037 CirrusVGAState *s = (CirrusVGAState *) opaque;
3038
3039 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3040
3041 if (addr >= 0x100) {
3042 cirrus_mmio_blt_write(s, addr - 0x100, val);
3043 } else {
3044 vga_ioport_write(s, addr + 0x3c0, val);
3045 }
3046 }
3047
3048 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3049 uint32_t val)
3050 {
3051 #ifdef TARGET_WORDS_BIGENDIAN
3052 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3053 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3054 #else
3055 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3056 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3057 #endif
3058 }
3059
3060 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3061 uint32_t val)
3062 {
3063 #ifdef TARGET_WORDS_BIGENDIAN
3064 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3065 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3066 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3067 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3068 #else
3069 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3070 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3071 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3072 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3073 #endif
3074 }
3075
3076
3077 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3078 cirrus_mmio_readb,
3079 cirrus_mmio_readw,
3080 cirrus_mmio_readl,
3081 };
3082
3083 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3084 cirrus_mmio_writeb,
3085 cirrus_mmio_writew,
3086 cirrus_mmio_writel,
3087 };
3088
3089 /* load/save state */
3090
3091 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3092 {
3093 CirrusVGAState *s = opaque;
3094
3095 if (s->pci_dev)
3096 pci_device_save(s->pci_dev, f);
3097
3098 qemu_put_be32s(f, &s->latch);
3099 qemu_put_8s(f, &s->sr_index);
3100 qemu_put_buffer(f, s->sr, 256);
3101 qemu_put_8s(f, &s->gr_index);
3102 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3103 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3104 qemu_put_buffer(f, s->gr + 2, 254);
3105 qemu_put_8s(f, &s->ar_index);
3106 qemu_put_buffer(f, s->ar, 21);
3107 qemu_put_be32(f, s->ar_flip_flop);
3108 qemu_put_8s(f, &s->cr_index);
3109 qemu_put_buffer(f, s->cr, 256);
3110 qemu_put_8s(f, &s->msr);
3111 qemu_put_8s(f, &s->fcr);
3112 qemu_put_8s(f, &s->st00);
3113 qemu_put_8s(f, &s->st01);
3114
3115 qemu_put_8s(f, &s->dac_state);
3116 qemu_put_8s(f, &s->dac_sub_index);
3117 qemu_put_8s(f, &s->dac_read_index);
3118 qemu_put_8s(f, &s->dac_write_index);
3119 qemu_put_buffer(f, s->dac_cache, 3);
3120 qemu_put_buffer(f, s->palette, 768);
3121
3122 qemu_put_be32(f, s->bank_offset);
3123
3124 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3125 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3126
3127 qemu_put_be32s(f, &s->hw_cursor_x);
3128 qemu_put_be32s(f, &s->hw_cursor_y);
3129 /* XXX: we do not save the bitblt state - we assume we do not save
3130 the state when the blitter is active */
3131 }
3132
3133 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3134 {
3135 CirrusVGAState *s = opaque;
3136 int ret;
3137
3138 if (version_id > 2)
3139 return -EINVAL;
3140
3141 if (s->pci_dev && version_id >= 2) {
3142 ret = pci_device_load(s->pci_dev, f);
3143 if (ret < 0)
3144 return ret;
3145 }
3146
3147 qemu_get_be32s(f, &s->latch);
3148 qemu_get_8s(f, &s->sr_index);
3149 qemu_get_buffer(f, s->sr, 256);
3150 qemu_get_8s(f, &s->gr_index);
3151 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3152 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3153 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3154 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3155 qemu_get_buffer(f, s->gr + 2, 254);
3156 qemu_get_8s(f, &s->ar_index);
3157 qemu_get_buffer(f, s->ar, 21);
3158 s->ar_flip_flop=qemu_get_be32(f);
3159 qemu_get_8s(f, &s->cr_index);
3160 qemu_get_buffer(f, s->cr, 256);
3161 qemu_get_8s(f, &s->msr);
3162 qemu_get_8s(f, &s->fcr);
3163 qemu_get_8s(f, &s->st00);
3164 qemu_get_8s(f, &s->st01);
3165
3166 qemu_get_8s(f, &s->dac_state);
3167 qemu_get_8s(f, &s->dac_sub_index);
3168 qemu_get_8s(f, &s->dac_read_index);
3169 qemu_get_8s(f, &s->dac_write_index);
3170 qemu_get_buffer(f, s->dac_cache, 3);
3171 qemu_get_buffer(f, s->palette, 768);
3172
3173 s->bank_offset=qemu_get_be32(f);
3174
3175 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3176 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3177
3178 qemu_get_be32s(f, &s->hw_cursor_x);
3179 qemu_get_be32s(f, &s->hw_cursor_y);
3180
3181 cirrus_update_memory_access(s);
3182 /* force refresh */
3183 s->graphic_mode = -1;
3184 cirrus_update_bank_ptr(s, 0);
3185 cirrus_update_bank_ptr(s, 1);
3186 return 0;
3187 }
3188
3189 /***************************************
3190 *
3191 * initialize
3192 *
3193 ***************************************/
3194
3195 static void cirrus_reset(void *opaque)
3196 {
3197 CirrusVGAState *s = opaque;
3198
3199 vga_reset(s);
3200 s->sr[0x06] = 0x0f;
3201 if (s->device_id == CIRRUS_ID_CLGD5446) {
3202 /* 4MB 64 bit memory config, always PCI */
3203 s->sr[0x1F] = 0x2d; // MemClock
3204 s->gr[0x18] = 0x0f; // fastest memory configuration
3205 #if 1
3206 s->sr[0x0f] = 0x98;
3207 s->sr[0x17] = 0x20;
3208 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3209 s->real_vram_size = 4096 * 1024;
3210 #else
3211 s->sr[0x0f] = 0x18;
3212 s->sr[0x17] = 0x20;
3213 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3214 s->real_vram_size = 2048 * 1024;
3215 #endif
3216 } else {
3217 s->sr[0x1F] = 0x22; // MemClock
3218 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3219 s->sr[0x17] = s->bustype;
3220 s->real_vram_size = 2048 * 1024;
3221 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3222 }
3223 s->cr[0x27] = s->device_id;
3224
3225 /* Win2K seems to assume that the pattern buffer is at 0xff
3226 initially ! */
3227 memset(s->vram_ptr, 0xff, s->real_vram_size);
3228
3229 s->cirrus_hidden_dac_lockindex = 5;
3230 s->cirrus_hidden_dac_data = 0;
3231
3232 /* I/O handler for LFB */
3233 s->cirrus_linear_io_addr =
3234 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3235 s);
3236 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3237
3238 /* I/O handler for LFB */
3239 s->cirrus_linear_bitblt_io_addr =
3240 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3241 s);
3242
3243 /* I/O handler for memory-mapped I/O */
3244 s->cirrus_mmio_io_addr =
3245 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3246
3247 /* XXX: s->vram_size must be a power of two */
3248 s->cirrus_addr_mask = s->real_vram_size - 1;
3249 s->linear_mmio_mask = s->real_vram_size - 256;
3250
3251 s->get_bpp = cirrus_get_bpp;
3252 s->get_offsets = cirrus_get_offsets;
3253 s->get_resolution = cirrus_get_resolution;
3254 s->cursor_invalidate = cirrus_cursor_invalidate;
3255 s->cursor_draw_line = cirrus_cursor_draw_line;
3256 }
3257
3258 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3259 {
3260 int i;
3261 static int inited;
3262
3263 if (!inited) {
3264 inited = 1;
3265 for(i = 0;i < 256; i++)
3266 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3267 rop_to_index[CIRRUS_ROP_0] = 0;
3268 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3269 rop_to_index[CIRRUS_ROP_NOP] = 2;
3270 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3271 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3272 rop_to_index[CIRRUS_ROP_SRC] = 5;
3273 rop_to_index[CIRRUS_ROP_1] = 6;
3274 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3275 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3276 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3277 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3278 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3279 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3280 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3281 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3282 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3283 s->device_id = device_id;
3284 if (is_pci)
3285 s->bustype = CIRRUS_BUSTYPE_PCI;
3286 else
3287 s->bustype = CIRRUS_BUSTYPE_ISA;
3288 }
3289
3290 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3291
3292 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3293 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3294 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3295 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3296
3297 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3298
3299 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3300 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3301 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3302 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3303
3304 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3305 cirrus_vga_mem_write, s);
3306 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3307 s->vga_io_memory);
3308 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3309
3310 qemu_register_reset(cirrus_reset, s);
3311 cirrus_reset(s);
3312 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3313 }
3314
3315 /***************************************
3316 *
3317 * ISA bus support
3318 *
3319 ***************************************/
3320
3321 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3322 ram_addr_t vga_ram_offset, int vga_ram_size)
3323 {
3324 CirrusVGAState *s;
3325
3326 s = qemu_mallocz(sizeof(CirrusVGAState));
3327
3328 vga_common_init((VGAState *)s,
3329 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3330 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3331 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3332 s->screen_dump, s->text_update, s);
3333 /* XXX ISA-LFB support */
3334 }
3335
3336 /***************************************
3337 *
3338 * PCI bus support
3339 *
3340 ***************************************/
3341
3342 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3343 uint32_t addr, uint32_t size, int type)
3344 {
3345 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3346
3347 vga_dirty_log_stop((VGAState *)s);
3348 /* XXX: add byte swapping apertures */
3349 cpu_register_physical_memory(addr, s->vram_size,
3350 s->cirrus_linear_io_addr);
3351 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3352 s->cirrus_linear_bitblt_io_addr);
3353
3354 s->map_addr = s->map_end = 0;
3355 s->lfb_addr = addr & TARGET_PAGE_MASK;
3356 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3357 /* account for overflow */
3358 if (s->lfb_end < addr + VGA_RAM_SIZE)
3359 s->lfb_end = addr + VGA_RAM_SIZE;
3360 vga_dirty_log_start((VGAState *)s);
3361 }
3362
3363 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3364 uint32_t addr, uint32_t size, int type)
3365 {
3366 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3367
3368 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3369 s->cirrus_mmio_io_addr);
3370 }
3371
3372 static void pci_cirrus_write_config(PCIDevice *d,
3373 uint32_t address, uint32_t val, int len)
3374 {
3375 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3376 CirrusVGAState *s = &pvs->cirrus_vga;
3377
3378 vga_dirty_log_stop((VGAState *)s);
3379 pci_default_write_config(d, address, val, len);
3380 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3381 s->map_addr = 0;
3382 cirrus_update_memory_access(s);
3383 vga_dirty_log_start((VGAState *)s);
3384 }
3385
3386 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3387 ram_addr_t vga_ram_offset, int vga_ram_size)
3388 {
3389 PCICirrusVGAState *d;
3390 uint8_t *pci_conf;
3391 CirrusVGAState *s;
3392 int device_id;
3393
3394 device_id = CIRRUS_ID_CLGD5446;
3395
3396 /* setup PCI configuration registers */
3397 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3398 sizeof(PCICirrusVGAState),
3399 -1, NULL, pci_cirrus_write_config);
3400 pci_conf = d->dev.config;
3401 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3402 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3403 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3404 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3405 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3406 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3407 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3408 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3409
3410 /* setup VGA */
3411 s = &d->cirrus_vga;
3412 vga_common_init((VGAState *)s,
3413 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3414 cirrus_init_common(s, device_id, 1);
3415
3416 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3417 s->screen_dump, s->text_update, s);
3418
3419 s->pci_dev = (PCIDevice *)d;
3420
3421 /* setup memory space */
3422 /* memory #0 LFB */
3423 /* memory #1 memory-mapped I/O */
3424 /* XXX: s->vram_size must be a power of two */
3425 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3426 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3427 if (device_id == CIRRUS_ID_CLGD5446) {
3428 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3429 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3430 }
3431 /* XXX: ROM BIOS */
3432 }
Patches shipped by Fedora