hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28 //#define DEBUG_IOAPIC
  29
  30 /* APIC Local Vector Table */
  31 #define APIC_LVT_TIMER   0
  32 #define APIC_LVT_THERMAL 1
  33 #define APIC_LVT_PERFORM 2
  34 #define APIC_LVT_LINT0   3
  35 #define APIC_LVT_LINT1   4
  36 #define APIC_LVT_ERROR   5
  37 #define APIC_LVT_NB      6
  38
  39 /* APIC delivery modes */
  40 #define APIC_DM_FIXED   0
  41 #define APIC_DM_LOWPRI  1
  42 #define APIC_DM_SMI     2
  43 #define APIC_DM_NMI     4
  44 #define APIC_DM_INIT    5
  45 #define APIC_DM_SIPI    6
  46 #define APIC_DM_EXTINT  7
  47
  48 /* APIC destination mode */
  49 #define APIC_DESTMODE_FLAT      0xf
  50 #define APIC_DESTMODE_CLUSTER   1
  51
  52 #define APIC_TRIGGER_EDGE  0
  53 #define APIC_TRIGGER_LEVEL 1
  54
  55 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  56 #define APIC_LVT_MASKED                 (1<<16)
  57 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  58 #define APIC_LVT_REMOTE_IRR             (1<<14)
  59 #define APIC_INPUT_POLARITY             (1<<13)
  60 #define APIC_SEND_PENDING               (1<<12)
  61
  62 /* FIXME: it's now hard coded to be equal with KVM_IOAPIC_NUM_PINS */
  63 #define IOAPIC_NUM_PINS                 0x18
  64 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  65
  66 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  67
  68 #define APIC_SV_ENABLE (1 << 8)
  69
  70 #define MAX_APICS 255
  71 #define MAX_APIC_WORDS 8
  72
  73 typedef struct APICState {
  74     CPUState *cpu_env;
  75     uint32_t apicbase;
  76     uint8_t id;
  77     uint8_t arb_id;
  78     uint8_t tpr;
  79     uint32_t spurious_vec;
  80     uint8_t log_dest;
  81     uint8_t dest_mode;
  82     uint32_t isr[8];  /* in service register */
  83     uint32_t tmr[8];  /* trigger mode register */
  84     uint32_t irr[8]; /* interrupt request register */
  85     uint32_t lvt[APIC_LVT_NB];
  86     uint32_t esr; /* error register */
  87     uint32_t icr[2];
  88
  89     uint32_t divide_conf;
  90     int count_shift;
  91     uint32_t initial_count;
  92     int64_t initial_count_load_time, next_time;
  93     QEMUTimer *timer;
  94 } APICState;
  95
  96 struct IOAPICState {
  97     uint8_t id;
  98     uint8_t ioregsel;
  99     uint64_t base_address;
 100
 101     uint32_t irr;
 102     uint64_t ioredtbl[IOAPIC_NUM_PINS];
 103 };
 104
 105 static int apic_io_memory;
 106 static APICState *local_apics[MAX_APICS + 1];
 107 static int last_apic_id = 0;
 108
 109 static void apic_init_ipi(APICState *s);
 110 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 111 static void apic_update_irq(APICState *s);
 112
 113 /* Find first bit starting from msb */
 114 static int fls_bit(uint32_t value)
 115 {
 116     return 31 - clz32(value);
 117 }
 118
 119 /* Find first bit starting from lsb */
 120 static int ffs_bit(uint32_t value)
 121 {
 122     return ctz32(value);
 123 }
 124
 125 static inline void set_bit(uint32_t *tab, int index)
 126 {
 127     int i, mask;
 128     i = index >> 5;
 129     mask = 1 << (index & 0x1f);
 130     tab[i] |= mask;
 131 }
 132
 133 static inline void reset_bit(uint32_t *tab, int index)
 134 {
 135     int i, mask;
 136     i = index >> 5;
 137     mask = 1 << (index & 0x1f);
 138     tab[i] &= ~mask;
 139 }
 140
 141 static void apic_local_deliver(CPUState *env, int vector)
 142 {
 143     APICState *s = env->apic_state;
 144     uint32_t lvt = s->lvt[vector];
 145     int trigger_mode;
 146
 147     if (lvt & APIC_LVT_MASKED)
 148         return;
 149
 150     switch ((lvt >> 8) & 7) {
 151     case APIC_DM_SMI:
 152         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 153         break;
 154
 155     case APIC_DM_NMI:
 156         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 157         break;
 158
 159     case APIC_DM_EXTINT:
 160         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 161         break;
 162
 163     case APIC_DM_FIXED:
 164         trigger_mode = APIC_TRIGGER_EDGE;
 165         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 166             (lvt & APIC_LVT_LEVEL_TRIGGER))
 167             trigger_mode = APIC_TRIGGER_LEVEL;
 168         apic_set_irq(s, lvt & 0xff, trigger_mode);
 169     }
 170 }
 171
 172 void apic_deliver_pic_intr(CPUState *env, int level)
 173 {
 174     if (level)
 175         apic_local_deliver(env, APIC_LVT_LINT0);
 176     else {
 177         APICState *s = env->apic_state;
 178         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 179
 180         switch ((lvt >> 8) & 7) {
 181         case APIC_DM_FIXED:
 182             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 183                 break;
 184             reset_bit(s->irr, lvt & 0xff);
 185             /* fall through */
 186         case APIC_DM_EXTINT:
 187             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 188             break;
 189         }
 190     }
 191 }
 192
 193 #define foreach_apic(apic, deliver_bitmask, code) \
 194 {\
 195     int __i, __j, __mask;\
 196     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 197         __mask = deliver_bitmask[__i];\
 198         if (__mask) {\
 199             for(__j = 0; __j < 32; __j++) {\
 200                 if (__mask & (1 << __j)) {\
 201                     apic = local_apics[__i * 32 + __j];\
 202                     if (apic) {\
 203                         code;\
 204                     }\
 205                 }\
 206             }\
 207         }\
 208     }\
 209 }
 210
 211 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 212                              uint8_t delivery_mode,
 213                              uint8_t vector_num, uint8_t polarity,
 214                              uint8_t trigger_mode)
 215 {
 216     APICState *apic_iter;
 217
 218     switch (delivery_mode) {
 219         case APIC_DM_LOWPRI:
 220             /* XXX: search for focus processor, arbitration */
 221             {
 222                 int i, d;
 223                 d = -1;
 224                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 225                     if (deliver_bitmask[i]) {
 226                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 227                         break;
 228                     }
 229                 }
 230                 if (d >= 0) {
 231                     apic_iter = local_apics[d];
 232                     if (apic_iter) {
 233                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 234                     }
 235                 }
 236             }
 237             return;
 238
 239         case APIC_DM_FIXED:
 240             break;
 241
 242         case APIC_DM_SMI:
 243             foreach_apic(apic_iter, deliver_bitmask,
 244                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 245             return;
 246
 247         case APIC_DM_NMI:
 248             foreach_apic(apic_iter, deliver_bitmask,
 249                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 250             return;
 251
 252         case APIC_DM_INIT:
 253             /* normal INIT IPI sent to processors */
 254             foreach_apic(apic_iter, deliver_bitmask,
 255                          apic_init_ipi(apic_iter) );
 256             return;
 257
 258         case APIC_DM_EXTINT:
 259             /* handled in I/O APIC code */
 260             break;
 261
 262         default:
 263             return;
 264     }
 265
 266     foreach_apic(apic_iter, deliver_bitmask,
 267                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 268 }
 269
 270 void cpu_set_apic_base(CPUState *env, uint64_t val)
 271 {
 272     APICState *s = env->apic_state;
 273 #ifdef DEBUG_APIC
 274     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 275 #endif
 276     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 277         s->apicbase = val;
 278     else
 279         s->apicbase = (val & 0xfffff000) |
 280             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 281     /* if disabled, cannot be enabled again */
 282     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 283         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 284         env->cpuid_features &= ~CPUID_APIC;
 285         s->spurious_vec &= ~APIC_SV_ENABLE;
 286     }
 287 }
 288
 289 uint64_t cpu_get_apic_base(CPUState *env)
 290 {
 291     APICState *s = env->apic_state;
 292 #ifdef DEBUG_APIC
 293     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 294 #endif
 295     return s->apicbase;
 296 }
 297
 298 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 299 {
 300     APICState *s = env->apic_state;
 301     s->tpr = (val & 0x0f) << 4;
 302     apic_update_irq(s);
 303 }
 304
 305 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 306 {
 307     APICState *s = env->apic_state;
 308     return s->tpr >> 4;
 309 }
 310
 311 /* return -1 if no bit is set */
 312 static int get_highest_priority_int(uint32_t *tab)
 313 {
 314     int i;
 315     for(i = 7; i >= 0; i--) {
 316         if (tab[i] != 0) {
 317             return i * 32 + fls_bit(tab[i]);
 318         }
 319     }
 320     return -1;
 321 }
 322
 323 static int apic_get_ppr(APICState *s)
 324 {
 325     int tpr, isrv, ppr;
 326
 327     tpr = (s->tpr >> 4);
 328     isrv = get_highest_priority_int(s->isr);
 329     if (isrv < 0)
 330         isrv = 0;
 331     isrv >>= 4;
 332     if (tpr >= isrv)
 333         ppr = s->tpr;
 334     else
 335         ppr = isrv << 4;
 336     return ppr;
 337 }
 338
 339 static int apic_get_arb_pri(APICState *s)
 340 {
 341     /* XXX: arbitration */
 342     return 0;
 343 }
 344
 345 /* signal the CPU if an irq is pending */
 346 static void apic_update_irq(APICState *s)
 347 {
 348     int irrv, ppr;
 349     if (!(s->spurious_vec & APIC_SV_ENABLE))
 350         return;
 351     irrv = get_highest_priority_int(s->irr);
 352     if (irrv < 0)
 353         return;
 354     ppr = apic_get_ppr(s);
 355     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 356         return;
 357     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 358 }
 359
 360 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 361 {
 362     set_bit(s->irr, vector_num);
 363     if (trigger_mode)
 364         set_bit(s->tmr, vector_num);
 365     else
 366         reset_bit(s->tmr, vector_num);
 367     apic_update_irq(s);
 368 }
 369
 370 static void apic_eoi(APICState *s)
 371 {
 372     int isrv;
 373     isrv = get_highest_priority_int(s->isr);
 374     if (isrv < 0)
 375         return;
 376     reset_bit(s->isr, isrv);
 377     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 378             set the remote IRR bit for level triggered interrupts. */
 379     apic_update_irq(s);
 380 }
 381
 382 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 383                                       uint8_t dest, uint8_t dest_mode)
 384 {
 385     APICState *apic_iter;
 386     int i;
 387
 388     if (dest_mode == 0) {
 389         if (dest == 0xff) {
 390             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 391         } else {
 392             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 393             set_bit(deliver_bitmask, dest);
 394         }
 395     } else {
 396         /* XXX: cluster mode */
 397         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 398         for(i = 0; i < MAX_APICS; i++) {
 399             apic_iter = local_apics[i];
 400             if (apic_iter) {
 401                 if (apic_iter->dest_mode == 0xf) {
 402                     if (dest & apic_iter->log_dest)
 403                         set_bit(deliver_bitmask, i);
 404                 } else if (apic_iter->dest_mode == 0x0) {
 405                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 406                         (dest & apic_iter->log_dest & 0x0f)) {
 407                         set_bit(deliver_bitmask, i);
 408                     }
 409                 }
 410             }
 411         }
 412     }
 413 }
 414
 415
 416 static void apic_init_ipi(APICState *s)
 417 {
 418     int i;
 419
 420     s->tpr = 0;
 421     s->spurious_vec = 0xff;
 422     s->log_dest = 0;
 423     s->dest_mode = 0xf;
 424     memset(s->isr, 0, sizeof(s->isr));
 425     memset(s->tmr, 0, sizeof(s->tmr));
 426     memset(s->irr, 0, sizeof(s->irr));
 427     for(i = 0; i < APIC_LVT_NB; i++)
 428         s->lvt[i] = 1 << 16; /* mask LVT */
 429     s->esr = 0;
 430     memset(s->icr, 0, sizeof(s->icr));
 431     s->divide_conf = 0;
 432     s->count_shift = 0;
 433     s->initial_count = 0;
 434     s->initial_count_load_time = 0;
 435     s->next_time = 0;
 436
 437     cpu_reset(s->cpu_env);
 438
 439     if (!(s->apicbase & MSR_IA32_APICBASE_BSP) &&
 440         (!kvm_enabled() || !qemu_kvm_irqchip_in_kernel()))
 441         s->cpu_env->halted = 1;
 442
 443     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 444         if (s->cpu_env)
 445             kvm_apic_init(s->cpu_env);
 446 }
 447
 448 /* send a SIPI message to the CPU to start it */
 449 static void apic_startup(APICState *s, int vector_num)
 450 {
 451     CPUState *env = s->cpu_env;
 452     if (!env->halted)
 453         return;
 454     env->eip = 0;
 455     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 456                            0xffff, 0);
 457     env->halted = 0;
 458     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 459         kvm_update_after_sipi(env);
 460 }
 461
 462 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 463                          uint8_t delivery_mode, uint8_t vector_num,
 464                          uint8_t polarity, uint8_t trigger_mode)
 465 {
 466     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 467     int dest_shorthand = (s->icr[0] >> 18) & 3;
 468     APICState *apic_iter;
 469
 470     switch (dest_shorthand) {
 471     case 0:
 472         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 473         break;
 474     case 1:
 475         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 476         set_bit(deliver_bitmask, s->id);
 477         break;
 478     case 2:
 479         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 480         break;
 481     case 3:
 482         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 483         reset_bit(deliver_bitmask, s->id);
 484         break;
 485     }
 486
 487     switch (delivery_mode) {
 488         case APIC_DM_INIT:
 489             {
 490                 int trig_mode = (s->icr[0] >> 15) & 1;
 491                 int level = (s->icr[0] >> 14) & 1;
 492                 if (level == 0 && trig_mode == 1) {
 493                     foreach_apic(apic_iter, deliver_bitmask,
 494                                  apic_iter->arb_id = apic_iter->id );
 495                     return;
 496                 }
 497             }
 498             break;
 499
 500         case APIC_DM_SIPI:
 501             foreach_apic(apic_iter, deliver_bitmask,
 502                          apic_startup(apic_iter, vector_num) );
 503             return;
 504     }
 505
 506     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 507                      trigger_mode);
 508 }
 509
 510 int apic_get_interrupt(CPUState *env)
 511 {
 512     APICState *s = env->apic_state;
 513     int intno;
 514
 515     /* if the APIC is installed or enabled, we let the 8259 handle the
 516        IRQs */
 517     if (!s)
 518         return -1;
 519     if (!(s->spurious_vec & APIC_SV_ENABLE))
 520         return -1;
 521
 522     /* XXX: spurious IRQ handling */
 523     intno = get_highest_priority_int(s->irr);
 524     if (intno < 0)
 525         return -1;
 526     if (s->tpr && intno <= s->tpr)
 527         return s->spurious_vec & 0xff;
 528     reset_bit(s->irr, intno);
 529     set_bit(s->isr, intno);
 530     apic_update_irq(s);
 531     return intno;
 532 }
 533
 534 int apic_accept_pic_intr(CPUState *env)
 535 {
 536     APICState *s = env->apic_state;
 537     uint32_t lvt0;
 538
 539     if (!s)
 540         return -1;
 541
 542     lvt0 = s->lvt[APIC_LVT_LINT0];
 543
 544     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 545         (lvt0 & APIC_LVT_MASKED) == 0)
 546         return 1;
 547
 548     return 0;
 549 }
 550
 551 static uint32_t apic_get_current_count(APICState *s)
 552 {
 553     int64_t d;
 554     uint32_t val;
 555     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 556         s->count_shift;
 557     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 558         /* periodic */
 559         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 560     } else {
 561         if (d >= s->initial_count)
 562             val = 0;
 563         else
 564             val = s->initial_count - d;
 565     }
 566     return val;
 567 }
 568
 569 static void apic_timer_update(APICState *s, int64_t current_time)
 570 {
 571     int64_t next_time, d;
 572
 573     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 574         d = (current_time - s->initial_count_load_time) >>
 575             s->count_shift;
 576         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 577             if (!s->initial_count)
 578                 goto no_timer;
 579             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 580         } else {
 581             if (d >= s->initial_count)
 582                 goto no_timer;
 583             d = (uint64_t)s->initial_count + 1;
 584         }
 585         next_time = s->initial_count_load_time + (d << s->count_shift);
 586         qemu_mod_timer(s->timer, next_time);
 587         s->next_time = next_time;
 588     } else {
 589     no_timer:
 590         qemu_del_timer(s->timer);
 591     }
 592 }
 593
 594 static void apic_timer(void *opaque)
 595 {
 596     APICState *s = opaque;
 597
 598     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 599     apic_timer_update(s, s->next_time);
 600 }
 601
 602 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 603 {
 604     return 0;
 605 }
 606
 607 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 608 {
 609     return 0;
 610 }
 611
 612 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 613 {
 614 }
 615
 616 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 617 {
 618 }
 619
 620 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 621 {
 622     CPUState *env;
 623     APICState *s;
 624     uint32_t val;
 625     int index;
 626
 627     env = cpu_single_env;
 628     if (!env)
 629         return 0;
 630     s = env->apic_state;
 631
 632     index = (addr >> 4) & 0xff;
 633     switch(index) {
 634     case 0x02: /* id */
 635         val = s->id << 24;
 636         break;
 637     case 0x03: /* version */
 638         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 639         break;
 640     case 0x08:
 641         val = s->tpr;
 642         break;
 643     case 0x09:
 644         val = apic_get_arb_pri(s);
 645         break;
 646     case 0x0a:
 647         /* ppr */
 648         val = apic_get_ppr(s);
 649         break;
 650     case 0x0b:
 651         val = 0;
 652         break;
 653     case 0x0d:
 654         val = s->log_dest << 24;
 655         break;
 656     case 0x0e:
 657         val = s->dest_mode << 28;
 658         break;
 659     case 0x0f:
 660         val = s->spurious_vec;
 661         break;
 662     case 0x10 ... 0x17:
 663         val = s->isr[index & 7];
 664         break;
 665     case 0x18 ... 0x1f:
 666         val = s->tmr[index & 7];
 667         break;
 668     case 0x20 ... 0x27:
 669         val = s->irr[index & 7];
 670         break;
 671     case 0x28:
 672         val = s->esr;
 673         break;
 674     case 0x30:
 675     case 0x31:
 676         val = s->icr[index & 1];
 677         break;
 678     case 0x32 ... 0x37:
 679         val = s->lvt[index - 0x32];
 680         break;
 681     case 0x38:
 682         val = s->initial_count;
 683         break;
 684     case 0x39:
 685         val = apic_get_current_count(s);
 686         break;
 687     case 0x3e:
 688         val = s->divide_conf;
 689         break;
 690     default:
 691         s->esr |= ESR_ILLEGAL_ADDRESS;
 692         val = 0;
 693         break;
 694     }
 695 #ifdef DEBUG_APIC
 696     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 697 #endif
 698     return val;
 699 }
 700
 701 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 702 {
 703     CPUState *env;
 704     APICState *s;
 705     int index;
 706
 707     env = cpu_single_env;
 708     if (!env)
 709         return;
 710     s = env->apic_state;
 711
 712 #ifdef DEBUG_APIC
 713     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 714 #endif
 715
 716     index = (addr >> 4) & 0xff;
 717     switch(index) {
 718     case 0x02:
 719         s->id = (val >> 24);
 720         break;
 721     case 0x03:
 722         break;
 723     case 0x08:
 724         s->tpr = val;
 725         apic_update_irq(s);
 726         break;
 727     case 0x09:
 728     case 0x0a:
 729         break;
 730     case 0x0b: /* EOI */
 731         apic_eoi(s);
 732         break;
 733     case 0x0d:
 734         s->log_dest = val >> 24;
 735         break;
 736     case 0x0e:
 737         s->dest_mode = val >> 28;
 738         break;
 739     case 0x0f:
 740         s->spurious_vec = val & 0x1ff;
 741         apic_update_irq(s);
 742         break;
 743     case 0x10 ... 0x17:
 744     case 0x18 ... 0x1f:
 745     case 0x20 ... 0x27:
 746     case 0x28:
 747         break;
 748     case 0x30:
 749         s->icr[0] = val;
 750         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 751                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 752                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 753         break;
 754     case 0x31:
 755         s->icr[1] = val;
 756         break;
 757     case 0x32 ... 0x37:
 758         {
 759             int n = index - 0x32;
 760             s->lvt[n] = val;
 761             if (n == APIC_LVT_TIMER)
 762                 apic_timer_update(s, qemu_get_clock(vm_clock));
 763         }
 764         break;
 765     case 0x38:
 766         s->initial_count = val;
 767         s->initial_count_load_time = qemu_get_clock(vm_clock);
 768         apic_timer_update(s, s->initial_count_load_time);
 769         break;
 770     case 0x39:
 771         break;
 772     case 0x3e:
 773         {
 774             int v;
 775             s->divide_conf = val & 0xb;
 776             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 777             s->count_shift = (v + 1) & 7;
 778         }
 779         break;
 780     default:
 781         s->esr |= ESR_ILLEGAL_ADDRESS;
 782         break;
 783     }
 784 }
 785
 786 #ifdef KVM_CAP_IRQCHIP
 787
 788 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 789 {
 790     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 791 }
 792
 793 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 794                                  int reg_id, uint32_t val)
 795 {
 796     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 797 }
 798
 799 static void kvm_kernel_lapic_save_to_user(APICState *s)
 800 {
 801     struct kvm_lapic_state apic;
 802     struct kvm_lapic_state *kapic = &apic;
 803     int i, v;
 804
 805     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 806
 807     s->id = kapic_reg(kapic, 0x2);
 808     s->tpr = kapic_reg(kapic, 0x8);
 809     s->arb_id = kapic_reg(kapic, 0x9);
 810     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 811     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 812     s->spurious_vec = kapic_reg(kapic, 0xf);
 813     for (i = 0; i < 8; i++) {
 814         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 815         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 816         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 817     }
 818     s->esr = kapic_reg(kapic, 0x28);
 819     s->icr[0] = kapic_reg(kapic, 0x30);
 820     s->icr[1] = kapic_reg(kapic, 0x31);
 821     for (i = 0; i < APIC_LVT_NB; i++)
 822         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 823     s->initial_count = kapic_reg(kapic, 0x38);
 824     s->divide_conf = kapic_reg(kapic, 0x3e);
 825
 826     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 827     s->count_shift = (v + 1) & 7;
 828
 829     s->initial_count_load_time = qemu_get_clock(vm_clock);
 830     apic_timer_update(s, s->initial_count_load_time);
 831 }
 832
 833 static void kvm_kernel_lapic_load_from_user(APICState *s)
 834 {
 835     struct kvm_lapic_state apic;
 836     struct kvm_lapic_state *klapic = &apic;
 837     int i;
 838
 839     memset(klapic, 0, sizeof apic);
 840     kapic_set_reg(klapic, 0x2, s->id);
 841     kapic_set_reg(klapic, 0x8, s->tpr);
 842     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 843     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 844     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 845     for (i = 0; i < 8; i++) {
 846         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 847         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 848         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 849     }
 850     kapic_set_reg(klapic, 0x28, s->esr);
 851     kapic_set_reg(klapic, 0x30, s->icr[0]);
 852     kapic_set_reg(klapic, 0x31, s->icr[1]);
 853     for (i = 0; i < APIC_LVT_NB; i++)
 854         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 855     kapic_set_reg(klapic, 0x38, s->initial_count);
 856     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 857
 858     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 859 }
 860
 861 #endif
 862
 863 static void apic_save(QEMUFile *f, void *opaque)
 864 {
 865     APICState *s = opaque;
 866     int i;
 867
 868 #ifdef KVM_CAP_IRQCHIP
 869     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 870         kvm_kernel_lapic_save_to_user(s);
 871     }
 872 #endif
 873
 874     qemu_put_be32s(f, &s->apicbase);
 875     qemu_put_8s(f, &s->id);
 876     qemu_put_8s(f, &s->arb_id);
 877     qemu_put_8s(f, &s->tpr);
 878     qemu_put_be32s(f, &s->spurious_vec);
 879     qemu_put_8s(f, &s->log_dest);
 880     qemu_put_8s(f, &s->dest_mode);
 881     for (i = 0; i < 8; i++) {
 882         qemu_put_be32s(f, &s->isr[i]);
 883         qemu_put_be32s(f, &s->tmr[i]);
 884         qemu_put_be32s(f, &s->irr[i]);
 885     }
 886     for (i = 0; i < APIC_LVT_NB; i++) {
 887         qemu_put_be32s(f, &s->lvt[i]);
 888     }
 889     qemu_put_be32s(f, &s->esr);
 890     qemu_put_be32s(f, &s->icr[0]);
 891     qemu_put_be32s(f, &s->icr[1]);
 892     qemu_put_be32s(f, &s->divide_conf);
 893     qemu_put_be32(f, s->count_shift);
 894     qemu_put_be32s(f, &s->initial_count);
 895     qemu_put_be64(f, s->initial_count_load_time);
 896     qemu_put_be64(f, s->next_time);
 897
 898     qemu_put_timer(f, s->timer);
 899 }
 900
 901 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 902 {
 903     APICState *s = opaque;
 904     int i;
 905
 906     if (version_id > 2)
 907         return -EINVAL;
 908
 909     /* XXX: what if the base changes? (registered memory regions) */
 910     qemu_get_be32s(f, &s->apicbase);
 911     qemu_get_8s(f, &s->id);
 912     qemu_get_8s(f, &s->arb_id);
 913     qemu_get_8s(f, &s->tpr);
 914     qemu_get_be32s(f, &s->spurious_vec);
 915     qemu_get_8s(f, &s->log_dest);
 916     qemu_get_8s(f, &s->dest_mode);
 917     for (i = 0; i < 8; i++) {
 918         qemu_get_be32s(f, &s->isr[i]);
 919         qemu_get_be32s(f, &s->tmr[i]);
 920         qemu_get_be32s(f, &s->irr[i]);
 921     }
 922     for (i = 0; i < APIC_LVT_NB; i++) {
 923         qemu_get_be32s(f, &s->lvt[i]);
 924     }
 925     qemu_get_be32s(f, &s->esr);
 926     qemu_get_be32s(f, &s->icr[0]);
 927     qemu_get_be32s(f, &s->icr[1]);
 928     qemu_get_be32s(f, &s->divide_conf);
 929     s->count_shift=qemu_get_be32(f);
 930     qemu_get_be32s(f, &s->initial_count);
 931     s->initial_count_load_time=qemu_get_be64(f);
 932     s->next_time=qemu_get_be64(f);
 933
 934     if (version_id >= 2)
 935         qemu_get_timer(f, s->timer);
 936
 937 #ifdef KVM_CAP_IRQCHIP
 938     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 939         kvm_kernel_lapic_load_from_user(s);
 940     }
 941 #endif
 942
 943     return 0;
 944 }
 945
 946 static void apic_reset(void *opaque)
 947 {
 948     APICState *s = opaque;
 949
 950     s->apicbase = 0xfee00000 |
 951         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 952
 953     apic_init_ipi(s);
 954
 955     if (s->id == 0) {
 956         /*
 957          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 958          * time typically by BIOS, so PIC interrupt can be delivered to the
 959          * processor when local APIC is enabled.
 960          */
 961         s->lvt[APIC_LVT_LINT0] = 0x700;
 962     }
 963 #ifdef KVM_CAP_IRQCHIP
 964     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 965         kvm_kernel_lapic_load_from_user(s);
 966     }
 967 #endif
 968 }
 969
 970 static CPUReadMemoryFunc *apic_mem_read[3] = {
 971     apic_mem_readb,
 972     apic_mem_readw,
 973     apic_mem_readl,
 974 };
 975
 976 static CPUWriteMemoryFunc *apic_mem_write[3] = {
 977     apic_mem_writeb,
 978     apic_mem_writew,
 979     apic_mem_writel,
 980 };
 981
 982 int apic_init(CPUState *env)
 983 {
 984     APICState *s;
 985
 986     if (last_apic_id >= MAX_APICS)
 987         return -1;
 988     s = qemu_mallocz(sizeof(APICState));
 989     if (!s)
 990         return -1;
 991     env->apic_state = s;
 992     s->id = last_apic_id++;
 993     env->cpuid_apic_id = s->id;
 994     s->cpu_env = env;
 995
 996     apic_reset(s);
 997
 998     /* XXX: mapping more APICs at the same memory location */
 999     if (apic_io_memory == 0) {
1000         /* NOTE: the APIC is directly connected to the CPU - it is not
1001            on the global memory bus. */
1002         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1003                                                 apic_mem_write, NULL);
1004         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1005                                      apic_io_memory);
1006     }
1007     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1008
1009     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
1010     qemu_register_reset(apic_reset, s);
1011
1012     local_apics[s->id] = s;
1013     return 0;
1014 }
1015
1016 static void ioapic_service(IOAPICState *s)
1017 {
1018     uint8_t i;
1019     uint8_t trig_mode;
1020     uint8_t vector;
1021     uint8_t delivery_mode;
1022     uint32_t mask;
1023     uint64_t entry;
1024     uint8_t dest;
1025     uint8_t dest_mode;
1026     uint8_t polarity;
1027     uint32_t deliver_bitmask[MAX_APIC_WORDS];
1028
1029     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1030         mask = 1 << i;
1031         if (s->irr & mask) {
1032             entry = s->ioredtbl[i];
1033             if (!(entry & APIC_LVT_MASKED)) {
1034                 trig_mode = ((entry >> 15) & 1);
1035                 dest = entry >> 56;
1036                 dest_mode = (entry >> 11) & 1;
1037                 delivery_mode = (entry >> 8) & 7;
1038                 polarity = (entry >> 13) & 1;
1039                 if (trig_mode == APIC_TRIGGER_EDGE)
1040                     s->irr &= ~mask;
1041                 if (delivery_mode == APIC_DM_EXTINT)
1042                     vector = pic_read_irq(isa_pic);
1043                 else
1044                     vector = entry & 0xff;
1045
1046                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
1047                 apic_bus_deliver(deliver_bitmask, delivery_mode,
1048                                  vector, polarity, trig_mode);
1049             }
1050         }
1051     }
1052 }
1053
1054 void ioapic_set_irq(void *opaque, int vector, int level)
1055 {
1056     IOAPICState *s = opaque;
1057
1058 #if 0
1059     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
1060      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
1061      * the cleanest way of doing it but it should work. */
1062
1063     if (vector == 0)
1064         vector = 2;
1065 #endif
1066
1067     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1068         uint32_t mask = 1 << vector;
1069         uint64_t entry = s->ioredtbl[vector];
1070
1071         if ((entry >> 15) & 1) {
1072             /* level triggered */
1073             if (level) {
1074                 s->irr |= mask;
1075                 ioapic_service(s);
1076             } else {
1077                 s->irr &= ~mask;
1078             }
1079         } else {
1080             /* edge triggered */
1081             if (level) {
1082                 s->irr |= mask;
1083                 ioapic_service(s);
1084             }
1085         }
1086     }
1087 }
1088
1089 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1090 {
1091     IOAPICState *s = opaque;
1092     int index;
1093     uint32_t val = 0;
1094
1095     addr &= 0xff;
1096     if (addr == 0x00) {
1097         val = s->ioregsel;
1098     } else if (addr == 0x10) {
1099         switch (s->ioregsel) {
1100             case 0x00:
1101                 val = s->id << 24;
1102                 break;
1103             case 0x01:
1104                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1105                 break;
1106             case 0x02:
1107                 val = 0;
1108                 break;
1109             default:
1110                 index = (s->ioregsel - 0x10) >> 1;
1111                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1112                     if (s->ioregsel & 1)
1113                         val = s->ioredtbl[index] >> 32;
1114                     else
1115                         val = s->ioredtbl[index] & 0xffffffff;
1116                 }
1117         }
1118 #ifdef DEBUG_IOAPIC
1119         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1120 #endif
1121     }
1122     return val;
1123 }
1124
1125 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1126 {
1127     IOAPICState *s = opaque;
1128     int index;
1129
1130     addr &= 0xff;
1131     if (addr == 0x00)  {
1132         s->ioregsel = val;
1133         return;
1134     } else if (addr == 0x10) {
1135 #ifdef DEBUG_IOAPIC
1136         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1137 #endif
1138         switch (s->ioregsel) {
1139             case 0x00:
1140                 s->id = (val >> 24) & 0xff;
1141                 return;
1142             case 0x01:
1143             case 0x02:
1144                 return;
1145             default:
1146                 index = (s->ioregsel - 0x10) >> 1;
1147                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1148                     if (s->ioregsel & 1) {
1149                         s->ioredtbl[index] &= 0xffffffff;
1150                         s->ioredtbl[index] |= (uint64_t)val << 32;
1151                     } else {
1152                         s->ioredtbl[index] &= ~0xffffffffULL;
1153                         s->ioredtbl[index] |= val;
1154                     }
1155                     ioapic_service(s);
1156                 }
1157         }
1158     }
1159 }
1160
1161 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
1162 {
1163 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1164     struct kvm_irqchip chip;
1165     struct kvm_ioapic_state *kioapic;
1166     int i;
1167
1168     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1169     kvm_get_irqchip(kvm_context, &chip);
1170     kioapic = &chip.chip.ioapic;
1171
1172     s->id = kioapic->id;
1173     s->ioregsel = kioapic->ioregsel;
1174     s->base_address = kioapic->base_address;
1175     s->irr = kioapic->irr;
1176     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1177         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
1178     }
1179 #endif
1180 }
1181
1182 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
1183 {
1184 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
1185     struct kvm_irqchip chip;
1186     struct kvm_ioapic_state *kioapic;
1187     int i;
1188
1189     chip.chip_id = KVM_IRQCHIP_IOAPIC;
1190     kioapic = &chip.chip.ioapic;
1191
1192     kioapic->id = s->id;
1193     kioapic->ioregsel = s->ioregsel;
1194     kioapic->base_address = s->base_address;
1195     kioapic->irr = s->irr;
1196     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1197         kioapic->redirtbl[i].bits = s->ioredtbl[i];
1198     }
1199
1200     kvm_set_irqchip(kvm_context, &chip);
1201 #endif
1202 }
1203
1204 static void ioapic_save(QEMUFile *f, void *opaque)
1205 {
1206     IOAPICState *s = opaque;
1207     int i;
1208
1209     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1210         kvm_kernel_ioapic_save_to_user(s);
1211     }
1212
1213     qemu_put_8s(f, &s->id);
1214     qemu_put_8s(f, &s->ioregsel);
1215     qemu_put_be64s(f, &s->base_address);
1216     qemu_put_be32s(f, &s->irr);
1217     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1218         qemu_put_be64s(f, &s->ioredtbl[i]);
1219     }
1220 }
1221
1222 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1223 {
1224     IOAPICState *s = opaque;
1225     int i;
1226
1227     if (version_id < 1 || version_id > 2)
1228         return -EINVAL;
1229
1230     qemu_get_8s(f, &s->id);
1231     qemu_get_8s(f, &s->ioregsel);
1232     if (version_id == 2) {
1233       /* for version 2, we get this data off of the wire */
1234       qemu_get_be64s(f, &s->base_address);
1235       qemu_get_be32s(f, &s->irr);
1236     }
1237     else {
1238       /* in case we are doing version 1, we just set these to sane values */
1239       s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1240       s->irr = 0;
1241     }
1242     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1243         qemu_get_be64s(f, &s->ioredtbl[i]);
1244     }
1245
1246     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1247         kvm_kernel_ioapic_load_from_user(s);
1248     }
1249
1250     return 0;
1251 }
1252
1253 static void ioapic_reset(void *opaque)
1254 {
1255     IOAPICState *s = opaque;
1256     int i;
1257
1258     memset(s, 0, sizeof(*s));
1259     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
1260     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1261         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1262 #ifdef KVM_CAP_IRQCHIP
1263     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
1264         kvm_kernel_ioapic_load_from_user(s);
1265     }
1266 #endif
1267 }
1268
1269 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1270     ioapic_mem_readl,
1271     ioapic_mem_readl,
1272     ioapic_mem_readl,
1273 };
1274
1275 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1276     ioapic_mem_writel,
1277     ioapic_mem_writel,
1278     ioapic_mem_writel,
1279 };
1280
1281 IOAPICState *ioapic_init(void)
1282 {
1283     IOAPICState *s;
1284     int io_memory;
1285
1286     s = qemu_mallocz(sizeof(IOAPICState));
1287     if (!s)
1288         return NULL;
1289     ioapic_reset(s);
1290     s->id = last_apic_id++;
1291
1292     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1293                                        ioapic_mem_write, s);
1294     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1295
1296     register_savevm("ioapic", 0, 2, ioapic_save, ioapic_load, s);
1297     qemu_register_reset(ioapic_reset, s);
1298
1299     return s;
1300 }