hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "fdc.h"
  30 #include "sysemu.h"
  31 #include "audio/audio.h"
  32 #include "boards.h"
  33 #include "net.h"
  34 #include "scsi.h"
  35
  36 #ifdef TARGET_WORDS_BIGENDIAN
  37 #define BIOS_FILENAME "mips_bios.bin"
  38 #else
  39 #define BIOS_FILENAME "mipsel_bios.bin"
  40 #endif
  41
  42 enum jazz_model_e
  43 {
  44     JAZZ_MAGNUM,
  45     JAZZ_PICA61,
  46 };
  47
  48 static void main_cpu_reset(void *opaque)
  49 {
  50     CPUState *env = opaque;
  51     cpu_reset(env);
  52 }
  53
  54 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
  55 {
  56     CPUState *env = opaque;
  57     return cpu_inw(env, 0x71);
  58 }
  59
  60 static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  61 {
  62     CPUState *env = opaque;
  63     cpu_outw(env, 0x71, val & 0xff);
  64 }
  65
  66 static CPUReadMemoryFunc *rtc_read[3] = {
  67     rtc_readb,
  68     rtc_readb,
  69     rtc_readb,
  70 };
  71
  72 static CPUWriteMemoryFunc *rtc_write[3] = {
  73     rtc_writeb,
  74     rtc_writeb,
  75     rtc_writeb,
  76 };
  77
  78 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  79 {
  80     /* Nothing to do. That is only to ensure that
  81      * the current DMA acknowledge cycle is completed. */
  82 }
  83
  84 static CPUReadMemoryFunc *dma_dummy_read[3] = {
  85     NULL,
  86     NULL,
  87     NULL,
  88 };
  89
  90 static CPUWriteMemoryFunc *dma_dummy_write[3] = {
  91     dma_dummy_writeb,
  92     dma_dummy_writeb,
  93     dma_dummy_writeb,
  94 };
  95
  96 #ifdef HAS_AUDIO
  97 static void audio_init(qemu_irq *pic)
  98 {
  99     struct soundhw *c;
 100     int audio_enabled = 0;
 101
 102     for (c = soundhw; !audio_enabled && c->name; ++c) {
 103         audio_enabled = c->enabled;
 104     }
 105
 106     if (audio_enabled) {
 107         for (c = soundhw; c->name; ++c) {
 108             if (c->enabled) {
 109                 if (c->isa) {
 110                     c->init.init_isa(pic);
 111                 }
 112             }
 113         }
 114     }
 115 }
 116 #endif
 117
 118 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 119 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 120
 121 static
 122 void mips_jazz_init (ram_addr_t ram_size,
 123                      const char *cpu_model,
 124                      enum jazz_model_e jazz_model)
 125 {
 126     char buf[1024];
 127     int bios_size, n;
 128     CPUState *env;
 129     qemu_irq *rc4030, *i8259;
 130     rc4030_dma *dmas;
 131     void* rc4030_opaque;
 132     int s_rtc, s_dma_dummy;
 133     NICInfo *nd;
 134     PITState *pit;
 135     BlockDriverState *fds[MAX_FD];
 136     qemu_irq esp_reset;
 137     ram_addr_t ram_offset;
 138     ram_addr_t bios_offset;
 139
 140     /* init CPUs */
 141     if (cpu_model == NULL) {
 142 #ifdef TARGET_MIPS64
 143         cpu_model = "R4000";
 144 #else
 145         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 146         cpu_model = "24Kf";
 147 #endif
 148     }
 149     env = cpu_init(cpu_model);
 150     if (!env) {
 151         fprintf(stderr, "Unable to find CPU definition\n");
 152         exit(1);
 153     }
 154     qemu_register_reset(main_cpu_reset, env);
 155
 156     /* allocate RAM */
 157     ram_offset = qemu_ram_alloc(ram_size);
 158     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 159
 160     bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
 161     cpu_register_physical_memory(0x1fc00000LL,
 162                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 163     cpu_register_physical_memory(0xfff00000LL,
 164                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 165
 166     /* load the BIOS image. */
 167     if (bios_name == NULL)
 168         bios_name = BIOS_FILENAME;
 169     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 170     bios_size = load_image_targphys(buf, 0xfff00000LL, MAGNUM_BIOS_SIZE);
 171     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 172         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 173                 buf);
 174         exit(1);
 175     }
 176
 177     /* Init CPU internal devices */
 178     cpu_mips_irq_init_cpu(env);
 179     cpu_mips_clock_init(env);
 180
 181     /* Chipset */
 182     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
 183     s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
 184     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 185
 186     /* ISA devices */
 187     i8259 = i8259_init(env->irq[4]);
 188     DMA_init(0);
 189     pit = pit_init(0x40, i8259[0]);
 190     pcspk_init(pit);
 191
 192     /* ISA IO space at 0x90000000 */
 193     isa_mmio_init(0x90000000, 0x01000000);
 194     isa_mem_base = 0x11000000;
 195
 196     /* Video card */
 197     switch (jazz_model) {
 198     case JAZZ_MAGNUM:
 199         g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
 200         break;
 201     case JAZZ_PICA61:
 202         isa_vga_mm_init(0x40000000, 0x60000000, 0);
 203         break;
 204     default:
 205         break;
 206     }
 207
 208     /* Network controller */
 209     for (n = 0; n < nb_nics; n++) {
 210         nd = &nd_table[n];
 211         if (!nd->model)
 212             nd->model = "dp83932";
 213         if (strcmp(nd->model, "dp83932") == 0) {
 214             dp83932_init(nd, 0x80001000, 2, rc4030[4],
 215                          rc4030_opaque, rc4030_dma_memory_rw);
 216             break;
 217         } else if (strcmp(nd->model, "?") == 0) {
 218             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 219             exit(1);
 220         } else {
 221             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 222             exit(1);
 223         }
 224     }
 225
 226     /* SCSI adapter */
 227     esp_init(0x80002000, 0,
 228              rc4030_dma_read, rc4030_dma_write, dmas[0],
 229              rc4030[5], &esp_reset);
 230
 231     /* Floppy */
 232     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 233         fprintf(stderr, "qemu: too many floppy drives\n");
 234         exit(1);
 235     }
 236     for (n = 0; n < MAX_FD; n++) {
 237         int fd = drive_get_index(IF_FLOPPY, 0, n);
 238         if (fd != -1)
 239             fds[n] = drives_table[fd].bdrv;
 240         else
 241             fds[n] = NULL;
 242     }
 243     fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
 244
 245     /* Real time clock */
 246     rtc_init(0x70, i8259[8], 1980);
 247     s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
 248     cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
 249
 250     /* Keyboard (i8042) */
 251     i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
 252
 253     /* Serial ports */
 254     if (serial_hds[0])
 255         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
 256     if (serial_hds[1])
 257         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
 258
 259     /* Parallel port */
 260     if (parallel_hds[0])
 261         parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
 262
 263     /* Sound card */
 264     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 265 #ifdef HAS_AUDIO
 266     audio_init(i8259);
 267 #endif
 268
 269     /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
 270     ds1225y_init(0x80009000, "nvram");
 271
 272     /* LED indicator */
 273     jazz_led_init(0x8000f000);
 274 }
 275
 276 static
 277 void mips_magnum_init (ram_addr_t ram_size,
 278                        const char *boot_device,
 279                        const char *kernel_filename, const char *kernel_cmdline,
 280                        const char *initrd_filename, const char *cpu_model)
 281 {
 282     mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
 283 }
 284
 285 static
 286 void mips_pica61_init (ram_addr_t ram_size,
 287                        const char *boot_device,
 288                        const char *kernel_filename, const char *kernel_cmdline,
 289                        const char *initrd_filename, const char *cpu_model)
 290 {
 291     mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
 292 }
 293
 294 QEMUMachine mips_magnum_machine = {
 295     .name = "magnum",
 296     .desc = "MIPS Magnum",
 297     .init = mips_magnum_init,
 298     .use_scsi = 1,
 299 };
 300
 301 QEMUMachine mips_pica61_machine = {
 302     .name = "pica61",
 303     .desc = "Acer Pica 61",
 304     .init = mips_pica61_init,
 305     .use_scsi = 1,
 306 };