hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31
  32 struct PCIBus {
  33     BusState qbus;
  34     int bus_num;
  35     int devfn_min;
  36     pci_set_irq_fn set_irq;
  37     pci_map_irq_fn map_irq;
  38     uint32_t config_reg; /* XXX: suppress */
  39     /* low level pic */
  40     SetIRQFunc *low_set_irq;
  41     qemu_irq *irq_opaque;
  42     PCIDevice *devices[256];
  43     PCIDevice *parent_dev;
  44     PCIBus *next;
  45     /* The bus IRQ state is the logical OR of the connected devices.
  46        Keep a count of the number of devices with raised IRQs.  */
  47     int nirq;
  48     int irq_count[];
  49 };
  50
  51 static void pci_update_mappings(PCIDevice *d);
  52 static void pci_set_irq(void *opaque, int irq_num, int level);
  53
  54 target_phys_addr_t pci_mem_base;
  55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  57 static int pci_irq_index;
  58 static PCIBus *first_bus;
  59
  60 static void pcibus_save(QEMUFile *f, void *opaque)
  61 {
  62     PCIBus *bus = (PCIBus *)opaque;
  63     int i;
  64
  65     qemu_put_be32(f, bus->nirq);
  66     for (i = 0; i < bus->nirq; i++)
  67         qemu_put_be32(f, bus->irq_count[i]);
  68 }
  69
  70 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  71 {
  72     PCIBus *bus = (PCIBus *)opaque;
  73     int i, nirq;
  74
  75     if (version_id != 1)
  76         return -EINVAL;
  77
  78     nirq = qemu_get_be32(f);
  79     if (bus->nirq != nirq) {
  80         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  81                 nirq, bus->nirq);
  82         return -EINVAL;
  83     }
  84
  85     for (i = 0; i < nirq; i++)
  86         bus->irq_count[i] = qemu_get_be32(f);
  87
  88     return 0;
  89 }
  90
  91 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
  92                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  93                          qemu_irq *pic, int devfn_min, int nirq)
  94 {
  95     PCIBus *bus;
  96     static int nbus = 0;
  97
  98     bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
  99                                         sizeof(PCIBus) + (nirq * sizeof(int)),
 100                                         parent, name));
 101     bus->set_irq = set_irq;
 102     bus->map_irq = map_irq;
 103     bus->irq_opaque = pic;
 104     bus->devfn_min = devfn_min;
 105     bus->nirq = nirq;
 106     bus->next = first_bus;
 107     first_bus = bus;
 108     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 109     return bus;
 110 }
 111
 112 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 113 {
 114     PCIBus *bus;
 115     bus = qemu_mallocz(sizeof(PCIBus));
 116     bus->map_irq = map_irq;
 117     bus->parent_dev = dev;
 118     bus->next = dev->bus->next;
 119     dev->bus->next = bus;
 120     return bus;
 121 }
 122
 123 int pci_bus_num(PCIBus *s)
 124 {
 125     return s->bus_num;
 126 }
 127
 128 void pci_device_save(PCIDevice *s, QEMUFile *f)
 129 {
 130     int i;
 131
 132     qemu_put_be32(f, 2); /* PCI device version */
 133     qemu_put_buffer(f, s->config, 256);
 134     for (i = 0; i < 4; i++)
 135         qemu_put_be32(f, s->irq_state[i]);
 136 }
 137
 138 int pci_device_load(PCIDevice *s, QEMUFile *f)
 139 {
 140     uint32_t version_id;
 141     int i;
 142
 143     version_id = qemu_get_be32(f);
 144     if (version_id > 2)
 145         return -EINVAL;
 146     qemu_get_buffer(f, s->config, 256);
 147     pci_update_mappings(s);
 148
 149     if (version_id >= 2)
 150         for (i = 0; i < 4; i ++)
 151             s->irq_state[i] = qemu_get_be32(f);
 152
 153     return 0;
 154 }
 155
 156 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 157 {
 158     uint16_t *id;
 159
 160     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 161     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 162     id[1] = cpu_to_le16(pci_default_sub_device_id);
 163     return 0;
 164 }
 165
 166 /*
 167  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 168  */
 169 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 170 {
 171     const char *p;
 172     char *e;
 173     unsigned long val;
 174     unsigned long dom = 0, bus = 0;
 175     unsigned slot = 0;
 176
 177     p = addr;
 178     val = strtoul(p, &e, 16);
 179     if (e == p)
 180         return -1;
 181     if (*e == ':') {
 182         bus = val;
 183         p = e + 1;
 184         val = strtoul(p, &e, 16);
 185         if (e == p)
 186             return -1;
 187         if (*e == ':') {
 188             dom = bus;
 189             bus = val;
 190             p = e + 1;
 191             val = strtoul(p, &e, 16);
 192             if (e == p)
 193                 return -1;
 194         }
 195     }
 196
 197     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 198         return -1;
 199
 200     slot = val;
 201
 202     if (*e)
 203         return -1;
 204
 205     /* Note: QEMU doesn't implement domains other than 0 */
 206     if (dom != 0 || pci_find_bus(bus) == NULL)
 207         return -1;
 208
 209     *domp = dom;
 210     *busp = bus;
 211     *slotp = slot;
 212     return 0;
 213 }
 214
 215 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 216 {
 217     char devaddr[32];
 218
 219     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 220         return -1;
 221
 222     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 223 }
 224
 225 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 226 {
 227     char devaddr[32];
 228
 229     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 230         return -1;
 231
 232     if (!strcmp(devaddr, "auto")) {
 233         *domp = *busp = 0;
 234         *slotp = -1;
 235         /* want to support dom/bus auto-assign at some point */
 236         return 0;
 237     }
 238
 239     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 240 }
 241
 242 /* -1 for devfn means auto assign */
 243 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 244                                          const char *name, int devfn,
 245                                          PCIConfigReadFunc *config_read,
 246                                          PCIConfigWriteFunc *config_write)
 247 {
 248     if (pci_irq_index >= PCI_DEVICES_MAX)
 249         return NULL;
 250
 251     if (devfn < 0) {
 252         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 253             if (!bus->devices[devfn])
 254                 goto found;
 255         }
 256         return NULL;
 257     found: ;
 258     }
 259     pci_dev->bus = bus;
 260     pci_dev->devfn = devfn;
 261     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 262     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 263     pci_set_default_subsystem_id(pci_dev);
 264
 265     if (!config_read)
 266         config_read = pci_default_read_config;
 267     if (!config_write)
 268         config_write = pci_default_write_config;
 269     pci_dev->config_read = config_read;
 270     pci_dev->config_write = config_write;
 271     pci_dev->irq_index = pci_irq_index++;
 272     bus->devices[devfn] = pci_dev;
 273     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 274     return pci_dev;
 275 }
 276
 277 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 278                                int instance_size, int devfn,
 279                                PCIConfigReadFunc *config_read,
 280                                PCIConfigWriteFunc *config_write)
 281 {
 282     PCIDevice *pci_dev;
 283
 284     pci_dev = qemu_mallocz(instance_size);
 285     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 286                                      config_read, config_write);
 287     return pci_dev;
 288 }
 289 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 290 {
 291     return addr + pci_mem_base;
 292 }
 293
 294 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 295 {
 296     PCIIORegion *r;
 297     int i;
 298
 299     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 300         r = &pci_dev->io_regions[i];
 301         if (!r->size || r->addr == -1)
 302             continue;
 303         if (r->type == PCI_ADDRESS_SPACE_IO) {
 304             isa_unassign_ioport(r->addr, r->size);
 305         } else {
 306             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 307                                                      r->size,
 308                                                      IO_MEM_UNASSIGNED);
 309         }
 310     }
 311 }
 312
 313 int pci_unregister_device(PCIDevice *pci_dev)
 314 {
 315     int ret = 0;
 316
 317     if (pci_dev->unregister)
 318         ret = pci_dev->unregister(pci_dev);
 319     if (ret)
 320         return ret;
 321
 322     pci_unregister_io_regions(pci_dev);
 323
 324     qemu_free_irqs(pci_dev->irq);
 325     pci_irq_index--;
 326     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 327     qdev_free(&pci_dev->qdev);
 328     return 0;
 329 }
 330
 331 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 332                             uint32_t size, int type,
 333                             PCIMapIORegionFunc *map_func)
 334 {
 335     PCIIORegion *r;
 336     uint32_t addr;
 337
 338     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 339         return;
 340
 341     if (size & (size-1)) {
 342         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 343                     "type=0x%x, size=0x%x\n", type, size);
 344         exit(1);
 345     }
 346
 347     r = &pci_dev->io_regions[region_num];
 348     r->addr = -1;
 349     r->size = size;
 350     r->type = type;
 351     r->map_func = map_func;
 352     if (region_num == PCI_ROM_SLOT) {
 353         addr = 0x30;
 354     } else {
 355         addr = 0x10 + region_num * 4;
 356     }
 357     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 358 }
 359
 360 static void pci_update_mappings(PCIDevice *d)
 361 {
 362     PCIIORegion *r;
 363     int cmd, i;
 364     uint32_t last_addr, new_addr, config_ofs;
 365
 366     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 367     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 368         r = &d->io_regions[i];
 369         if (i == PCI_ROM_SLOT) {
 370             config_ofs = 0x30;
 371         } else {
 372             config_ofs = 0x10 + i * 4;
 373         }
 374         if (r->size != 0) {
 375             if (r->type & PCI_ADDRESS_SPACE_IO) {
 376                 if (cmd & PCI_COMMAND_IO) {
 377                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 378                                                          config_ofs));
 379                     new_addr = new_addr & ~(r->size - 1);
 380                     last_addr = new_addr + r->size - 1;
 381                     /* NOTE: we have only 64K ioports on PC */
 382                     if (last_addr <= new_addr || new_addr == 0 ||
 383                         last_addr >= 0x10000) {
 384                         new_addr = -1;
 385                     }
 386                 } else {
 387                     new_addr = -1;
 388                 }
 389             } else {
 390                 if (cmd & PCI_COMMAND_MEMORY) {
 391                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 392                                                          config_ofs));
 393                     /* the ROM slot has a specific enable bit */
 394                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 395                         goto no_mem_map;
 396                     new_addr = new_addr & ~(r->size - 1);
 397                     last_addr = new_addr + r->size - 1;
 398                     /* NOTE: we do not support wrapping */
 399                     /* XXX: as we cannot support really dynamic
 400                        mappings, we handle specific values as invalid
 401                        mappings. */
 402                     if (last_addr <= new_addr || new_addr == 0 ||
 403                         last_addr == -1) {
 404                         new_addr = -1;
 405                     }
 406                 } else {
 407                 no_mem_map:
 408                     new_addr = -1;
 409                 }
 410             }
 411             /* now do the real mapping */
 412             if (new_addr != r->addr) {
 413                 if (r->addr != -1) {
 414                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 415                         int class;
 416                         /* NOTE: specific hack for IDE in PC case:
 417                            only one byte must be mapped. */
 418                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 419                         if (class == 0x0101 && r->size == 4) {
 420                             isa_unassign_ioport(r->addr + 2, 1);
 421                         } else {
 422                             isa_unassign_ioport(r->addr, r->size);
 423                         }
 424                     } else {
 425                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 426                                                      r->size,
 427                                                      IO_MEM_UNASSIGNED);
 428                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 429                     }
 430                 }
 431                 r->addr = new_addr;
 432                 if (r->addr != -1) {
 433                     r->map_func(d, i, r->addr, r->size, r->type);
 434                 }
 435             }
 436         }
 437     }
 438 }
 439
 440 uint32_t pci_default_read_config(PCIDevice *d,
 441                                  uint32_t address, int len)
 442 {
 443     uint32_t val;
 444
 445     switch(len) {
 446     default:
 447     case 4:
 448         if (address <= 0xfc) {
 449             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 450             break;
 451         }
 452         /* fall through */
 453     case 2:
 454         if (address <= 0xfe) {
 455             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 456             break;
 457         }
 458         /* fall through */
 459     case 1:
 460         val = d->config[address];
 461         break;
 462     }
 463     return val;
 464 }
 465
 466 void pci_default_write_config(PCIDevice *d,
 467                               uint32_t address, uint32_t val, int len)
 468 {
 469     int can_write, i;
 470     uint32_t end, addr;
 471
 472     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 473                      (address >= 0x30 && address < 0x34))) {
 474         PCIIORegion *r;
 475         int reg;
 476
 477         if ( address >= 0x30 ) {
 478             reg = PCI_ROM_SLOT;
 479         }else{
 480             reg = (address - 0x10) >> 2;
 481         }
 482         r = &d->io_regions[reg];
 483         if (r->size == 0)
 484             goto default_config;
 485         /* compute the stored value */
 486         if (reg == PCI_ROM_SLOT) {
 487             /* keep ROM enable bit */
 488             val &= (~(r->size - 1)) | 1;
 489         } else {
 490             val &= ~(r->size - 1);
 491             val |= r->type;
 492         }
 493         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 494         pci_update_mappings(d);
 495         return;
 496     }
 497  default_config:
 498     /* not efficient, but simple */
 499     addr = address;
 500     for(i = 0; i < len; i++) {
 501         /* default read/write accesses */
 502         switch(d->config[0x0e]) {
 503         case 0x00:
 504         case 0x80:
 505             switch(addr) {
 506             case 0x00:
 507             case 0x01:
 508             case 0x02:
 509             case 0x03:
 510             case 0x06:
 511             case 0x07:
 512             case 0x08:
 513             case 0x09:
 514             case 0x0a:
 515             case 0x0b:
 516             case 0x0e:
 517             case 0x10 ... 0x27: /* base */
 518             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 519             case 0x30 ... 0x33: /* rom */
 520             case 0x3d:
 521                 can_write = 0;
 522                 break;
 523             default:
 524                 can_write = 1;
 525                 break;
 526             }
 527             break;
 528         default:
 529         case 0x01:
 530             switch(addr) {
 531             case 0x00:
 532             case 0x01:
 533             case 0x02:
 534             case 0x03:
 535             case 0x06:
 536             case 0x07:
 537             case 0x08:
 538             case 0x09:
 539             case 0x0a:
 540             case 0x0b:
 541             case 0x0e:
 542             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 543             case 0x38 ... 0x3b: /* rom */
 544             case 0x3d:
 545                 can_write = 0;
 546                 break;
 547             default:
 548                 can_write = 1;
 549                 break;
 550             }
 551             break;
 552         }
 553         if (can_write) {
 554             /* Mask out writes to reserved bits in registers */
 555             switch (addr) {
 556             case 0x05:
 557                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 558                 break;
 559             case 0x06:
 560                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 561                 break;
 562             case 0x07:
 563                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 564                 break;
 565             }
 566             d->config[addr] = val;
 567         }
 568         if (++addr > 0xff)
 569                 break;
 570         val >>= 8;
 571     }
 572
 573     end = address + len;
 574     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 575         /* if the command register is modified, we must modify the mappings */
 576         pci_update_mappings(d);
 577     }
 578 }
 579
 580 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 581 {
 582     PCIBus *s = opaque;
 583     PCIDevice *pci_dev;
 584     int config_addr, bus_num;
 585
 586 #if defined(DEBUG_PCI) && 0
 587     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 588            addr, val, len);
 589 #endif
 590     bus_num = (addr >> 16) & 0xff;
 591     while (s && s->bus_num != bus_num)
 592         s = s->next;
 593     if (!s)
 594         return;
 595     pci_dev = s->devices[(addr >> 8) & 0xff];
 596     if (!pci_dev)
 597         return;
 598     config_addr = addr & 0xff;
 599 #if defined(DEBUG_PCI)
 600     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 601            pci_dev->name, config_addr, val, len);
 602 #endif
 603     pci_dev->config_write(pci_dev, config_addr, val, len);
 604 }
 605
 606 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 607 {
 608     PCIBus *s = opaque;
 609     PCIDevice *pci_dev;
 610     int config_addr, bus_num;
 611     uint32_t val;
 612
 613     bus_num = (addr >> 16) & 0xff;
 614     while (s && s->bus_num != bus_num)
 615         s= s->next;
 616     if (!s)
 617         goto fail;
 618     pci_dev = s->devices[(addr >> 8) & 0xff];
 619     if (!pci_dev) {
 620     fail:
 621         switch(len) {
 622         case 1:
 623             val = 0xff;
 624             break;
 625         case 2:
 626             val = 0xffff;
 627             break;
 628         default:
 629         case 4:
 630             val = 0xffffffff;
 631             break;
 632         }
 633         goto the_end;
 634     }
 635     config_addr = addr & 0xff;
 636     val = pci_dev->config_read(pci_dev, config_addr, len);
 637 #if defined(DEBUG_PCI)
 638     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 639            pci_dev->name, config_addr, val, len);
 640 #endif
 641  the_end:
 642 #if defined(DEBUG_PCI) && 0
 643     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 644            addr, val, len);
 645 #endif
 646     return val;
 647 }
 648
 649 /***********************************************************/
 650 /* generic PCI irq support */
 651
 652 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 653 static void pci_set_irq(void *opaque, int irq_num, int level)
 654 {
 655     PCIDevice *pci_dev = (PCIDevice *)opaque;
 656     PCIBus *bus;
 657     int change;
 658
 659     change = level - pci_dev->irq_state[irq_num];
 660     if (!change)
 661         return;
 662
 663     pci_dev->irq_state[irq_num] = level;
 664     for (;;) {
 665         bus = pci_dev->bus;
 666         irq_num = bus->map_irq(pci_dev, irq_num);
 667         if (bus->set_irq)
 668             break;
 669         pci_dev = bus->parent_dev;
 670     }
 671     bus->irq_count[irq_num] += change;
 672     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 673 }
 674
 675 /***********************************************************/
 676 /* monitor info on PCI */
 677
 678 typedef struct {
 679     uint16_t class;
 680     const char *desc;
 681 } pci_class_desc;
 682
 683 static const pci_class_desc pci_class_descriptions[] =
 684 {
 685     { 0x0100, "SCSI controller"},
 686     { 0x0101, "IDE controller"},
 687     { 0x0102, "Floppy controller"},
 688     { 0x0103, "IPI controller"},
 689     { 0x0104, "RAID controller"},
 690     { 0x0106, "SATA controller"},
 691     { 0x0107, "SAS controller"},
 692     { 0x0180, "Storage controller"},
 693     { 0x0200, "Ethernet controller"},
 694     { 0x0201, "Token Ring controller"},
 695     { 0x0202, "FDDI controller"},
 696     { 0x0203, "ATM controller"},
 697     { 0x0280, "Network controller"},
 698     { 0x0300, "VGA controller"},
 699     { 0x0301, "XGA controller"},
 700     { 0x0302, "3D controller"},
 701     { 0x0380, "Display controller"},
 702     { 0x0400, "Video controller"},
 703     { 0x0401, "Audio controller"},
 704     { 0x0402, "Phone"},
 705     { 0x0480, "Multimedia controller"},
 706     { 0x0500, "RAM controller"},
 707     { 0x0501, "Flash controller"},
 708     { 0x0580, "Memory controller"},
 709     { 0x0600, "Host bridge"},
 710     { 0x0601, "ISA bridge"},
 711     { 0x0602, "EISA bridge"},
 712     { 0x0603, "MC bridge"},
 713     { 0x0604, "PCI bridge"},
 714     { 0x0605, "PCMCIA bridge"},
 715     { 0x0606, "NUBUS bridge"},
 716     { 0x0607, "CARDBUS bridge"},
 717     { 0x0608, "RACEWAY bridge"},
 718     { 0x0680, "Bridge"},
 719     { 0x0c03, "USB controller"},
 720     { 0, NULL}
 721 };
 722
 723 static void pci_info_device(PCIDevice *d)
 724 {
 725     Monitor *mon = cur_mon;
 726     int i, class;
 727     PCIIORegion *r;
 728     const pci_class_desc *desc;
 729
 730     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 731                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 732     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 733     monitor_printf(mon, "    ");
 734     desc = pci_class_descriptions;
 735     while (desc->desc && class != desc->class)
 736         desc++;
 737     if (desc->desc) {
 738         monitor_printf(mon, "%s", desc->desc);
 739     } else {
 740         monitor_printf(mon, "Class %04x", class);
 741     }
 742     monitor_printf(mon, ": PCI device %04x:%04x\n",
 743            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 744            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 745
 746     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 747         monitor_printf(mon, "      IRQ %d.\n",
 748                        d->config[PCI_INTERRUPT_LINE]);
 749     }
 750     if (class == 0x0604) {
 751         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 752     }
 753     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 754         r = &d->io_regions[i];
 755         if (r->size != 0) {
 756             monitor_printf(mon, "      BAR%d: ", i);
 757             if (r->type & PCI_ADDRESS_SPACE_IO) {
 758                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 759                                r->addr, r->addr + r->size - 1);
 760             } else {
 761                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 762                                r->addr, r->addr + r->size - 1);
 763             }
 764         }
 765     }
 766     if (class == 0x0604 && d->config[0x19] != 0) {
 767         pci_for_each_device(d->config[0x19], pci_info_device);
 768     }
 769 }
 770
 771 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 772 {
 773     PCIBus *bus = first_bus;
 774     PCIDevice *d;
 775     int devfn;
 776
 777     while (bus && bus->bus_num != bus_num)
 778         bus = bus->next;
 779     if (bus) {
 780         for(devfn = 0; devfn < 256; devfn++) {
 781             d = bus->devices[devfn];
 782             if (d)
 783                 fn(d);
 784         }
 785     }
 786 }
 787
 788 void pci_info(Monitor *mon)
 789 {
 790     pci_for_each_device(0, pci_info_device);
 791 }
 792
 793 static const char * const pci_nic_models[] = {
 794     "ne2k_pci",
 795     "i82551",
 796     "i82557b",
 797     "i82559er",
 798     "rtl8139",
 799     "e1000",
 800     "pcnet",
 801     "virtio",
 802     NULL
 803 };
 804
 805 static const char * const pci_nic_names[] = {
 806     "ne2k_pci",
 807     "i82551",
 808     "i82557b",
 809     "i82559er",
 810     "rtl8139",
 811     "e1000",
 812     "pcnet",
 813     "virtio-net-pci",
 814     NULL
 815 };
 816
 817 /* Initialize a PCI NIC.  */
 818 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 819                   const char *default_model)
 820 {
 821     DeviceState *dev;
 822     int i;
 823
 824     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 825
 826     for (i = 0; pci_nic_models[i]; i++) {
 827         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 828             dev = qdev_create(&bus->qbus, pci_nic_names[i]);
 829             qdev_set_prop_int(dev, "devfn", devfn);
 830             qdev_set_netdev(dev, nd);
 831             qdev_init(dev);
 832             nd->private = dev;
 833             return (PCIDevice *)dev;
 834         }
 835     }
 836
 837     return NULL;
 838 }
 839
 840 typedef struct {
 841     PCIDevice dev;
 842     PCIBus *bus;
 843 } PCIBridge;
 844
 845 static void pci_bridge_write_config(PCIDevice *d,
 846                              uint32_t address, uint32_t val, int len)
 847 {
 848     PCIBridge *s = (PCIBridge *)d;
 849
 850     if (address == 0x19 || (address == 0x18 && len > 1)) {
 851         if (address == 0x19)
 852             s->bus->bus_num = val & 0xff;
 853         else
 854             s->bus->bus_num = (val >> 8) & 0xff;
 855 #if defined(DEBUG_PCI)
 856         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 857 #endif
 858     }
 859     pci_default_write_config(d, address, val, len);
 860 }
 861
 862 PCIBus *pci_find_bus(int bus_num)
 863 {
 864     PCIBus *bus = first_bus;
 865
 866     while (bus && bus->bus_num != bus_num)
 867         bus = bus->next;
 868
 869     return bus;
 870 }
 871
 872 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 873 {
 874     PCIBus *bus = pci_find_bus(bus_num);
 875
 876     if (!bus)
 877         return NULL;
 878
 879     return bus->devices[PCI_DEVFN(slot, function)];
 880 }
 881
 882 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 883                         pci_map_irq_fn map_irq, const char *name)
 884 {
 885     PCIBridge *s;
 886     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 887                                          devfn, NULL, pci_bridge_write_config);
 888
 889     pci_config_set_vendor_id(s->dev.config, vid);
 890     pci_config_set_device_id(s->dev.config, did);
 891
 892     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 893     s->dev.config[0x05] = 0x00;
 894     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 895     s->dev.config[0x07] = 0x00; // status = fast devsel
 896     s->dev.config[0x08] = 0x00; // revision
 897     s->dev.config[0x09] = 0x00; // programming i/f
 898     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 899     s->dev.config[0x0D] = 0x10; // latency_timer
 900     s->dev.config[PCI_HEADER_TYPE] =
 901         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 902     s->dev.config[0x1E] = 0xa0; // secondary status
 903
 904     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 905     return s->bus;
 906 }
 907
 908 typedef struct {
 909     DeviceInfo qdev;
 910     pci_qdev_initfn init;
 911 } PCIDeviceInfo;
 912
 913 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 914 {
 915     PCIDevice *pci_dev = (PCIDevice *)qdev;
 916     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 917     PCIBus *bus;
 918     int devfn;
 919
 920     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 921     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 922     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
 923                                      NULL, NULL);//FIXME:config_read, config_write);
 924     assert(pci_dev);
 925     info->init(pci_dev);
 926 }
 927
 928 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
 929 {
 930     PCIDeviceInfo *info;
 931
 932     info = qemu_mallocz(sizeof(*info));
 933     info->init = init;
 934     info->qdev.init = pci_qdev_init;
 935     info->qdev.bus_type = BUS_TYPE_PCI;
 936
 937     qdev_register(name, size, &info->qdev);
 938 }
 939
 940 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 941 {
 942     DeviceState *dev;
 943
 944     dev = qdev_create(&bus->qbus, name);
 945     qdev_set_prop_int(dev, "devfn", devfn);
 946     qdev_init(dev);
 947
 948     return (PCIDevice *)dev;
 949 }