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Factor out the VGA vram mapping updating routine
[qemu-kvm/fedora.git] / hw / sun4m.c
blob8b3c49ddb5e4115064885e1520a1708d617ec31b
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34
35 //#define DEBUG_IRQ
36
37 /*
38 * Sun4m architecture was used in the following machines:
39 *
40 * SPARCserver 6xxMP/xx
41 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
42 * SPARCstation LX/ZX (4/30)
43 * SPARCstation Voyager
44 * SPARCstation 10/xx, SPARCserver 10/xx
45 * SPARCstation 5, SPARCserver 5
46 * SPARCstation 20/xx, SPARCserver 20
47 * SPARCstation 4
48 *
49 * Sun4d architecture was used in the following machines:
50 *
51 * SPARCcenter 2000
52 * SPARCserver 1000
53 *
54 * Sun4c architecture was used in the following machines:
55 * SPARCstation 1/1+, SPARCserver 1/1+
56 * SPARCstation SLC
57 * SPARCstation IPC
58 * SPARCstation ELC
59 * SPARCstation IPX
60 *
61 * See for example: http://www.sunhelp.org/faq/sunref1.html
62 */
63
64 #ifdef DEBUG_IRQ
65 #define DPRINTF(fmt, args...) \
66 do { printf("CPUIRQ: " fmt , ##args); } while (0)
67 #else
68 #define DPRINTF(fmt, args...)
69 #endif
70
71 #define KERNEL_LOAD_ADDR 0x00004000
72 #define CMDLINE_ADDR 0x007ff000
73 #define INITRD_LOAD_ADDR 0x00800000
74 #define PROM_SIZE_MAX (512 * 1024)
75 #define PROM_VADDR 0xffd00000
76 #define PROM_FILENAME "openbios-sparc32"
77
78 #define MAX_CPUS 16
79 #define MAX_PILS 16
80
81 struct hwdef {
82 target_phys_addr_t iommu_base, slavio_base;
83 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
84 target_phys_addr_t serial_base, fd_base;
85 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
86 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
87 target_phys_addr_t ecc_base;
88 uint32_t ecc_version;
89 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
90 long vram_size, nvram_size;
91 // IRQ numbers are not PIL ones, but master interrupt controller
92 // register bit numbers
93 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
94 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
95 int machine_id; // For NVRAM
96 uint32_t iommu_version;
97 uint32_t intbit_to_level[32];
98 uint64_t max_mem;
99 const char * const default_cpu_model;
100 };
101
102 #define MAX_IOUNITS 5
103
104 struct sun4d_hwdef {
105 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
106 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
107 target_phys_addr_t serial_base;
108 target_phys_addr_t espdma_base, esp_base;
109 target_phys_addr_t ledma_base, le_base;
110 target_phys_addr_t tcx_base;
111 target_phys_addr_t sbi_base;
112 unsigned long vram_size, nvram_size;
113 // IRQ numbers are not PIL ones, but SBI register bit numbers
114 int esp_irq, le_irq, clock_irq, clock1_irq;
115 int ser_irq, ms_kb_irq, me_irq;
116 int machine_id; // For NVRAM
117 uint32_t iounit_version;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 };
121
122 /* TSC handling */
123
124 uint64_t cpu_get_tsc()
125 {
126 return qemu_get_clock(vm_clock);
127 }
128
129 int DMA_get_channel_mode (int nchan)
130 {
131 return 0;
132 }
133 int DMA_read_memory (int nchan, void *buf, int pos, int size)
134 {
135 return 0;
136 }
137 int DMA_write_memory (int nchan, void *buf, int pos, int size)
138 {
139 return 0;
140 }
141 void DMA_hold_DREQ (int nchan) {}
142 void DMA_release_DREQ (int nchan) {}
143 void DMA_schedule(int nchan) {}
144 void DMA_run (void) {}
145 void DMA_init (int high_page_enable) {}
146 void DMA_register_channel (int nchan,
147 DMA_transfer_handler transfer_handler,
148 void *opaque)
149 {
150 }
151
152 extern int nographic;
153
154 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
155 const char *boot_devices, uint32_t RAM_size,
156 uint32_t kernel_size,
157 int width, int height, int depth,
158 int machine_id, const char *arch)
159 {
160 unsigned int i;
161 uint32_t start, end;
162 uint8_t image[0x1ff0];
163 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
164 struct sparc_arch_cfg *sparc_header;
165 struct OpenBIOS_nvpart_v1 *part_header;
166
167 memset(image, '\0', sizeof(image));
168
169 // Try to match PPC NVRAM
170 strcpy(header->struct_ident, "QEMU_BIOS");
171 header->struct_version = cpu_to_be32(3); /* structure v3 */
172
173 header->nvram_size = cpu_to_be16(0x2000);
174 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
175 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
176 strcpy(header->arch, arch);
177 header->nb_cpus = smp_cpus & 0xff;
178 header->RAM0_base = 0;
179 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
180 strcpy(header->boot_devices, boot_devices);
181 header->nboot_devices = strlen(boot_devices) & 0xff;
182 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
183 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
184 if (cmdline) {
185 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
186 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
187 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
188 }
189 // XXX add initrd_image, initrd_size
190 header->width = cpu_to_be16(width);
191 header->height = cpu_to_be16(height);
192 header->depth = cpu_to_be16(depth);
193 if (nographic)
194 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
195
196 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
197
198 // Architecture specific header
199 start = sizeof(ohwcfg_v3_t);
200 sparc_header = (struct sparc_arch_cfg *)&image[start];
201 sparc_header->valid = 0;
202 start += sizeof(struct sparc_arch_cfg);
203
204 // OpenBIOS nvram variables
205 // Variable partition
206 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
207 part_header->signature = OPENBIOS_PART_SYSTEM;
208 strcpy(part_header->name, "system");
209
210 end = start + sizeof(struct OpenBIOS_nvpart_v1);
211 for (i = 0; i < nb_prom_envs; i++)
212 end = OpenBIOS_set_var(image, end, prom_envs[i]);
213
214 // End marker
215 image[end++] = '\0';
216
217 end = start + ((end - start + 15) & ~15);
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 // free partition
221 start = end;
222 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
223 part_header->signature = OPENBIOS_PART_FREE;
224 strcpy(part_header->name, "free");
225
226 end = 0x1fd0;
227 OpenBIOS_finish_partition(part_header, end - start);
228
229 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
230
231 for (i = 0; i < sizeof(image); i++)
232 m48t59_write(nvram, i, image[i]);
233 }
234
235 static void *slavio_intctl;
236
237 void pic_info()
238 {
239 if (slavio_intctl)
240 slavio_pic_info(slavio_intctl);
241 }
242
243 void irq_info()
244 {
245 if (slavio_intctl)
246 slavio_irq_info(slavio_intctl);
247 }
248
249 void cpu_check_irqs(CPUState *env)
250 {
251 if (env->pil_in && (env->interrupt_index == 0 ||
252 (env->interrupt_index & ~15) == TT_EXTINT)) {
253 unsigned int i;
254
255 for (i = 15; i > 0; i--) {
256 if (env->pil_in & (1 << i)) {
257 int old_interrupt = env->interrupt_index;
258
259 env->interrupt_index = TT_EXTINT | i;
260 if (old_interrupt != env->interrupt_index)
261 cpu_interrupt(env, CPU_INTERRUPT_HARD);
262 break;
263 }
264 }
265 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
266 env->interrupt_index = 0;
267 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
268 }
269 }
270
271 static void cpu_set_irq(void *opaque, int irq, int level)
272 {
273 CPUState *env = opaque;
274
275 if (level) {
276 DPRINTF("Raise CPU IRQ %d\n", irq);
277 env->halted = 0;
278 env->pil_in |= 1 << irq;
279 cpu_check_irqs(env);
280 } else {
281 DPRINTF("Lower CPU IRQ %d\n", irq);
282 env->pil_in &= ~(1 << irq);
283 cpu_check_irqs(env);
284 }
285 }
286
287 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
288 {
289 }
290
291 static void *slavio_misc;
292
293 void qemu_system_powerdown(void)
294 {
295 slavio_set_power_fail(slavio_misc, 1);
296 }
297
298 static void main_cpu_reset(void *opaque)
299 {
300 CPUState *env = opaque;
301
302 cpu_reset(env);
303 env->halted = 0;
304 }
305
306 static void secondary_cpu_reset(void *opaque)
307 {
308 CPUState *env = opaque;
309
310 cpu_reset(env);
311 env->halted = 1;
312 }
313
314 static unsigned long sun4m_load_kernel(const char *kernel_filename,
315 const char *kernel_cmdline,
316 const char *initrd_filename)
317 {
318 int linux_boot;
319 unsigned int i;
320 long initrd_size, kernel_size;
321
322 linux_boot = (kernel_filename != NULL);
323
324 kernel_size = 0;
325 if (linux_boot) {
326 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
327 NULL);
328 if (kernel_size < 0)
329 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
330 if (kernel_size < 0)
331 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
332 if (kernel_size < 0) {
333 fprintf(stderr, "qemu: could not load kernel '%s'\n",
334 kernel_filename);
335 exit(1);
336 }
337
338 /* load initrd */
339 initrd_size = 0;
340 if (initrd_filename) {
341 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
342 if (initrd_size < 0) {
343 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
344 initrd_filename);
345 exit(1);
346 }
347 }
348 if (initrd_size > 0) {
349 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
350 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
351 == 0x48647253) { // HdrS
352 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
353 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
354 break;
355 }
356 }
357 }
358 }
359 return kernel_size;
360 }
361
362 static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
363 const char *boot_device,
364 DisplayState *ds, const char *kernel_filename,
365 const char *kernel_cmdline,
366 const char *initrd_filename, const char *cpu_model)
367
368 {
369 CPUState *env, *envs[MAX_CPUS];
370 unsigned int i;
371 void *iommu, *espdma, *ledma, *main_esp, *nvram;
372 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
373 *espdma_irq, *ledma_irq;
374 qemu_irq *esp_reset, *le_reset;
375 unsigned long prom_offset, kernel_size;
376 int ret;
377 char buf[1024];
378 BlockDriverState *fd[MAX_FD];
379 int index;
380
381 /* init CPUs */
382 if (!cpu_model)
383 cpu_model = hwdef->default_cpu_model;
384
385 for(i = 0; i < smp_cpus; i++) {
386 env = cpu_init(cpu_model);
387 if (!env) {
388 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
389 exit(1);
390 }
391 cpu_sparc_set_id(env, i);
392 envs[i] = env;
393 if (i == 0) {
394 qemu_register_reset(main_cpu_reset, env);
395 } else {
396 qemu_register_reset(secondary_cpu_reset, env);
397 env->halted = 1;
398 }
399 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
400 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
401 env->prom_addr = hwdef->slavio_base;
402 }
403
404 for (i = smp_cpus; i < MAX_CPUS; i++)
405 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
406
407
408 /* allocate RAM */
409 if ((uint64_t)RAM_size > hwdef->max_mem) {
410 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
411 (unsigned int)RAM_size / (1024 * 1024),
412 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
413 exit(1);
414 }
415 cpu_register_physical_memory(0, RAM_size, 0);
416
417 /* load boot prom */
418 prom_offset = RAM_size + hwdef->vram_size;
419 cpu_register_physical_memory(hwdef->slavio_base,
420 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
421 TARGET_PAGE_MASK,
422 prom_offset | IO_MEM_ROM);
423
424 if (bios_name == NULL)
425 bios_name = PROM_FILENAME;
426 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
427 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
428 if (ret < 0 || ret > PROM_SIZE_MAX)
429 ret = load_image(buf, phys_ram_base + prom_offset);
430 if (ret < 0 || ret > PROM_SIZE_MAX) {
431 fprintf(stderr, "qemu: could not load prom '%s'\n",
432 buf);
433 exit(1);
434 }
435 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
436
437 /* set up devices */
438 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
439 hwdef->intctl_base + 0x10000ULL,
440 &hwdef->intbit_to_level[0],
441 &slavio_irq, &slavio_cpu_irq,
442 cpu_irqs,
443 hwdef->clock_irq);
444
445 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
446 stl_raw(phys_ram_base + prom_offset, 0xfe810103);
447
448 cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
449 prom_offset | IO_MEM_ROM);
450 }
451
452 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
453 slavio_irq[hwdef->me_irq]);
454
455 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
456 iommu, &espdma_irq, &esp_reset);
457
458 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
459 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
460 &le_reset);
461
462 if (graphic_depth != 8 && graphic_depth != 24) {
463 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
464 exit (1);
465 }
466 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
467 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
468
469 if (nd_table[0].model == NULL
470 || strcmp(nd_table[0].model, "lance") == 0) {
471 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
472 } else if (strcmp(nd_table[0].model, "?") == 0) {
473 fprintf(stderr, "qemu: Supported NICs: lance\n");
474 exit (1);
475 } else {
476 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
477 exit (1);
478 }
479
480 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
481 hwdef->nvram_size, 8);
482
483 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
484 slavio_cpu_irq, smp_cpus);
485
486 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
487 nographic);
488 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
489 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
490 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
491 serial_hds[1], serial_hds[0]);
492
493 if (hwdef->fd_base != (target_phys_addr_t)-1) {
494 /* there is zero or one floppy drive */
495 fd[1] = fd[0] = NULL;
496 index = drive_get_index(IF_FLOPPY, 0, 0);
497 if (index != -1)
498 fd[0] = drives_table[index].bdrv;
499
500 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
501 }
502
503 if (drive_get_max_bus(IF_SCSI) > 0) {
504 fprintf(stderr, "qemu: too many SCSI bus\n");
505 exit(1);
506 }
507
508 main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
509 esp_reset);
510
511 for (i = 0; i < ESP_MAX_DEVS; i++) {
512 index = drive_get_index(IF_SCSI, 0, i);
513 if (index == -1)
514 continue;
515 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
516 }
517
518 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
519 hwdef->aux1_base, hwdef->aux2_base,
520 slavio_irq[hwdef->me_irq], envs[0]);
521 if (hwdef->cs_base != (target_phys_addr_t)-1)
522 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
523
524 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
525 initrd_filename);
526
527 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
528 boot_device, RAM_size, kernel_size, graphic_width,
529 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
530
531 if (hwdef->ecc_base != (target_phys_addr_t)-1)
532 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
533 hwdef->ecc_version);
534 }
535
536 static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
537 const char *boot_device,
538 DisplayState *ds, const char *kernel_filename,
539 const char *kernel_cmdline,
540 const char *initrd_filename, const char *cpu_model)
541 {
542 CPUState *env;
543 unsigned int i;
544 void *iommu, *espdma, *ledma, *main_esp, *nvram;
545 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
546 qemu_irq *esp_reset, *le_reset;
547 unsigned long prom_offset, kernel_size;
548 int ret;
549 char buf[1024];
550 BlockDriverState *fd[MAX_FD];
551 int index;
552
553 /* init CPU */
554 if (!cpu_model)
555 cpu_model = hwdef->default_cpu_model;
556
557 env = cpu_init(cpu_model);
558 if (!env) {
559 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
560 exit(1);
561 }
562
563 cpu_sparc_set_id(env, 0);
564
565 qemu_register_reset(main_cpu_reset, env);
566 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
567 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
568 env->prom_addr = hwdef->slavio_base;
569
570 /* allocate RAM */
571 if ((uint64_t)RAM_size > hwdef->max_mem) {
572 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
573 (unsigned int)RAM_size / (1024 * 1024),
574 (unsigned int)hwdef->max_mem / (1024 * 1024));
575 exit(1);
576 }
577 cpu_register_physical_memory(0, RAM_size, 0);
578
579 /* load boot prom */
580 prom_offset = RAM_size + hwdef->vram_size;
581 cpu_register_physical_memory(hwdef->slavio_base,
582 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
583 TARGET_PAGE_MASK,
584 prom_offset | IO_MEM_ROM);
585
586 if (bios_name == NULL)
587 bios_name = PROM_FILENAME;
588 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
589 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
590 if (ret < 0 || ret > PROM_SIZE_MAX)
591 ret = load_image(buf, phys_ram_base + prom_offset);
592 if (ret < 0 || ret > PROM_SIZE_MAX) {
593 fprintf(stderr, "qemu: could not load prom '%s'\n",
594 buf);
595 exit(1);
596 }
597 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
598
599 /* set up devices */
600 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
601 &slavio_irq, cpu_irqs);
602
603 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
604 slavio_irq[hwdef->me_irq]);
605
606 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
607 iommu, &espdma_irq, &esp_reset);
608
609 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
610 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
611 &le_reset);
612
613 if (graphic_depth != 8 && graphic_depth != 24) {
614 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
615 exit (1);
616 }
617 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
618 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
619
620 if (nd_table[0].model == NULL
621 || strcmp(nd_table[0].model, "lance") == 0) {
622 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
623 } else if (strcmp(nd_table[0].model, "?") == 0) {
624 fprintf(stderr, "qemu: Supported NICs: lance\n");
625 exit (1);
626 } else {
627 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
628 exit (1);
629 }
630
631 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
632 hwdef->nvram_size, 2);
633
634 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
635 nographic);
636 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
637 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
638 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
639 serial_hds[1], serial_hds[0]);
640
641 if (hwdef->fd_base != (target_phys_addr_t)-1) {
642 /* there is zero or one floppy drive */
643 fd[1] = fd[0] = NULL;
644 index = drive_get_index(IF_FLOPPY, 0, 0);
645 if (index != -1)
646 fd[0] = drives_table[index].bdrv;
647
648 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
649 }
650
651 if (drive_get_max_bus(IF_SCSI) > 0) {
652 fprintf(stderr, "qemu: too many SCSI bus\n");
653 exit(1);
654 }
655
656 main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
657 esp_reset);
658
659 for (i = 0; i < ESP_MAX_DEVS; i++) {
660 index = drive_get_index(IF_SCSI, 0, i);
661 if (index == -1)
662 continue;
663 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
664 }
665
666 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
667 hwdef->aux1_base, hwdef->aux2_base,
668 slavio_irq[hwdef->me_irq], env);
669
670 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
671 initrd_filename);
672
673 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
674 boot_device, RAM_size, kernel_size, graphic_width,
675 graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
676 }
677
678 static const struct hwdef hwdefs[] = {
679 /* SS-5 */
680 {
681 .iommu_base = 0x10000000,
682 .tcx_base = 0x50000000,
683 .cs_base = 0x6c000000,
684 .slavio_base = 0x70000000,
685 .ms_kb_base = 0x71000000,
686 .serial_base = 0x71100000,
687 .nvram_base = 0x71200000,
688 .fd_base = 0x71400000,
689 .counter_base = 0x71d00000,
690 .intctl_base = 0x71e00000,
691 .idreg_base = 0x78000000,
692 .dma_base = 0x78400000,
693 .esp_base = 0x78800000,
694 .le_base = 0x78c00000,
695 .apc_base = 0x6a000000,
696 .aux1_base = 0x71900000,
697 .aux2_base = 0x71910000,
698 .ecc_base = -1,
699 .sun4c_intctl_base = -1,
700 .sun4c_counter_base = -1,
701 .vram_size = 0x00100000,
702 .nvram_size = 0x2000,
703 .esp_irq = 18,
704 .le_irq = 16,
705 .clock_irq = 7,
706 .clock1_irq = 19,
707 .ms_kb_irq = 14,
708 .ser_irq = 15,
709 .fd_irq = 22,
710 .me_irq = 30,
711 .cs_irq = 5,
712 .machine_id = 0x80,
713 .iommu_version = 0x05000000,
714 .intbit_to_level = {
715 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
716 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
717 },
718 .max_mem = 0x10000000,
719 .default_cpu_model = "Fujitsu MB86904",
720 },
721 /* SS-10 */
722 {
723 .iommu_base = 0xfe0000000ULL,
724 .tcx_base = 0xe20000000ULL,
725 .cs_base = -1,
726 .slavio_base = 0xff0000000ULL,
727 .ms_kb_base = 0xff1000000ULL,
728 .serial_base = 0xff1100000ULL,
729 .nvram_base = 0xff1200000ULL,
730 .fd_base = 0xff1700000ULL,
731 .counter_base = 0xff1300000ULL,
732 .intctl_base = 0xff1400000ULL,
733 .idreg_base = 0xef0000000ULL,
734 .dma_base = 0xef0400000ULL,
735 .esp_base = 0xef0800000ULL,
736 .le_base = 0xef0c00000ULL,
737 .apc_base = 0xefa000000ULL, // XXX should not exist
738 .aux1_base = 0xff1800000ULL,
739 .aux2_base = 0xff1a01000ULL,
740 .ecc_base = 0xf00000000ULL,
741 .ecc_version = 0x10000000, // version 0, implementation 1
742 .sun4c_intctl_base = -1,
743 .sun4c_counter_base = -1,
744 .vram_size = 0x00100000,
745 .nvram_size = 0x2000,
746 .esp_irq = 18,
747 .le_irq = 16,
748 .clock_irq = 7,
749 .clock1_irq = 19,
750 .ms_kb_irq = 14,
751 .ser_irq = 15,
752 .fd_irq = 22,
753 .me_irq = 30,
754 .cs_irq = -1,
755 .ecc_irq = 28,
756 .machine_id = 0x72,
757 .iommu_version = 0x03000000,
758 .intbit_to_level = {
759 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
760 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
761 },
762 .max_mem = 0xffffffff, // XXX actually first 62GB ok
763 .default_cpu_model = "TI SuperSparc II",
764 },
765 /* SS-600MP */
766 {
767 .iommu_base = 0xfe0000000ULL,
768 .tcx_base = 0xe20000000ULL,
769 .cs_base = -1,
770 .slavio_base = 0xff0000000ULL,
771 .ms_kb_base = 0xff1000000ULL,
772 .serial_base = 0xff1100000ULL,
773 .nvram_base = 0xff1200000ULL,
774 .fd_base = -1,
775 .counter_base = 0xff1300000ULL,
776 .intctl_base = 0xff1400000ULL,
777 .idreg_base = -1,
778 .dma_base = 0xef0081000ULL,
779 .esp_base = 0xef0080000ULL,
780 .le_base = 0xef0060000ULL,
781 .apc_base = 0xefa000000ULL, // XXX should not exist
782 .aux1_base = 0xff1800000ULL,
783 .aux2_base = 0xff1a01000ULL, // XXX should not exist
784 .ecc_base = 0xf00000000ULL,
785 .ecc_version = 0x00000000, // version 0, implementation 0
786 .sun4c_intctl_base = -1,
787 .sun4c_counter_base = -1,
788 .vram_size = 0x00100000,
789 .nvram_size = 0x2000,
790 .esp_irq = 18,
791 .le_irq = 16,
792 .clock_irq = 7,
793 .clock1_irq = 19,
794 .ms_kb_irq = 14,
795 .ser_irq = 15,
796 .fd_irq = 22,
797 .me_irq = 30,
798 .cs_irq = -1,
799 .ecc_irq = 28,
800 .machine_id = 0x71,
801 .iommu_version = 0x01000000,
802 .intbit_to_level = {
803 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
804 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
805 },
806 .max_mem = 0xffffffff, // XXX actually first 62GB ok
807 .default_cpu_model = "TI SuperSparc II",
808 },
809 /* SS-20 */
810 {
811 .iommu_base = 0xfe0000000ULL,
812 .tcx_base = 0xe20000000ULL,
813 .cs_base = -1,
814 .slavio_base = 0xff0000000ULL,
815 .ms_kb_base = 0xff1000000ULL,
816 .serial_base = 0xff1100000ULL,
817 .nvram_base = 0xff1200000ULL,
818 .fd_base = 0xff1700000ULL,
819 .counter_base = 0xff1300000ULL,
820 .intctl_base = 0xff1400000ULL,
821 .idreg_base = 0xef0000000ULL,
822 .dma_base = 0xef0400000ULL,
823 .esp_base = 0xef0800000ULL,
824 .le_base = 0xef0c00000ULL,
825 .apc_base = 0xefa000000ULL, // XXX should not exist
826 .aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
827 .aux2_base = 0xff1910000ULL, // XXX 0xff1a01000ULL,
828 .ecc_base = 0xf00000000ULL,
829 .ecc_version = 0x20000000, // version 0, implementation 2
830 .sun4c_intctl_base = -1,
831 .sun4c_counter_base = -1,
832 .vram_size = 0x00100000,
833 .nvram_size = 0x2000,
834 .esp_irq = 18,
835 .le_irq = 16,
836 .clock_irq = 7,
837 .clock1_irq = 19,
838 .ms_kb_irq = 14,
839 .ser_irq = 15,
840 .fd_irq = 22,
841 .me_irq = 30,
842 .cs_irq = -1,
843 .ecc_irq = 28,
844 .machine_id = 0x72,
845 .iommu_version = 0x13000000,
846 .intbit_to_level = {
847 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
848 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
849 },
850 .max_mem = 0xffffffff, // XXX actually first 62GB ok
851 .default_cpu_model = "TI SuperSparc II",
852 },
853 /* SS-2 */
854 {
855 .iommu_base = 0xf8000000,
856 .tcx_base = 0xfe000000,
857 .cs_base = -1,
858 .slavio_base = 0xf6000000,
859 .ms_kb_base = 0xf0000000,
860 .serial_base = 0xf1000000,
861 .nvram_base = 0xf2000000,
862 .fd_base = 0xf7200000,
863 .counter_base = -1,
864 .intctl_base = -1,
865 .dma_base = 0xf8400000,
866 .esp_base = 0xf8800000,
867 .le_base = 0xf8c00000,
868 .apc_base = -1,
869 .aux1_base = 0xf7400003,
870 .aux2_base = -1,
871 .sun4c_intctl_base = 0xf5000000,
872 .sun4c_counter_base = 0xf3000000,
873 .vram_size = 0x00100000,
874 .nvram_size = 0x800,
875 .esp_irq = 2,
876 .le_irq = 3,
877 .clock_irq = 5,
878 .clock1_irq = 7,
879 .ms_kb_irq = 1,
880 .ser_irq = 1,
881 .fd_irq = 1,
882 .me_irq = 1,
883 .cs_irq = -1,
884 .machine_id = 0x55,
885 .max_mem = 0x10000000,
886 .default_cpu_model = "Cypress CY7C601",
887 },
888 };
889
890 /* SPARCstation 5 hardware initialisation */
891 static void ss5_init(int RAM_size, int vga_ram_size,
892 const char *boot_device, DisplayState *ds,
893 const char *kernel_filename, const char *kernel_cmdline,
894 const char *initrd_filename, const char *cpu_model)
895 {
896 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
897 kernel_cmdline, initrd_filename, cpu_model);
898 }
899
900 /* SPARCstation 10 hardware initialisation */
901 static void ss10_init(int RAM_size, int vga_ram_size,
902 const char *boot_device, DisplayState *ds,
903 const char *kernel_filename, const char *kernel_cmdline,
904 const char *initrd_filename, const char *cpu_model)
905 {
906 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
907 kernel_cmdline, initrd_filename, cpu_model);
908 }
909
910 /* SPARCserver 600MP hardware initialisation */
911 static void ss600mp_init(int RAM_size, int vga_ram_size,
912 const char *boot_device, DisplayState *ds,
913 const char *kernel_filename, const char *kernel_cmdline,
914 const char *initrd_filename, const char *cpu_model)
915 {
916 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
917 kernel_cmdline, initrd_filename, cpu_model);
918 }
919
920 /* SPARCstation 20 hardware initialisation */
921 static void ss20_init(int RAM_size, int vga_ram_size,
922 const char *boot_device, DisplayState *ds,
923 const char *kernel_filename, const char *kernel_cmdline,
924 const char *initrd_filename, const char *cpu_model)
925 {
926 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
927 kernel_cmdline, initrd_filename, cpu_model);
928 }
929
930 /* SPARCstation 2 hardware initialisation */
931 static void ss2_init(int RAM_size, int vga_ram_size,
932 const char *boot_device, DisplayState *ds,
933 const char *kernel_filename, const char *kernel_cmdline,
934 const char *initrd_filename, const char *cpu_model)
935 {
936 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
937 kernel_cmdline, initrd_filename, cpu_model);
938 }
939
940 QEMUMachine ss5_machine = {
941 "SS-5",
942 "Sun4m platform, SPARCstation 5",
943 ss5_init,
944 };
945
946 QEMUMachine ss10_machine = {
947 "SS-10",
948 "Sun4m platform, SPARCstation 10",
949 ss10_init,
950 };
951
952 QEMUMachine ss600mp_machine = {
953 "SS-600MP",
954 "Sun4m platform, SPARCserver 600MP",
955 ss600mp_init,
956 };
957
958 QEMUMachine ss20_machine = {
959 "SS-20",
960 "Sun4m platform, SPARCstation 20",
961 ss20_init,
962 };
963
964 QEMUMachine ss2_machine = {
965 "SS-2",
966 "Sun4c platform, SPARCstation 2",
967 ss2_init,
968 };
969
970 static const struct sun4d_hwdef sun4d_hwdefs[] = {
971 /* SS-1000 */
972 {
973 .iounit_bases = {
974 0xfe0200000ULL,
975 0xfe1200000ULL,
976 0xfe2200000ULL,
977 0xfe3200000ULL,
978 -1,
979 },
980 .tcx_base = 0x820000000ULL,
981 .slavio_base = 0xf00000000ULL,
982 .ms_kb_base = 0xf00240000ULL,
983 .serial_base = 0xf00200000ULL,
984 .nvram_base = 0xf00280000ULL,
985 .counter_base = 0xf00300000ULL,
986 .espdma_base = 0x800081000ULL,
987 .esp_base = 0x800080000ULL,
988 .ledma_base = 0x800040000ULL,
989 .le_base = 0x800060000ULL,
990 .sbi_base = 0xf02800000ULL,
991 .vram_size = 0x00100000,
992 .nvram_size = 0x2000,
993 .esp_irq = 3,
994 .le_irq = 4,
995 .clock_irq = 14,
996 .clock1_irq = 10,
997 .ms_kb_irq = 12,
998 .ser_irq = 12,
999 .machine_id = 0x80,
1000 .iounit_version = 0x03000000,
1001 .max_mem = 0xffffffff, // XXX actually first 62GB ok
1002 .default_cpu_model = "TI SuperSparc II",
1003 },
1004 /* SS-2000 */
1005 {
1006 .iounit_bases = {
1007 0xfe0200000ULL,
1008 0xfe1200000ULL,
1009 0xfe2200000ULL,
1010 0xfe3200000ULL,
1011 0xfe4200000ULL,
1012 },
1013 .tcx_base = 0x820000000ULL,
1014 .slavio_base = 0xf00000000ULL,
1015 .ms_kb_base = 0xf00240000ULL,
1016 .serial_base = 0xf00200000ULL,
1017 .nvram_base = 0xf00280000ULL,
1018 .counter_base = 0xf00300000ULL,
1019 .espdma_base = 0x800081000ULL,
1020 .esp_base = 0x800080000ULL,
1021 .ledma_base = 0x800040000ULL,
1022 .le_base = 0x800060000ULL,
1023 .sbi_base = 0xf02800000ULL,
1024 .vram_size = 0x00100000,
1025 .nvram_size = 0x2000,
1026 .esp_irq = 3,
1027 .le_irq = 4,
1028 .clock_irq = 14,
1029 .clock1_irq = 10,
1030 .ms_kb_irq = 12,
1031 .ser_irq = 12,
1032 .machine_id = 0x80,
1033 .iounit_version = 0x03000000,
1034 .max_mem = 0xffffffff, // XXX actually first 62GB ok
1035 .default_cpu_model = "TI SuperSparc II",
1036 },
1037 };
1038
1039 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
1040 const char *boot_device,
1041 DisplayState *ds, const char *kernel_filename,
1042 const char *kernel_cmdline,
1043 const char *initrd_filename, const char *cpu_model)
1044 {
1045 CPUState *env, *envs[MAX_CPUS];
1046 unsigned int i;
1047 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1048 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1049 *espdma_irq, *ledma_irq;
1050 qemu_irq *esp_reset, *le_reset;
1051 unsigned long prom_offset, kernel_size;
1052 int ret;
1053 char buf[1024];
1054 int index;
1055
1056 /* init CPUs */
1057 if (!cpu_model)
1058 cpu_model = hwdef->default_cpu_model;
1059
1060 for (i = 0; i < smp_cpus; i++) {
1061 env = cpu_init(cpu_model);
1062 if (!env) {
1063 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1064 exit(1);
1065 }
1066 cpu_sparc_set_id(env, i);
1067 envs[i] = env;
1068 if (i == 0) {
1069 qemu_register_reset(main_cpu_reset, env);
1070 } else {
1071 qemu_register_reset(secondary_cpu_reset, env);
1072 env->halted = 1;
1073 }
1074 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
1075 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1076 env->prom_addr = hwdef->slavio_base;
1077 }
1078
1079 for (i = smp_cpus; i < MAX_CPUS; i++)
1080 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1081
1082 /* allocate RAM */
1083 if ((uint64_t)RAM_size > hwdef->max_mem) {
1084 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
1085 (unsigned int)RAM_size / (1024 * 1024),
1086 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1087 exit(1);
1088 }
1089 cpu_register_physical_memory(0, RAM_size, 0);
1090
1091 /* load boot prom */
1092 prom_offset = RAM_size + hwdef->vram_size;
1093 cpu_register_physical_memory(hwdef->slavio_base,
1094 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1095 TARGET_PAGE_MASK,
1096 prom_offset | IO_MEM_ROM);
1097
1098 if (bios_name == NULL)
1099 bios_name = PROM_FILENAME;
1100 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1101 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1102 if (ret < 0 || ret > PROM_SIZE_MAX)
1103 ret = load_image(buf, phys_ram_base + prom_offset);
1104 if (ret < 0 || ret > PROM_SIZE_MAX) {
1105 fprintf(stderr, "qemu: could not load prom '%s'\n",
1106 buf);
1107 exit(1);
1108 }
1109
1110 /* set up devices */
1111 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1112
1113 for (i = 0; i < MAX_IOUNITS; i++)
1114 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1115 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1116 hwdef->iounit_version,
1117 sbi_irq[hwdef->me_irq]);
1118
1119 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1120 iounits[0], &espdma_irq, &esp_reset);
1121
1122 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1123 iounits[0], &ledma_irq, &le_reset);
1124
1125 if (graphic_depth != 8 && graphic_depth != 24) {
1126 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1127 exit (1);
1128 }
1129 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1130 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1131
1132 if (nd_table[0].model == NULL
1133 || strcmp(nd_table[0].model, "lance") == 0) {
1134 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1135 } else if (strcmp(nd_table[0].model, "?") == 0) {
1136 fprintf(stderr, "qemu: Supported NICs: lance\n");
1137 exit (1);
1138 } else {
1139 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1140 exit (1);
1141 }
1142
1143 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1144 hwdef->nvram_size, 8);
1145
1146 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1147 sbi_cpu_irq, smp_cpus);
1148
1149 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1150 nographic);
1151 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1152 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1153 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1154 serial_hds[1], serial_hds[0]);
1155
1156 if (drive_get_max_bus(IF_SCSI) > 0) {
1157 fprintf(stderr, "qemu: too many SCSI bus\n");
1158 exit(1);
1159 }
1160
1161 main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
1162 esp_reset);
1163
1164 for (i = 0; i < ESP_MAX_DEVS; i++) {
1165 index = drive_get_index(IF_SCSI, 0, i);
1166 if (index == -1)
1167 continue;
1168 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
1169 }
1170
1171 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
1172 initrd_filename);
1173
1174 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1175 boot_device, RAM_size, kernel_size, graphic_width,
1176 graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1177 }
1178
1179 /* SPARCserver 1000 hardware initialisation */
1180 static void ss1000_init(int RAM_size, int vga_ram_size,
1181 const char *boot_device, DisplayState *ds,
1182 const char *kernel_filename, const char *kernel_cmdline,
1183 const char *initrd_filename, const char *cpu_model)
1184 {
1185 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1186 kernel_cmdline, initrd_filename, cpu_model);
1187 }
1188
1189 /* SPARCcenter 2000 hardware initialisation */
1190 static void ss2000_init(int RAM_size, int vga_ram_size,
1191 const char *boot_device, DisplayState *ds,
1192 const char *kernel_filename, const char *kernel_cmdline,
1193 const char *initrd_filename, const char *cpu_model)
1194 {
1195 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1196 kernel_cmdline, initrd_filename, cpu_model);
1197 }
1198
1199 QEMUMachine ss1000_machine = {
1200 "SS-1000",
1201 "Sun4d platform, SPARCserver 1000",
1202 ss1000_init,
1203 };
1204
1205 QEMUMachine ss2000_machine = {
1206 "SS-2000",
1207 "Sun4d platform, SPARCcenter 2000",
1208 ss2000_init,
1209 };
Patches shipped by Fedora