2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define MIPS_DEBUG_DISAS
34 //#define MIPS_DEBUG_SIGN_EXTENSIONS
35 //#define MIPS_SINGLE_STEP
37 #ifdef USE_DIRECT_JUMP
40 #define TBPARAM(x) (long)(x)
44 #define DEF(s, n, copy_size) INDEX_op_ ## s,
50 static uint16_t *gen_opc_ptr
;
51 static uint32_t *gen_opparam_ptr
;
55 /* MIPS major opcodes */
56 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
59 /* indirect opcode tables */
60 OPC_SPECIAL
= (0x00 << 26),
61 OPC_REGIMM
= (0x01 << 26),
62 OPC_CP0
= (0x10 << 26),
63 OPC_CP1
= (0x11 << 26),
64 OPC_CP2
= (0x12 << 26),
65 OPC_CP3
= (0x13 << 26),
66 OPC_SPECIAL2
= (0x1C << 26),
67 OPC_SPECIAL3
= (0x1F << 26),
68 /* arithmetic with immediate */
69 OPC_ADDI
= (0x08 << 26),
70 OPC_ADDIU
= (0x09 << 26),
71 OPC_SLTI
= (0x0A << 26),
72 OPC_SLTIU
= (0x0B << 26),
73 OPC_ANDI
= (0x0C << 26),
74 OPC_ORI
= (0x0D << 26),
75 OPC_XORI
= (0x0E << 26),
76 OPC_LUI
= (0x0F << 26),
77 OPC_DADDI
= (0x18 << 26),
78 OPC_DADDIU
= (0x19 << 26),
79 /* Jump and branches */
81 OPC_JAL
= (0x03 << 26),
82 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
83 OPC_BEQL
= (0x14 << 26),
84 OPC_BNE
= (0x05 << 26),
85 OPC_BNEL
= (0x15 << 26),
86 OPC_BLEZ
= (0x06 << 26),
87 OPC_BLEZL
= (0x16 << 26),
88 OPC_BGTZ
= (0x07 << 26),
89 OPC_BGTZL
= (0x17 << 26),
90 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
92 OPC_LDL
= (0x1A << 26),
93 OPC_LDR
= (0x1B << 26),
94 OPC_LB
= (0x20 << 26),
95 OPC_LH
= (0x21 << 26),
96 OPC_LWL
= (0x22 << 26),
97 OPC_LW
= (0x23 << 26),
98 OPC_LBU
= (0x24 << 26),
99 OPC_LHU
= (0x25 << 26),
100 OPC_LWR
= (0x26 << 26),
101 OPC_LWU
= (0x27 << 26),
102 OPC_SB
= (0x28 << 26),
103 OPC_SH
= (0x29 << 26),
104 OPC_SWL
= (0x2A << 26),
105 OPC_SW
= (0x2B << 26),
106 OPC_SDL
= (0x2C << 26),
107 OPC_SDR
= (0x2D << 26),
108 OPC_SWR
= (0x2E << 26),
109 OPC_LL
= (0x30 << 26),
110 OPC_LLD
= (0x34 << 26),
111 OPC_LD
= (0x37 << 26),
112 OPC_SC
= (0x38 << 26),
113 OPC_SCD
= (0x3C << 26),
114 OPC_SD
= (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1
= (0x31 << 26),
117 OPC_LWC2
= (0x32 << 26),
118 OPC_LDC1
= (0x35 << 26),
119 OPC_LDC2
= (0x36 << 26),
120 OPC_SWC1
= (0x39 << 26),
121 OPC_SWC2
= (0x3A << 26),
122 OPC_SDC1
= (0x3D << 26),
123 OPC_SDC2
= (0x3E << 26),
124 /* MDMX ASE specific */
125 OPC_MDMX
= (0x1E << 26),
126 /* Cache and prefetch */
127 OPC_CACHE
= (0x2F << 26),
128 OPC_PREF
= (0x33 << 26),
129 /* Reserved major opcode */
130 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
133 /* MIPS special opcodes */
134 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
138 OPC_SLL
= 0x00 | OPC_SPECIAL
,
139 /* NOP is SLL r0, r0, 0 */
140 /* SSNOP is SLL r0, r0, 1 */
141 /* EHB is SLL r0, r0, 3 */
142 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
143 OPC_SRA
= 0x03 | OPC_SPECIAL
,
144 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
145 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
146 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
147 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
148 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
149 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
150 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
151 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
152 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
153 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
154 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
155 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
156 /* Multiplication / division */
157 OPC_MULT
= 0x18 | OPC_SPECIAL
,
158 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
159 OPC_DIV
= 0x1A | OPC_SPECIAL
,
160 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
161 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
162 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
163 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
164 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
165 /* 2 registers arithmetic / logic */
166 OPC_ADD
= 0x20 | OPC_SPECIAL
,
167 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
168 OPC_SUB
= 0x22 | OPC_SPECIAL
,
169 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
170 OPC_AND
= 0x24 | OPC_SPECIAL
,
171 OPC_OR
= 0x25 | OPC_SPECIAL
,
172 OPC_XOR
= 0x26 | OPC_SPECIAL
,
173 OPC_NOR
= 0x27 | OPC_SPECIAL
,
174 OPC_SLT
= 0x2A | OPC_SPECIAL
,
175 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
176 OPC_DADD
= 0x2C | OPC_SPECIAL
,
177 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
178 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
179 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
181 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
182 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* Multiplication variants of the vr54xx. */
218 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
221 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
222 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
223 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
224 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
225 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
226 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
227 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
228 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
229 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
230 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
231 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
232 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
233 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
234 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
237 /* REGIMM (rt field) opcodes */
238 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
241 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
242 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
243 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
244 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
245 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
246 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
247 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
248 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
249 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
250 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
251 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
252 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
253 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
254 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
255 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
258 /* Special2 opcodes */
259 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
262 /* Multiply & xxx operations */
263 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
264 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
265 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
266 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
267 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
269 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
270 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
271 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
272 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
274 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
277 /* Special3 opcodes */
278 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
281 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
282 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
283 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
284 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
285 OPC_INS
= 0x04 | OPC_SPECIAL3
,
286 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
287 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
288 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
289 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
290 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
291 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
292 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
293 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
297 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
300 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
301 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
302 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
306 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
309 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
310 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
313 /* Coprocessor 0 (rs field) */
314 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
317 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
318 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
319 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
320 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
321 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
322 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
323 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
324 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
325 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
326 OPC_C0
= (0x10 << 21) | OPC_CP0
,
327 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
328 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
332 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
335 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
336 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
337 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
338 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
339 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
340 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
343 /* Coprocessor 0 (with rs == C0) */
344 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
347 OPC_TLBR
= 0x01 | OPC_C0
,
348 OPC_TLBWI
= 0x02 | OPC_C0
,
349 OPC_TLBWR
= 0x06 | OPC_C0
,
350 OPC_TLBP
= 0x08 | OPC_C0
,
351 OPC_RFE
= 0x10 | OPC_C0
,
352 OPC_ERET
= 0x18 | OPC_C0
,
353 OPC_DERET
= 0x1F | OPC_C0
,
354 OPC_WAIT
= 0x20 | OPC_C0
,
357 /* Coprocessor 1 (rs field) */
358 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
361 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
362 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
363 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
364 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
365 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
366 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
367 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
368 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
369 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
370 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
371 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
372 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
373 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
374 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
375 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
376 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
377 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
378 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
381 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
382 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
385 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
386 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
387 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
388 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
392 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
393 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
397 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
398 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
401 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
404 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
405 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
406 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
407 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
408 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
409 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
410 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
411 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
412 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
415 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
418 OPC_LWXC1
= 0x00 | OPC_CP3
,
419 OPC_LDXC1
= 0x01 | OPC_CP3
,
420 OPC_LUXC1
= 0x05 | OPC_CP3
,
421 OPC_SWXC1
= 0x08 | OPC_CP3
,
422 OPC_SDXC1
= 0x09 | OPC_CP3
,
423 OPC_SUXC1
= 0x0D | OPC_CP3
,
424 OPC_PREFX
= 0x0F | OPC_CP3
,
425 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
426 OPC_MADD_S
= 0x20 | OPC_CP3
,
427 OPC_MADD_D
= 0x21 | OPC_CP3
,
428 OPC_MADD_PS
= 0x26 | OPC_CP3
,
429 OPC_MSUB_S
= 0x28 | OPC_CP3
,
430 OPC_MSUB_D
= 0x29 | OPC_CP3
,
431 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
432 OPC_NMADD_S
= 0x30 | OPC_CP3
,
433 OPC_NMADD_D
= 0x31 | OPC_CP3
,
434 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
435 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
436 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
437 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
441 const unsigned char *regnames
[] =
442 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
443 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
444 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
445 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
447 /* Warning: no function for r0 register (hard wired to zero) */
448 #define GEN32(func, NAME) \
449 static GenOpFunc *NAME ## _table [32] = { \
450 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
451 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
452 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
453 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
454 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
455 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
456 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
457 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
459 static always_inline void func(int n) \
461 NAME ## _table[n](); \
464 /* General purpose registers moves */
465 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
466 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
467 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
469 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
470 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
472 /* Moves to/from shadow registers */
473 GEN32(gen_op_load_srsgpr_T0
, gen_op_load_srsgpr_T0_gpr
);
474 GEN32(gen_op_store_T0_srsgpr
, gen_op_store_T0_srsgpr_gpr
);
476 static const char *fregnames
[] =
477 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
478 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
479 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
480 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
482 #define FGEN32(func, NAME) \
483 static GenOpFunc *NAME ## _table [32] = { \
484 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
485 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
486 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
487 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
488 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
489 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
490 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
491 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
493 static always_inline void func(int n) \
495 NAME ## _table[n](); \
498 FGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
499 FGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
501 FGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
502 FGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
504 FGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
505 FGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
507 FGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
508 FGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
510 FGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
511 FGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
513 FGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
514 FGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
516 FGEN32(gen_op_load_fpr_WTH0
, gen_op_load_fpr_WTH0_fpr
);
517 FGEN32(gen_op_store_fpr_WTH0
, gen_op_store_fpr_WTH0_fpr
);
519 FGEN32(gen_op_load_fpr_WTH1
, gen_op_load_fpr_WTH1_fpr
);
520 FGEN32(gen_op_store_fpr_WTH1
, gen_op_store_fpr_WTH1_fpr
);
522 FGEN32(gen_op_load_fpr_WTH2
, gen_op_load_fpr_WTH2_fpr
);
523 FGEN32(gen_op_store_fpr_WTH2
, gen_op_store_fpr_WTH2_fpr
);
525 #define FOP_CONDS(type, fmt) \
526 static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
527 gen_op_cmp ## type ## _ ## fmt ## _f, \
528 gen_op_cmp ## type ## _ ## fmt ## _un, \
529 gen_op_cmp ## type ## _ ## fmt ## _eq, \
530 gen_op_cmp ## type ## _ ## fmt ## _ueq, \
531 gen_op_cmp ## type ## _ ## fmt ## _olt, \
532 gen_op_cmp ## type ## _ ## fmt ## _ult, \
533 gen_op_cmp ## type ## _ ## fmt ## _ole, \
534 gen_op_cmp ## type ## _ ## fmt ## _ule, \
535 gen_op_cmp ## type ## _ ## fmt ## _sf, \
536 gen_op_cmp ## type ## _ ## fmt ## _ngle, \
537 gen_op_cmp ## type ## _ ## fmt ## _seq, \
538 gen_op_cmp ## type ## _ ## fmt ## _ngl, \
539 gen_op_cmp ## type ## _ ## fmt ## _lt, \
540 gen_op_cmp ## type ## _ ## fmt ## _nge, \
541 gen_op_cmp ## type ## _ ## fmt ## _le, \
542 gen_op_cmp ## type ## _ ## fmt ## _ngt, \
544 static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
546 gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
556 typedef struct DisasContext
{
557 struct TranslationBlock
*tb
;
558 target_ulong pc
, saved_pc
;
561 /* Routine used to access memory */
563 uint32_t hflags
, saved_hflags
;
565 target_ulong btarget
;
571 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
572 * exception condition
574 BS_STOP
= 1, /* We want to stop translation for any reason */
575 BS_BRANCH
= 2, /* We reached a branch condition */
576 BS_EXCP
= 3, /* We reached an exception condition */
579 #ifdef MIPS_DEBUG_DISAS
580 #define MIPS_DEBUG(fmt, args...) \
582 if (loglevel & CPU_LOG_TB_IN_ASM) { \
583 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
584 ctx->pc, ctx->opcode , ##args); \
588 #define MIPS_DEBUG(fmt, args...) do { } while(0)
591 #define MIPS_INVAL(op) \
593 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
594 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
597 #define GEN_LOAD_REG_T0(Rn) \
602 if (ctx->glue(last_T0, _store) != gen_opc_ptr \
603 || ctx->glue(last_T0, _gpr) != Rn) { \
604 gen_op_load_gpr_T0(Rn); \
609 #define GEN_LOAD_REG_T1(Rn) \
614 gen_op_load_gpr_T1(Rn); \
618 #define GEN_LOAD_REG_T2(Rn) \
623 gen_op_load_gpr_T2(Rn); \
627 #define GEN_LOAD_SRSREG_TN(Tn, Rn) \
630 glue(gen_op_reset_, Tn)(); \
632 glue(gen_op_load_srsgpr_, Tn)(Rn); \
636 #if defined(TARGET_MIPS64)
637 #define GEN_LOAD_IMM_TN(Tn, Imm) \
640 glue(gen_op_reset_, Tn)(); \
641 } else if ((int32_t)Imm == Imm) { \
642 glue(gen_op_set_, Tn)(Imm); \
644 glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
648 #define GEN_LOAD_IMM_TN(Tn, Imm) \
651 glue(gen_op_reset_, Tn)(); \
653 glue(gen_op_set_, Tn)(Imm); \
658 #define GEN_STORE_T0_REG(Rn) \
661 glue(gen_op_store_T0,_gpr)(Rn); \
662 ctx->glue(last_T0,_store) = gen_opc_ptr; \
663 ctx->glue(last_T0,_gpr) = Rn; \
667 #define GEN_STORE_T1_REG(Rn) \
670 glue(gen_op_store_T1,_gpr)(Rn); \
673 #define GEN_STORE_TN_SRSREG(Rn, Tn) \
676 glue(glue(gen_op_store_, Tn),_srsgpr)(Rn); \
680 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
682 glue(gen_op_load_fpr_, FTn)(Fn); \
685 #define GEN_STORE_FTN_FREG(Fn, FTn) \
687 glue(gen_op_store_fpr_, FTn)(Fn); \
690 static always_inline
void gen_save_pc(target_ulong pc
)
692 #if defined(TARGET_MIPS64)
693 if (pc
== (int32_t)pc
) {
696 gen_op_save_pc64(pc
>> 32, (uint32_t)pc
);
703 static always_inline
void gen_save_btarget(target_ulong btarget
)
705 #if defined(TARGET_MIPS64)
706 if (btarget
== (int32_t)btarget
) {
707 gen_op_save_btarget(btarget
);
709 gen_op_save_btarget64(btarget
>> 32, (uint32_t)btarget
);
712 gen_op_save_btarget(btarget
);
716 static always_inline
void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
718 #if defined MIPS_DEBUG_DISAS
719 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
720 fprintf(logfile
, "hflags %08x saved %08x\n",
721 ctx
->hflags
, ctx
->saved_hflags
);
724 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
725 gen_save_pc(ctx
->pc
);
726 ctx
->saved_pc
= ctx
->pc
;
728 if (ctx
->hflags
!= ctx
->saved_hflags
) {
729 gen_op_save_state(ctx
->hflags
);
730 ctx
->saved_hflags
= ctx
->hflags
;
731 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
733 gen_op_save_breg_target();
739 /* bcond was already saved by the BL insn */
742 gen_save_btarget(ctx
->btarget
);
748 static always_inline
void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
750 ctx
->saved_hflags
= ctx
->hflags
;
751 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
753 gen_op_restore_breg_target();
756 ctx
->btarget
= env
->btarget
;
760 ctx
->btarget
= env
->btarget
;
761 gen_op_restore_bcond();
766 static always_inline
void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
768 #if defined MIPS_DEBUG_DISAS
769 if (loglevel
& CPU_LOG_TB_IN_ASM
)
770 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
772 save_cpu_state(ctx
, 1);
774 gen_op_raise_exception(excp
);
776 gen_op_raise_exception_err(excp
, err
);
777 ctx
->bstate
= BS_EXCP
;
780 static always_inline
void generate_exception (DisasContext
*ctx
, int excp
)
782 generate_exception_err (ctx
, excp
, 0);
785 static always_inline
void check_cp0_enabled(DisasContext
*ctx
)
787 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
788 generate_exception_err(ctx
, EXCP_CpU
, 1);
791 static always_inline
void check_cp1_enabled(DisasContext
*ctx
)
793 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
794 generate_exception_err(ctx
, EXCP_CpU
, 1);
797 /* Verify that the processor is running with COP1X instructions enabled.
798 This is associated with the nabla symbol in the MIPS32 and MIPS64
801 static always_inline
void check_cop1x(DisasContext
*ctx
)
803 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
804 generate_exception(ctx
, EXCP_RI
);
807 /* Verify that the processor is running with 64-bit floating-point
808 operations enabled. */
810 static always_inline
void check_cp1_64bitmode(DisasContext
*ctx
)
812 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
813 generate_exception(ctx
, EXCP_RI
);
817 * Verify if floating point register is valid; an operation is not defined
818 * if bit 0 of any register specification is set and the FR bit in the
819 * Status register equals zero, since the register numbers specify an
820 * even-odd pair of adjacent coprocessor general registers. When the FR bit
821 * in the Status register equals one, both even and odd register numbers
822 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
824 * Multiple 64 bit wide registers can be checked by calling
825 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
827 void check_cp1_registers(DisasContext
*ctx
, int regs
)
829 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
830 generate_exception(ctx
, EXCP_RI
);
833 /* This code generates a "reserved instruction" exception if the
834 CPU does not support the instruction set corresponding to flags. */
835 static always_inline
void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
837 if (unlikely(!(env
->insn_flags
& flags
)))
838 generate_exception(ctx
, EXCP_RI
);
841 /* This code generates a "reserved instruction" exception if 64-bit
842 instructions are not enabled. */
843 static always_inline
void check_mips_64(DisasContext
*ctx
)
845 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
846 generate_exception(ctx
, EXCP_RI
);
849 #if defined(CONFIG_USER_ONLY)
850 #define op_ldst(name) gen_op_##name##_raw()
851 #define OP_LD_TABLE(width)
852 #define OP_ST_TABLE(width)
854 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
855 #define OP_LD_TABLE(width) \
856 static GenOpFunc *gen_op_l##width[] = { \
857 &gen_op_l##width##_kernel, \
858 &gen_op_l##width##_super, \
859 &gen_op_l##width##_user, \
861 #define OP_ST_TABLE(width) \
862 static GenOpFunc *gen_op_s##width[] = { \
863 &gen_op_s##width##_kernel, \
864 &gen_op_s##width##_super, \
865 &gen_op_s##width##_user, \
869 #if defined(TARGET_MIPS64)
902 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
903 int base
, int16_t offset
)
905 const char *opn
= "ldst";
908 GEN_LOAD_IMM_TN(T0
, offset
);
909 } else if (offset
== 0) {
910 gen_op_load_gpr_T0(base
);
912 gen_op_load_gpr_T0(base
);
913 gen_op_set_T1(offset
);
916 /* Don't do NOP if destination is zero: we must perform the actual
919 #if defined(TARGET_MIPS64)
922 GEN_STORE_T0_REG(rt
);
927 GEN_STORE_T0_REG(rt
);
932 GEN_STORE_T0_REG(rt
);
941 save_cpu_state(ctx
, 1);
944 GEN_STORE_T0_REG(rt
);
950 GEN_STORE_T1_REG(rt
);
961 GEN_STORE_T1_REG(rt
);
972 GEN_STORE_T0_REG(rt
);
982 GEN_STORE_T0_REG(rt
);
992 GEN_STORE_T0_REG(rt
);
997 GEN_STORE_T0_REG(rt
);
1001 GEN_LOAD_REG_T1(rt
);
1007 GEN_STORE_T0_REG(rt
);
1011 GEN_LOAD_REG_T1(rt
);
1013 GEN_STORE_T1_REG(rt
);
1017 GEN_LOAD_REG_T1(rt
);
1022 GEN_LOAD_REG_T1(rt
);
1024 GEN_STORE_T1_REG(rt
);
1028 GEN_LOAD_REG_T1(rt
);
1034 GEN_STORE_T0_REG(rt
);
1038 save_cpu_state(ctx
, 1);
1039 GEN_LOAD_REG_T1(rt
);
1041 GEN_STORE_T0_REG(rt
);
1046 generate_exception(ctx
, EXCP_RI
);
1049 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1052 /* Load and store */
1053 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1054 int base
, int16_t offset
)
1056 const char *opn
= "flt_ldst";
1059 GEN_LOAD_IMM_TN(T0
, offset
);
1060 } else if (offset
== 0) {
1061 gen_op_load_gpr_T0(base
);
1063 gen_op_load_gpr_T0(base
);
1064 gen_op_set_T1(offset
);
1067 /* Don't do NOP if destination is zero: we must perform the actual
1072 GEN_STORE_FTN_FREG(ft
, WT0
);
1076 GEN_LOAD_FREG_FTN(WT0
, ft
);
1082 GEN_STORE_FTN_FREG(ft
, DT0
);
1086 GEN_LOAD_FREG_FTN(DT0
, ft
);
1092 generate_exception(ctx
, EXCP_RI
);
1095 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1098 /* Arithmetic with immediate operand */
1099 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1100 int rt
, int rs
, int16_t imm
)
1103 const char *opn
= "imm arith";
1105 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1106 /* If no destination, treat it as a NOP.
1107 For addi, we must generate the overflow exception when needed. */
1111 uimm
= (uint16_t)imm
;
1115 #if defined(TARGET_MIPS64)
1121 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1126 GEN_LOAD_REG_T0(rs
);
1127 GEN_LOAD_IMM_TN(T1
, uimm
);
1130 GEN_LOAD_IMM_TN(T0
, imm
<< 16);
1135 #if defined(TARGET_MIPS64)
1144 GEN_LOAD_REG_T0(rs
);
1145 GEN_LOAD_IMM_TN(T1
, uimm
);
1150 save_cpu_state(ctx
, 1);
1158 #if defined(TARGET_MIPS64)
1160 save_cpu_state(ctx
, 1);
1201 switch ((ctx
->opcode
>> 21) & 0x1f) {
1207 /* rotr is decoded as srl on non-R2 CPUs */
1208 if (env
->insn_flags
& ISA_MIPS32R2
) {
1217 MIPS_INVAL("invalid srl flag");
1218 generate_exception(ctx
, EXCP_RI
);
1222 #if defined(TARGET_MIPS64)
1232 switch ((ctx
->opcode
>> 21) & 0x1f) {
1238 /* drotr is decoded as dsrl on non-R2 CPUs */
1239 if (env
->insn_flags
& ISA_MIPS32R2
) {
1248 MIPS_INVAL("invalid dsrl flag");
1249 generate_exception(ctx
, EXCP_RI
);
1262 switch ((ctx
->opcode
>> 21) & 0x1f) {
1268 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1269 if (env
->insn_flags
& ISA_MIPS32R2
) {
1278 MIPS_INVAL("invalid dsrl32 flag");
1279 generate_exception(ctx
, EXCP_RI
);
1286 generate_exception(ctx
, EXCP_RI
);
1289 GEN_STORE_T0_REG(rt
);
1290 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1294 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1295 int rd
, int rs
, int rt
)
1297 const char *opn
= "arith";
1299 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1300 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1301 /* If no destination, treat it as a NOP.
1302 For add & sub, we must generate the overflow exception when needed. */
1306 GEN_LOAD_REG_T0(rs
);
1307 /* Specialcase the conventional move operation. */
1308 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1309 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1310 GEN_STORE_T0_REG(rd
);
1313 GEN_LOAD_REG_T1(rt
);
1316 save_cpu_state(ctx
, 1);
1325 save_cpu_state(ctx
, 1);
1333 #if defined(TARGET_MIPS64)
1335 save_cpu_state(ctx
, 1);
1344 save_cpu_state(ctx
, 1);
1398 switch ((ctx
->opcode
>> 6) & 0x1f) {
1404 /* rotrv is decoded as srlv on non-R2 CPUs */
1405 if (env
->insn_flags
& ISA_MIPS32R2
) {
1414 MIPS_INVAL("invalid srlv flag");
1415 generate_exception(ctx
, EXCP_RI
);
1419 #if defined(TARGET_MIPS64)
1429 switch ((ctx
->opcode
>> 6) & 0x1f) {
1435 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1436 if (env
->insn_flags
& ISA_MIPS32R2
) {
1445 MIPS_INVAL("invalid dsrlv flag");
1446 generate_exception(ctx
, EXCP_RI
);
1453 generate_exception(ctx
, EXCP_RI
);
1456 GEN_STORE_T0_REG(rd
);
1458 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1461 /* Arithmetic on HI/LO registers */
1462 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1464 const char *opn
= "hilo";
1466 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1474 GEN_STORE_T0_REG(reg
);
1479 GEN_STORE_T0_REG(reg
);
1483 GEN_LOAD_REG_T0(reg
);
1488 GEN_LOAD_REG_T0(reg
);
1494 generate_exception(ctx
, EXCP_RI
);
1497 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1500 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1503 const char *opn
= "mul/div";
1505 GEN_LOAD_REG_T0(rs
);
1506 GEN_LOAD_REG_T1(rt
);
1524 #if defined(TARGET_MIPS64)
1560 generate_exception(ctx
, EXCP_RI
);
1563 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
1566 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
1567 int rd
, int rs
, int rt
)
1569 const char *opn
= "mul vr54xx";
1571 GEN_LOAD_REG_T0(rs
);
1572 GEN_LOAD_REG_T1(rt
);
1575 case OPC_VR54XX_MULS
:
1579 case OPC_VR54XX_MULSU
:
1583 case OPC_VR54XX_MACC
:
1587 case OPC_VR54XX_MACCU
:
1591 case OPC_VR54XX_MSAC
:
1595 case OPC_VR54XX_MSACU
:
1599 case OPC_VR54XX_MULHI
:
1603 case OPC_VR54XX_MULHIU
:
1607 case OPC_VR54XX_MULSHI
:
1611 case OPC_VR54XX_MULSHIU
:
1615 case OPC_VR54XX_MACCHI
:
1619 case OPC_VR54XX_MACCHIU
:
1623 case OPC_VR54XX_MSACHI
:
1627 case OPC_VR54XX_MSACHIU
:
1632 MIPS_INVAL("mul vr54xx");
1633 generate_exception(ctx
, EXCP_RI
);
1636 GEN_STORE_T0_REG(rd
);
1637 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1640 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
1643 const char *opn
= "CLx";
1649 GEN_LOAD_REG_T0(rs
);
1659 #if defined(TARGET_MIPS64)
1671 generate_exception(ctx
, EXCP_RI
);
1674 gen_op_store_T0_gpr(rd
);
1675 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1679 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
1680 int rs
, int rt
, int16_t imm
)
1685 /* Load needed operands */
1693 /* Compare two registers */
1695 GEN_LOAD_REG_T0(rs
);
1696 GEN_LOAD_REG_T1(rt
);
1706 /* Compare register to immediate */
1707 if (rs
!= 0 || imm
!= 0) {
1708 GEN_LOAD_REG_T0(rs
);
1709 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1716 case OPC_TEQ
: /* rs == rs */
1717 case OPC_TEQI
: /* r0 == 0 */
1718 case OPC_TGE
: /* rs >= rs */
1719 case OPC_TGEI
: /* r0 >= 0 */
1720 case OPC_TGEU
: /* rs >= rs unsigned */
1721 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1725 case OPC_TLT
: /* rs < rs */
1726 case OPC_TLTI
: /* r0 < 0 */
1727 case OPC_TLTU
: /* rs < rs unsigned */
1728 case OPC_TLTIU
: /* r0 < 0 unsigned */
1729 case OPC_TNE
: /* rs != rs */
1730 case OPC_TNEI
: /* r0 != 0 */
1731 /* Never trap: treat as NOP. */
1735 generate_exception(ctx
, EXCP_RI
);
1766 generate_exception(ctx
, EXCP_RI
);
1770 save_cpu_state(ctx
, 1);
1772 ctx
->bstate
= BS_STOP
;
1775 static always_inline
void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1777 TranslationBlock
*tb
;
1779 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1781 gen_op_goto_tb0(TBPARAM(tb
));
1783 gen_op_goto_tb1(TBPARAM(tb
));
1785 gen_op_set_T0((long)tb
+ n
);
1793 /* Branches (before delay slot) */
1794 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
1795 int rs
, int rt
, int32_t offset
)
1797 target_ulong btarget
= -1;
1801 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1802 #ifdef MIPS_DEBUG_DISAS
1803 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1805 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
1809 generate_exception(ctx
, EXCP_RI
);
1813 /* Load needed operands */
1819 /* Compare two registers */
1821 GEN_LOAD_REG_T0(rs
);
1822 GEN_LOAD_REG_T1(rt
);
1825 btarget
= ctx
->pc
+ 4 + offset
;
1839 /* Compare to zero */
1841 gen_op_load_gpr_T0(rs
);
1844 btarget
= ctx
->pc
+ 4 + offset
;
1848 /* Jump to immediate */
1849 btarget
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
1853 /* Jump to register */
1854 if (offset
!= 0 && offset
!= 16) {
1855 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1856 others are reserved. */
1857 MIPS_INVAL("jump hint");
1858 generate_exception(ctx
, EXCP_RI
);
1861 GEN_LOAD_REG_T2(rs
);
1864 MIPS_INVAL("branch/jump");
1865 generate_exception(ctx
, EXCP_RI
);
1869 /* No condition to be computed */
1871 case OPC_BEQ
: /* rx == rx */
1872 case OPC_BEQL
: /* rx == rx likely */
1873 case OPC_BGEZ
: /* 0 >= 0 */
1874 case OPC_BGEZL
: /* 0 >= 0 likely */
1875 case OPC_BLEZ
: /* 0 <= 0 */
1876 case OPC_BLEZL
: /* 0 <= 0 likely */
1878 ctx
->hflags
|= MIPS_HFLAG_B
;
1879 MIPS_DEBUG("balways");
1881 case OPC_BGEZAL
: /* 0 >= 0 */
1882 case OPC_BGEZALL
: /* 0 >= 0 likely */
1883 /* Always take and link */
1885 ctx
->hflags
|= MIPS_HFLAG_B
;
1886 MIPS_DEBUG("balways and link");
1888 case OPC_BNE
: /* rx != rx */
1889 case OPC_BGTZ
: /* 0 > 0 */
1890 case OPC_BLTZ
: /* 0 < 0 */
1892 MIPS_DEBUG("bnever (NOP)");
1894 case OPC_BLTZAL
: /* 0 < 0 */
1895 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1896 gen_op_store_T0_gpr(31);
1897 MIPS_DEBUG("bnever and link");
1899 case OPC_BLTZALL
: /* 0 < 0 likely */
1900 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1901 gen_op_store_T0_gpr(31);
1902 /* Skip the instruction in the delay slot */
1903 MIPS_DEBUG("bnever, link and skip");
1906 case OPC_BNEL
: /* rx != rx likely */
1907 case OPC_BGTZL
: /* 0 > 0 likely */
1908 case OPC_BLTZL
: /* 0 < 0 likely */
1909 /* Skip the instruction in the delay slot */
1910 MIPS_DEBUG("bnever and skip");
1914 ctx
->hflags
|= MIPS_HFLAG_B
;
1915 MIPS_DEBUG("j " TARGET_FMT_lx
, btarget
);
1919 ctx
->hflags
|= MIPS_HFLAG_B
;
1920 MIPS_DEBUG("jal " TARGET_FMT_lx
, btarget
);
1923 ctx
->hflags
|= MIPS_HFLAG_BR
;
1924 MIPS_DEBUG("jr %s", regnames
[rs
]);
1928 ctx
->hflags
|= MIPS_HFLAG_BR
;
1929 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1932 MIPS_INVAL("branch/jump");
1933 generate_exception(ctx
, EXCP_RI
);
1940 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
1941 regnames
[rs
], regnames
[rt
], btarget
);
1945 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
1946 regnames
[rs
], regnames
[rt
], btarget
);
1950 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
1951 regnames
[rs
], regnames
[rt
], btarget
);
1955 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
1956 regnames
[rs
], regnames
[rt
], btarget
);
1960 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1964 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1968 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1974 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1978 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1982 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1986 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1990 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1994 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1998 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2003 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2005 ctx
->hflags
|= MIPS_HFLAG_BC
;
2011 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
2013 ctx
->hflags
|= MIPS_HFLAG_BL
;
2015 gen_op_save_bcond();
2018 MIPS_INVAL("conditional branch/jump");
2019 generate_exception(ctx
, EXCP_RI
);
2023 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2024 blink
, ctx
->hflags
, btarget
);
2026 ctx
->btarget
= btarget
;
2028 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
2029 gen_op_store_T0_gpr(blink
);
2033 /* special3 bitfield operations */
2034 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2035 int rs
, int lsb
, int msb
)
2037 GEN_LOAD_REG_T1(rs
);
2042 gen_op_ext(lsb
, msb
+ 1);
2044 #if defined(TARGET_MIPS64)
2048 gen_op_dext(lsb
, msb
+ 1 + 32);
2053 gen_op_dext(lsb
+ 32, msb
+ 1);
2058 gen_op_dext(lsb
, msb
+ 1);
2064 GEN_LOAD_REG_T0(rt
);
2065 gen_op_ins(lsb
, msb
- lsb
+ 1);
2067 #if defined(TARGET_MIPS64)
2071 GEN_LOAD_REG_T0(rt
);
2072 gen_op_dins(lsb
, msb
- lsb
+ 1 + 32);
2077 GEN_LOAD_REG_T0(rt
);
2078 gen_op_dins(lsb
+ 32, msb
- lsb
+ 1);
2083 GEN_LOAD_REG_T0(rt
);
2084 gen_op_dins(lsb
, msb
- lsb
+ 1);
2089 MIPS_INVAL("bitops");
2090 generate_exception(ctx
, EXCP_RI
);
2093 GEN_STORE_T0_REG(rt
);
2096 /* CP0 (MMU and control) */
2097 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2099 const char *rn
= "invalid";
2102 check_insn(env
, ctx
, ISA_MIPS32
);
2108 gen_op_mfc0_index();
2112 check_insn(env
, ctx
, ASE_MT
);
2113 gen_op_mfc0_mvpcontrol();
2117 check_insn(env
, ctx
, ASE_MT
);
2118 gen_op_mfc0_mvpconf0();
2122 check_insn(env
, ctx
, ASE_MT
);
2123 gen_op_mfc0_mvpconf1();
2133 gen_op_mfc0_random();
2137 check_insn(env
, ctx
, ASE_MT
);
2138 gen_op_mfc0_vpecontrol();
2142 check_insn(env
, ctx
, ASE_MT
);
2143 gen_op_mfc0_vpeconf0();
2147 check_insn(env
, ctx
, ASE_MT
);
2148 gen_op_mfc0_vpeconf1();
2152 check_insn(env
, ctx
, ASE_MT
);
2153 gen_op_mfc0_yqmask();
2157 check_insn(env
, ctx
, ASE_MT
);
2158 gen_op_mfc0_vpeschedule();
2162 check_insn(env
, ctx
, ASE_MT
);
2163 gen_op_mfc0_vpeschefback();
2164 rn
= "VPEScheFBack";
2167 check_insn(env
, ctx
, ASE_MT
);
2168 gen_op_mfc0_vpeopt();
2178 gen_op_mfc0_entrylo0();
2182 check_insn(env
, ctx
, ASE_MT
);
2183 gen_op_mfc0_tcstatus();
2187 check_insn(env
, ctx
, ASE_MT
);
2188 gen_op_mfc0_tcbind();
2192 check_insn(env
, ctx
, ASE_MT
);
2193 gen_op_mfc0_tcrestart();
2197 check_insn(env
, ctx
, ASE_MT
);
2198 gen_op_mfc0_tchalt();
2202 check_insn(env
, ctx
, ASE_MT
);
2203 gen_op_mfc0_tccontext();
2207 check_insn(env
, ctx
, ASE_MT
);
2208 gen_op_mfc0_tcschedule();
2212 check_insn(env
, ctx
, ASE_MT
);
2213 gen_op_mfc0_tcschefback();
2223 gen_op_mfc0_entrylo1();
2233 gen_op_mfc0_context();
2237 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
2238 rn
= "ContextConfig";
2247 gen_op_mfc0_pagemask();
2251 check_insn(env
, ctx
, ISA_MIPS32R2
);
2252 gen_op_mfc0_pagegrain();
2262 gen_op_mfc0_wired();
2266 check_insn(env
, ctx
, ISA_MIPS32R2
);
2267 gen_op_mfc0_srsconf0();
2271 check_insn(env
, ctx
, ISA_MIPS32R2
);
2272 gen_op_mfc0_srsconf1();
2276 check_insn(env
, ctx
, ISA_MIPS32R2
);
2277 gen_op_mfc0_srsconf2();
2281 check_insn(env
, ctx
, ISA_MIPS32R2
);
2282 gen_op_mfc0_srsconf3();
2286 check_insn(env
, ctx
, ISA_MIPS32R2
);
2287 gen_op_mfc0_srsconf4();
2297 check_insn(env
, ctx
, ISA_MIPS32R2
);
2298 gen_op_mfc0_hwrena();
2308 gen_op_mfc0_badvaddr();
2318 gen_op_mfc0_count();
2321 /* 6,7 are implementation dependent */
2329 gen_op_mfc0_entryhi();
2339 gen_op_mfc0_compare();
2342 /* 6,7 are implementation dependent */
2350 gen_op_mfc0_status();
2354 check_insn(env
, ctx
, ISA_MIPS32R2
);
2355 gen_op_mfc0_intctl();
2359 check_insn(env
, ctx
, ISA_MIPS32R2
);
2360 gen_op_mfc0_srsctl();
2364 check_insn(env
, ctx
, ISA_MIPS32R2
);
2365 gen_op_mfc0_srsmap();
2375 gen_op_mfc0_cause();
2399 check_insn(env
, ctx
, ISA_MIPS32R2
);
2400 gen_op_mfc0_ebase();
2410 gen_op_mfc0_config0();
2414 gen_op_mfc0_config1();
2418 gen_op_mfc0_config2();
2422 gen_op_mfc0_config3();
2425 /* 4,5 are reserved */
2426 /* 6,7 are implementation dependent */
2428 gen_op_mfc0_config6();
2432 gen_op_mfc0_config7();
2442 gen_op_mfc0_lladdr();
2452 gen_op_mfc0_watchlo(sel
);
2462 gen_op_mfc0_watchhi(sel
);
2472 #if defined(TARGET_MIPS64)
2473 check_insn(env
, ctx
, ISA_MIPS3
);
2474 gen_op_mfc0_xcontext();
2483 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2486 gen_op_mfc0_framemask();
2495 rn
= "'Diagnostic"; /* implementation dependent */
2500 gen_op_mfc0_debug(); /* EJTAG support */
2504 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2505 rn
= "TraceControl";
2508 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2509 rn
= "TraceControl2";
2512 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2513 rn
= "UserTraceData";
2516 // gen_op_mfc0_debug(); /* PDtrace support */
2526 gen_op_mfc0_depc(); /* EJTAG support */
2536 gen_op_mfc0_performance0();
2537 rn
= "Performance0";
2540 // gen_op_mfc0_performance1();
2541 rn
= "Performance1";
2544 // gen_op_mfc0_performance2();
2545 rn
= "Performance2";
2548 // gen_op_mfc0_performance3();
2549 rn
= "Performance3";
2552 // gen_op_mfc0_performance4();
2553 rn
= "Performance4";
2556 // gen_op_mfc0_performance5();
2557 rn
= "Performance5";
2560 // gen_op_mfc0_performance6();
2561 rn
= "Performance6";
2564 // gen_op_mfc0_performance7();
2565 rn
= "Performance7";
2590 gen_op_mfc0_taglo();
2597 gen_op_mfc0_datalo();
2610 gen_op_mfc0_taghi();
2617 gen_op_mfc0_datahi();
2627 gen_op_mfc0_errorepc();
2637 gen_op_mfc0_desave(); /* EJTAG support */
2647 #if defined MIPS_DEBUG_DISAS
2648 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2649 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2656 #if defined MIPS_DEBUG_DISAS
2657 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2658 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2662 generate_exception(ctx
, EXCP_RI
);
2665 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2667 const char *rn
= "invalid";
2670 check_insn(env
, ctx
, ISA_MIPS32
);
2676 gen_op_mtc0_index();
2680 check_insn(env
, ctx
, ASE_MT
);
2681 gen_op_mtc0_mvpcontrol();
2685 check_insn(env
, ctx
, ASE_MT
);
2690 check_insn(env
, ctx
, ASE_MT
);
2705 check_insn(env
, ctx
, ASE_MT
);
2706 gen_op_mtc0_vpecontrol();
2710 check_insn(env
, ctx
, ASE_MT
);
2711 gen_op_mtc0_vpeconf0();
2715 check_insn(env
, ctx
, ASE_MT
);
2716 gen_op_mtc0_vpeconf1();
2720 check_insn(env
, ctx
, ASE_MT
);
2721 gen_op_mtc0_yqmask();
2725 check_insn(env
, ctx
, ASE_MT
);
2726 gen_op_mtc0_vpeschedule();
2730 check_insn(env
, ctx
, ASE_MT
);
2731 gen_op_mtc0_vpeschefback();
2732 rn
= "VPEScheFBack";
2735 check_insn(env
, ctx
, ASE_MT
);
2736 gen_op_mtc0_vpeopt();
2746 gen_op_mtc0_entrylo0();
2750 check_insn(env
, ctx
, ASE_MT
);
2751 gen_op_mtc0_tcstatus();
2755 check_insn(env
, ctx
, ASE_MT
);
2756 gen_op_mtc0_tcbind();
2760 check_insn(env
, ctx
, ASE_MT
);
2761 gen_op_mtc0_tcrestart();
2765 check_insn(env
, ctx
, ASE_MT
);
2766 gen_op_mtc0_tchalt();
2770 check_insn(env
, ctx
, ASE_MT
);
2771 gen_op_mtc0_tccontext();
2775 check_insn(env
, ctx
, ASE_MT
);
2776 gen_op_mtc0_tcschedule();
2780 check_insn(env
, ctx
, ASE_MT
);
2781 gen_op_mtc0_tcschefback();
2791 gen_op_mtc0_entrylo1();
2801 gen_op_mtc0_context();
2805 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2806 rn
= "ContextConfig";
2815 gen_op_mtc0_pagemask();
2819 check_insn(env
, ctx
, ISA_MIPS32R2
);
2820 gen_op_mtc0_pagegrain();
2830 gen_op_mtc0_wired();
2834 check_insn(env
, ctx
, ISA_MIPS32R2
);
2835 gen_op_mtc0_srsconf0();
2839 check_insn(env
, ctx
, ISA_MIPS32R2
);
2840 gen_op_mtc0_srsconf1();
2844 check_insn(env
, ctx
, ISA_MIPS32R2
);
2845 gen_op_mtc0_srsconf2();
2849 check_insn(env
, ctx
, ISA_MIPS32R2
);
2850 gen_op_mtc0_srsconf3();
2854 check_insn(env
, ctx
, ISA_MIPS32R2
);
2855 gen_op_mtc0_srsconf4();
2865 check_insn(env
, ctx
, ISA_MIPS32R2
);
2866 gen_op_mtc0_hwrena();
2880 gen_op_mtc0_count();
2883 /* 6,7 are implementation dependent */
2887 /* Stop translation as we may have switched the execution mode */
2888 ctx
->bstate
= BS_STOP
;
2893 gen_op_mtc0_entryhi();
2903 gen_op_mtc0_compare();
2906 /* 6,7 are implementation dependent */
2910 /* Stop translation as we may have switched the execution mode */
2911 ctx
->bstate
= BS_STOP
;
2916 gen_op_mtc0_status();
2917 /* BS_STOP isn't good enough here, hflags may have changed. */
2918 gen_save_pc(ctx
->pc
+ 4);
2919 ctx
->bstate
= BS_EXCP
;
2923 check_insn(env
, ctx
, ISA_MIPS32R2
);
2924 gen_op_mtc0_intctl();
2925 /* Stop translation as we may have switched the execution mode */
2926 ctx
->bstate
= BS_STOP
;
2930 check_insn(env
, ctx
, ISA_MIPS32R2
);
2931 gen_op_mtc0_srsctl();
2932 /* Stop translation as we may have switched the execution mode */
2933 ctx
->bstate
= BS_STOP
;
2937 check_insn(env
, ctx
, ISA_MIPS32R2
);
2938 gen_op_mtc0_srsmap();
2939 /* Stop translation as we may have switched the execution mode */
2940 ctx
->bstate
= BS_STOP
;
2950 gen_op_mtc0_cause();
2956 /* Stop translation as we may have switched the execution mode */
2957 ctx
->bstate
= BS_STOP
;
2976 check_insn(env
, ctx
, ISA_MIPS32R2
);
2977 gen_op_mtc0_ebase();
2987 gen_op_mtc0_config0();
2989 /* Stop translation as we may have switched the execution mode */
2990 ctx
->bstate
= BS_STOP
;
2993 /* ignored, read only */
2997 gen_op_mtc0_config2();
2999 /* Stop translation as we may have switched the execution mode */
3000 ctx
->bstate
= BS_STOP
;
3003 /* ignored, read only */
3006 /* 4,5 are reserved */
3007 /* 6,7 are implementation dependent */
3017 rn
= "Invalid config selector";
3034 gen_op_mtc0_watchlo(sel
);
3044 gen_op_mtc0_watchhi(sel
);
3054 #if defined(TARGET_MIPS64)
3055 check_insn(env
, ctx
, ISA_MIPS3
);
3056 gen_op_mtc0_xcontext();
3065 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3068 gen_op_mtc0_framemask();
3077 rn
= "Diagnostic"; /* implementation dependent */
3082 gen_op_mtc0_debug(); /* EJTAG support */
3083 /* BS_STOP isn't good enough here, hflags may have changed. */
3084 gen_save_pc(ctx
->pc
+ 4);
3085 ctx
->bstate
= BS_EXCP
;
3089 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
3090 rn
= "TraceControl";
3091 /* Stop translation as we may have switched the execution mode */
3092 ctx
->bstate
= BS_STOP
;
3095 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
3096 rn
= "TraceControl2";
3097 /* Stop translation as we may have switched the execution mode */
3098 ctx
->bstate
= BS_STOP
;
3101 /* Stop translation as we may have switched the execution mode */
3102 ctx
->bstate
= BS_STOP
;
3103 // gen_op_mtc0_usertracedata(); /* PDtrace support */
3104 rn
= "UserTraceData";
3105 /* Stop translation as we may have switched the execution mode */
3106 ctx
->bstate
= BS_STOP
;
3109 // gen_op_mtc0_debug(); /* PDtrace support */
3110 /* Stop translation as we may have switched the execution mode */
3111 ctx
->bstate
= BS_STOP
;
3121 gen_op_mtc0_depc(); /* EJTAG support */
3131 gen_op_mtc0_performance0();
3132 rn
= "Performance0";
3135 // gen_op_mtc0_performance1();
3136 rn
= "Performance1";
3139 // gen_op_mtc0_performance2();
3140 rn
= "Performance2";
3143 // gen_op_mtc0_performance3();
3144 rn
= "Performance3";
3147 // gen_op_mtc0_performance4();
3148 rn
= "Performance4";
3151 // gen_op_mtc0_performance5();
3152 rn
= "Performance5";
3155 // gen_op_mtc0_performance6();
3156 rn
= "Performance6";
3159 // gen_op_mtc0_performance7();
3160 rn
= "Performance7";
3186 gen_op_mtc0_taglo();
3193 gen_op_mtc0_datalo();
3206 gen_op_mtc0_taghi();
3213 gen_op_mtc0_datahi();
3224 gen_op_mtc0_errorepc();
3234 gen_op_mtc0_desave(); /* EJTAG support */
3240 /* Stop translation as we may have switched the execution mode */
3241 ctx
->bstate
= BS_STOP
;
3246 #if defined MIPS_DEBUG_DISAS
3247 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3248 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3255 #if defined MIPS_DEBUG_DISAS
3256 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3257 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3261 generate_exception(ctx
, EXCP_RI
);
3264 #if defined(TARGET_MIPS64)
3265 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3267 const char *rn
= "invalid";
3270 check_insn(env
, ctx
, ISA_MIPS64
);
3276 gen_op_mfc0_index();
3280 check_insn(env
, ctx
, ASE_MT
);
3281 gen_op_mfc0_mvpcontrol();
3285 check_insn(env
, ctx
, ASE_MT
);
3286 gen_op_mfc0_mvpconf0();
3290 check_insn(env
, ctx
, ASE_MT
);
3291 gen_op_mfc0_mvpconf1();
3301 gen_op_mfc0_random();
3305 check_insn(env
, ctx
, ASE_MT
);
3306 gen_op_mfc0_vpecontrol();
3310 check_insn(env
, ctx
, ASE_MT
);
3311 gen_op_mfc0_vpeconf0();
3315 check_insn(env
, ctx
, ASE_MT
);
3316 gen_op_mfc0_vpeconf1();
3320 check_insn(env
, ctx
, ASE_MT
);
3321 gen_op_dmfc0_yqmask();
3325 check_insn(env
, ctx
, ASE_MT
);
3326 gen_op_dmfc0_vpeschedule();
3330 check_insn(env
, ctx
, ASE_MT
);
3331 gen_op_dmfc0_vpeschefback();
3332 rn
= "VPEScheFBack";
3335 check_insn(env
, ctx
, ASE_MT
);
3336 gen_op_mfc0_vpeopt();
3346 gen_op_dmfc0_entrylo0();
3350 check_insn(env
, ctx
, ASE_MT
);
3351 gen_op_mfc0_tcstatus();
3355 check_insn(env
, ctx
, ASE_MT
);
3356 gen_op_mfc0_tcbind();
3360 check_insn(env
, ctx
, ASE_MT
);
3361 gen_op_dmfc0_tcrestart();
3365 check_insn(env
, ctx
, ASE_MT
);
3366 gen_op_dmfc0_tchalt();
3370 check_insn(env
, ctx
, ASE_MT
);
3371 gen_op_dmfc0_tccontext();
3375 check_insn(env
, ctx
, ASE_MT
);
3376 gen_op_dmfc0_tcschedule();
3380 check_insn(env
, ctx
, ASE_MT
);
3381 gen_op_dmfc0_tcschefback();
3391 gen_op_dmfc0_entrylo1();
3401 gen_op_dmfc0_context();
3405 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
3406 rn
= "ContextConfig";
3415 gen_op_mfc0_pagemask();
3419 check_insn(env
, ctx
, ISA_MIPS32R2
);
3420 gen_op_mfc0_pagegrain();
3430 gen_op_mfc0_wired();
3434 check_insn(env
, ctx
, ISA_MIPS32R2
);
3435 gen_op_mfc0_srsconf0();
3439 check_insn(env
, ctx
, ISA_MIPS32R2
);
3440 gen_op_mfc0_srsconf1();
3444 check_insn(env
, ctx
, ISA_MIPS32R2
);
3445 gen_op_mfc0_srsconf2();
3449 check_insn(env
, ctx
, ISA_MIPS32R2
);
3450 gen_op_mfc0_srsconf3();
3454 check_insn(env
, ctx
, ISA_MIPS32R2
);
3455 gen_op_mfc0_srsconf4();
3465 check_insn(env
, ctx
, ISA_MIPS32R2
);
3466 gen_op_mfc0_hwrena();
3476 gen_op_dmfc0_badvaddr();
3486 gen_op_mfc0_count();
3489 /* 6,7 are implementation dependent */
3497 gen_op_dmfc0_entryhi();
3507 gen_op_mfc0_compare();
3510 /* 6,7 are implementation dependent */
3518 gen_op_mfc0_status();
3522 check_insn(env
, ctx
, ISA_MIPS32R2
);
3523 gen_op_mfc0_intctl();
3527 check_insn(env
, ctx
, ISA_MIPS32R2
);
3528 gen_op_mfc0_srsctl();
3532 check_insn(env
, ctx
, ISA_MIPS32R2
);
3533 gen_op_mfc0_srsmap();
3543 gen_op_mfc0_cause();
3567 check_insn(env
, ctx
, ISA_MIPS32R2
);
3568 gen_op_mfc0_ebase();
3578 gen_op_mfc0_config0();
3582 gen_op_mfc0_config1();
3586 gen_op_mfc0_config2();
3590 gen_op_mfc0_config3();
3593 /* 6,7 are implementation dependent */
3601 gen_op_dmfc0_lladdr();
3611 gen_op_dmfc0_watchlo(sel
);
3621 gen_op_mfc0_watchhi(sel
);
3631 check_insn(env
, ctx
, ISA_MIPS3
);
3632 gen_op_dmfc0_xcontext();
3640 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3643 gen_op_mfc0_framemask();
3652 rn
= "'Diagnostic"; /* implementation dependent */
3657 gen_op_mfc0_debug(); /* EJTAG support */
3661 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3662 rn
= "TraceControl";
3665 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3666 rn
= "TraceControl2";
3669 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3670 rn
= "UserTraceData";
3673 // gen_op_dmfc0_debug(); /* PDtrace support */
3683 gen_op_dmfc0_depc(); /* EJTAG support */
3693 gen_op_mfc0_performance0();
3694 rn
= "Performance0";
3697 // gen_op_dmfc0_performance1();
3698 rn
= "Performance1";
3701 // gen_op_dmfc0_performance2();
3702 rn
= "Performance2";
3705 // gen_op_dmfc0_performance3();
3706 rn
= "Performance3";
3709 // gen_op_dmfc0_performance4();
3710 rn
= "Performance4";
3713 // gen_op_dmfc0_performance5();
3714 rn
= "Performance5";
3717 // gen_op_dmfc0_performance6();
3718 rn
= "Performance6";
3721 // gen_op_dmfc0_performance7();
3722 rn
= "Performance7";
3747 gen_op_mfc0_taglo();
3754 gen_op_mfc0_datalo();
3767 gen_op_mfc0_taghi();
3774 gen_op_mfc0_datahi();
3784 gen_op_dmfc0_errorepc();
3794 gen_op_mfc0_desave(); /* EJTAG support */
3804 #if defined MIPS_DEBUG_DISAS
3805 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3806 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3813 #if defined MIPS_DEBUG_DISAS
3814 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3815 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3819 generate_exception(ctx
, EXCP_RI
);
3822 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3824 const char *rn
= "invalid";
3827 check_insn(env
, ctx
, ISA_MIPS64
);
3833 gen_op_mtc0_index();
3837 check_insn(env
, ctx
, ASE_MT
);
3838 gen_op_mtc0_mvpcontrol();
3842 check_insn(env
, ctx
, ASE_MT
);
3847 check_insn(env
, ctx
, ASE_MT
);
3862 check_insn(env
, ctx
, ASE_MT
);
3863 gen_op_mtc0_vpecontrol();
3867 check_insn(env
, ctx
, ASE_MT
);
3868 gen_op_mtc0_vpeconf0();
3872 check_insn(env
, ctx
, ASE_MT
);
3873 gen_op_mtc0_vpeconf1();
3877 check_insn(env
, ctx
, ASE_MT
);
3878 gen_op_mtc0_yqmask();
3882 check_insn(env
, ctx
, ASE_MT
);
3883 gen_op_mtc0_vpeschedule();
3887 check_insn(env
, ctx
, ASE_MT
);
3888 gen_op_mtc0_vpeschefback();
3889 rn
= "VPEScheFBack";
3892 check_insn(env
, ctx
, ASE_MT
);
3893 gen_op_mtc0_vpeopt();
3903 gen_op_mtc0_entrylo0();
3907 check_insn(env
, ctx
, ASE_MT
);
3908 gen_op_mtc0_tcstatus();
3912 check_insn(env
, ctx
, ASE_MT
);
3913 gen_op_mtc0_tcbind();
3917 check_insn(env
, ctx
, ASE_MT
);
3918 gen_op_mtc0_tcrestart();
3922 check_insn(env
, ctx
, ASE_MT
);
3923 gen_op_mtc0_tchalt();
3927 check_insn(env
, ctx
, ASE_MT
);
3928 gen_op_mtc0_tccontext();
3932 check_insn(env
, ctx
, ASE_MT
);
3933 gen_op_mtc0_tcschedule();
3937 check_insn(env
, ctx
, ASE_MT
);
3938 gen_op_mtc0_tcschefback();
3948 gen_op_mtc0_entrylo1();
3958 gen_op_mtc0_context();
3962 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
3963 rn
= "ContextConfig";
3972 gen_op_mtc0_pagemask();
3976 check_insn(env
, ctx
, ISA_MIPS32R2
);
3977 gen_op_mtc0_pagegrain();
3987 gen_op_mtc0_wired();
3991 check_insn(env
, ctx
, ISA_MIPS32R2
);
3992 gen_op_mtc0_srsconf0();
3996 check_insn(env
, ctx
, ISA_MIPS32R2
);
3997 gen_op_mtc0_srsconf1();
4001 check_insn(env
, ctx
, ISA_MIPS32R2
);
4002 gen_op_mtc0_srsconf2();
4006 check_insn(env
, ctx
, ISA_MIPS32R2
);
4007 gen_op_mtc0_srsconf3();
4011 check_insn(env
, ctx
, ISA_MIPS32R2
);
4012 gen_op_mtc0_srsconf4();
4022 check_insn(env
, ctx
, ISA_MIPS32R2
);
4023 gen_op_mtc0_hwrena();
4037 gen_op_mtc0_count();
4040 /* 6,7 are implementation dependent */
4044 /* Stop translation as we may have switched the execution mode */
4045 ctx
->bstate
= BS_STOP
;
4050 gen_op_mtc0_entryhi();
4060 gen_op_mtc0_compare();
4063 /* 6,7 are implementation dependent */
4067 /* Stop translation as we may have switched the execution mode */
4068 ctx
->bstate
= BS_STOP
;
4073 gen_op_mtc0_status();
4074 /* BS_STOP isn't good enough here, hflags may have changed. */
4075 gen_save_pc(ctx
->pc
+ 4);
4076 ctx
->bstate
= BS_EXCP
;
4080 check_insn(env
, ctx
, ISA_MIPS32R2
);
4081 gen_op_mtc0_intctl();
4082 /* Stop translation as we may have switched the execution mode */
4083 ctx
->bstate
= BS_STOP
;
4087 check_insn(env
, ctx
, ISA_MIPS32R2
);
4088 gen_op_mtc0_srsctl();
4089 /* Stop translation as we may have switched the execution mode */
4090 ctx
->bstate
= BS_STOP
;
4094 check_insn(env
, ctx
, ISA_MIPS32R2
);
4095 gen_op_mtc0_srsmap();
4096 /* Stop translation as we may have switched the execution mode */
4097 ctx
->bstate
= BS_STOP
;
4107 gen_op_mtc0_cause();
4113 /* Stop translation as we may have switched the execution mode */
4114 ctx
->bstate
= BS_STOP
;
4133 check_insn(env
, ctx
, ISA_MIPS32R2
);
4134 gen_op_mtc0_ebase();
4144 gen_op_mtc0_config0();
4146 /* Stop translation as we may have switched the execution mode */
4147 ctx
->bstate
= BS_STOP
;
4154 gen_op_mtc0_config2();
4156 /* Stop translation as we may have switched the execution mode */
4157 ctx
->bstate
= BS_STOP
;
4163 /* 6,7 are implementation dependent */
4165 rn
= "Invalid config selector";
4182 gen_op_mtc0_watchlo(sel
);
4192 gen_op_mtc0_watchhi(sel
);
4202 check_insn(env
, ctx
, ISA_MIPS3
);
4203 gen_op_mtc0_xcontext();
4211 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4214 gen_op_mtc0_framemask();
4223 rn
= "Diagnostic"; /* implementation dependent */
4228 gen_op_mtc0_debug(); /* EJTAG support */
4229 /* BS_STOP isn't good enough here, hflags may have changed. */
4230 gen_save_pc(ctx
->pc
+ 4);
4231 ctx
->bstate
= BS_EXCP
;
4235 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
4236 /* Stop translation as we may have switched the execution mode */
4237 ctx
->bstate
= BS_STOP
;
4238 rn
= "TraceControl";
4241 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
4242 /* Stop translation as we may have switched the execution mode */
4243 ctx
->bstate
= BS_STOP
;
4244 rn
= "TraceControl2";
4247 // gen_op_mtc0_usertracedata(); /* PDtrace support */
4248 /* Stop translation as we may have switched the execution mode */
4249 ctx
->bstate
= BS_STOP
;
4250 rn
= "UserTraceData";
4253 // gen_op_mtc0_debug(); /* PDtrace support */
4254 /* Stop translation as we may have switched the execution mode */
4255 ctx
->bstate
= BS_STOP
;
4265 gen_op_mtc0_depc(); /* EJTAG support */
4275 gen_op_mtc0_performance0();
4276 rn
= "Performance0";
4279 // gen_op_mtc0_performance1();
4280 rn
= "Performance1";
4283 // gen_op_mtc0_performance2();
4284 rn
= "Performance2";
4287 // gen_op_mtc0_performance3();
4288 rn
= "Performance3";
4291 // gen_op_mtc0_performance4();
4292 rn
= "Performance4";
4295 // gen_op_mtc0_performance5();
4296 rn
= "Performance5";
4299 // gen_op_mtc0_performance6();
4300 rn
= "Performance6";
4303 // gen_op_mtc0_performance7();
4304 rn
= "Performance7";
4330 gen_op_mtc0_taglo();
4337 gen_op_mtc0_datalo();
4350 gen_op_mtc0_taghi();
4357 gen_op_mtc0_datahi();
4368 gen_op_mtc0_errorepc();
4378 gen_op_mtc0_desave(); /* EJTAG support */
4384 /* Stop translation as we may have switched the execution mode */
4385 ctx
->bstate
= BS_STOP
;
4390 #if defined MIPS_DEBUG_DISAS
4391 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4392 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4399 #if defined MIPS_DEBUG_DISAS
4400 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4401 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4405 generate_exception(ctx
, EXCP_RI
);
4407 #endif /* TARGET_MIPS64 */
4409 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
,
4410 int u
, int sel
, int h
)
4412 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4414 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4415 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4416 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4418 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4419 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4426 gen_op_mftc0_tcstatus();
4429 gen_op_mftc0_tcbind();
4432 gen_op_mftc0_tcrestart();
4435 gen_op_mftc0_tchalt();
4438 gen_op_mftc0_tccontext();
4441 gen_op_mftc0_tcschedule();
4444 gen_op_mftc0_tcschefback();
4447 gen_mfc0(env
, ctx
, rt
, sel
);
4454 gen_op_mftc0_entryhi();
4457 gen_mfc0(env
, ctx
, rt
, sel
);
4463 gen_op_mftc0_status();
4466 gen_mfc0(env
, ctx
, rt
, sel
);
4472 gen_op_mftc0_debug();
4475 gen_mfc0(env
, ctx
, rt
, sel
);
4480 gen_mfc0(env
, ctx
, rt
, sel
);
4482 } else switch (sel
) {
4483 /* GPR registers. */
4487 /* Auxiliary CPU registers */
4533 /* Floating point (COP1). */
4535 /* XXX: For now we support only a single FPU context. */
4537 GEN_LOAD_FREG_FTN(WT0
, rt
);
4540 GEN_LOAD_FREG_FTN(WTH0
, rt
);
4545 /* XXX: For now we support only a single FPU context. */
4548 /* COP2: Not implemented. */
4555 #if defined MIPS_DEBUG_DISAS
4556 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4557 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4564 #if defined MIPS_DEBUG_DISAS
4565 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4566 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4570 generate_exception(ctx
, EXCP_RI
);
4573 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
,
4574 int u
, int sel
, int h
)
4576 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4578 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4579 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4580 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4582 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4583 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4590 gen_op_mttc0_tcstatus();
4593 gen_op_mttc0_tcbind();
4596 gen_op_mttc0_tcrestart();
4599 gen_op_mttc0_tchalt();
4602 gen_op_mttc0_tccontext();
4605 gen_op_mttc0_tcschedule();
4608 gen_op_mttc0_tcschefback();
4611 gen_mtc0(env
, ctx
, rd
, sel
);
4618 gen_op_mttc0_entryhi();
4621 gen_mtc0(env
, ctx
, rd
, sel
);
4627 gen_op_mttc0_status();
4630 gen_mtc0(env
, ctx
, rd
, sel
);
4636 gen_op_mttc0_debug();
4639 gen_mtc0(env
, ctx
, rd
, sel
);
4644 gen_mtc0(env
, ctx
, rd
, sel
);
4646 } else switch (sel
) {
4647 /* GPR registers. */
4651 /* Auxiliary CPU registers */
4697 /* Floating point (COP1). */
4699 /* XXX: For now we support only a single FPU context. */
4702 GEN_STORE_FTN_FREG(rd
, WT0
);
4705 GEN_STORE_FTN_FREG(rd
, WTH0
);
4709 /* XXX: For now we support only a single FPU context. */
4712 /* COP2: Not implemented. */
4719 #if defined MIPS_DEBUG_DISAS
4720 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4721 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4728 #if defined MIPS_DEBUG_DISAS
4729 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4730 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4734 generate_exception(ctx
, EXCP_RI
);
4737 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
4739 const char *opn
= "ldst";
4747 gen_mfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4748 gen_op_store_T0_gpr(rt
);
4752 GEN_LOAD_REG_T0(rt
);
4753 save_cpu_state(ctx
, 1);
4754 gen_mtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4757 #if defined(TARGET_MIPS64)
4759 check_insn(env
, ctx
, ISA_MIPS3
);
4764 gen_dmfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4765 gen_op_store_T0_gpr(rt
);
4769 check_insn(env
, ctx
, ISA_MIPS3
);
4770 GEN_LOAD_REG_T0(rt
);
4771 save_cpu_state(ctx
, 1);
4772 gen_dmtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4777 check_insn(env
, ctx
, ASE_MT
);
4782 gen_mftr(env
, ctx
, rt
, (ctx
->opcode
>> 5) & 1,
4783 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4784 gen_op_store_T0_gpr(rd
);
4788 check_insn(env
, ctx
, ASE_MT
);
4789 GEN_LOAD_REG_T0(rt
);
4790 gen_mttr(env
, ctx
, rd
, (ctx
->opcode
>> 5) & 1,
4791 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4796 if (!env
->tlb
->do_tlbwi
)
4802 if (!env
->tlb
->do_tlbwr
)
4808 if (!env
->tlb
->do_tlbp
)
4814 if (!env
->tlb
->do_tlbr
)
4820 check_insn(env
, ctx
, ISA_MIPS2
);
4821 save_cpu_state(ctx
, 1);
4823 ctx
->bstate
= BS_EXCP
;
4827 check_insn(env
, ctx
, ISA_MIPS32
);
4828 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
4830 generate_exception(ctx
, EXCP_RI
);
4832 save_cpu_state(ctx
, 1);
4834 ctx
->bstate
= BS_EXCP
;
4839 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
4840 /* If we get an exception, we want to restart at next instruction */
4842 save_cpu_state(ctx
, 1);
4845 ctx
->bstate
= BS_EXCP
;
4850 generate_exception(ctx
, EXCP_RI
);
4853 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
4856 /* CP1 Branches (before delay slot) */
4857 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
4858 int32_t cc
, int32_t offset
)
4860 target_ulong btarget
;
4861 const char *opn
= "cp1 cond branch";
4864 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
4866 btarget
= ctx
->pc
+ 4 + offset
;
4885 ctx
->hflags
|= MIPS_HFLAG_BL
;
4887 gen_op_save_bcond();
4890 gen_op_bc1any2f(cc
);
4894 gen_op_bc1any2t(cc
);
4898 gen_op_bc1any4f(cc
);
4902 gen_op_bc1any4t(cc
);
4905 ctx
->hflags
|= MIPS_HFLAG_BC
;
4910 generate_exception (ctx
, EXCP_RI
);
4913 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
4914 ctx
->hflags
, btarget
);
4915 ctx
->btarget
= btarget
;
4918 /* Coprocessor 1 (FPU) */
4920 #define FOP(func, fmt) (((fmt) << 21) | (func))
4922 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
4924 const char *opn
= "cp1 move";
4928 GEN_LOAD_FREG_FTN(WT0
, fs
);
4930 GEN_STORE_T0_REG(rt
);
4934 GEN_LOAD_REG_T0(rt
);
4936 GEN_STORE_FTN_FREG(fs
, WT0
);
4941 GEN_STORE_T0_REG(rt
);
4945 GEN_LOAD_REG_T0(rt
);
4950 GEN_LOAD_FREG_FTN(DT0
, fs
);
4952 GEN_STORE_T0_REG(rt
);
4956 GEN_LOAD_REG_T0(rt
);
4958 GEN_STORE_FTN_FREG(fs
, DT0
);
4962 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4964 GEN_STORE_T0_REG(rt
);
4968 GEN_LOAD_REG_T0(rt
);
4970 GEN_STORE_FTN_FREG(fs
, WTH0
);
4975 generate_exception (ctx
, EXCP_RI
);
4978 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
4981 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
4985 GEN_LOAD_REG_T0(rd
);
4986 GEN_LOAD_REG_T1(rs
);
4988 ccbit
= 1 << (24 + cc
);
4995 GEN_STORE_T0_REG(rd
);
4998 #define GEN_MOVCF(fmt) \
4999 static void glue(gen_movcf_, fmt) (DisasContext *ctx, int cc, int tf) \
5004 ccbit = 1 << (24 + cc); \
5008 glue(gen_op_float_movf_, fmt)(ccbit); \
5010 glue(gen_op_float_movt_, fmt)(ccbit); \
5017 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5018 int ft
, int fs
, int fd
, int cc
)
5020 const char *opn
= "farith";
5021 const char *condnames
[] = {
5039 const char *condnames_abs
[] = {
5057 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
5058 uint32_t func
= ctx
->opcode
& 0x3f;
5060 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
5062 GEN_LOAD_FREG_FTN(WT0
, fs
);
5063 GEN_LOAD_FREG_FTN(WT1
, ft
);
5064 gen_op_float_add_s();
5065 GEN_STORE_FTN_FREG(fd
, WT2
);
5070 GEN_LOAD_FREG_FTN(WT0
, fs
);
5071 GEN_LOAD_FREG_FTN(WT1
, ft
);
5072 gen_op_float_sub_s();
5073 GEN_STORE_FTN_FREG(fd
, WT2
);
5078 GEN_LOAD_FREG_FTN(WT0
, fs
);
5079 GEN_LOAD_FREG_FTN(WT1
, ft
);
5080 gen_op_float_mul_s();
5081 GEN_STORE_FTN_FREG(fd
, WT2
);
5086 GEN_LOAD_FREG_FTN(WT0
, fs
);
5087 GEN_LOAD_FREG_FTN(WT1
, ft
);
5088 gen_op_float_div_s();
5089 GEN_STORE_FTN_FREG(fd
, WT2
);
5094 GEN_LOAD_FREG_FTN(WT0
, fs
);
5095 gen_op_float_sqrt_s();
5096 GEN_STORE_FTN_FREG(fd
, WT2
);
5100 GEN_LOAD_FREG_FTN(WT0
, fs
);
5101 gen_op_float_abs_s();
5102 GEN_STORE_FTN_FREG(fd
, WT2
);
5106 GEN_LOAD_FREG_FTN(WT0
, fs
);
5107 gen_op_float_mov_s();
5108 GEN_STORE_FTN_FREG(fd
, WT2
);
5112 GEN_LOAD_FREG_FTN(WT0
, fs
);
5113 gen_op_float_chs_s();
5114 GEN_STORE_FTN_FREG(fd
, WT2
);
5118 check_cp1_64bitmode(ctx
);
5119 GEN_LOAD_FREG_FTN(WT0
, fs
);
5120 gen_op_float_roundl_s();
5121 GEN_STORE_FTN_FREG(fd
, DT2
);
5125 check_cp1_64bitmode(ctx
);
5126 GEN_LOAD_FREG_FTN(WT0
, fs
);
5127 gen_op_float_truncl_s();
5128 GEN_STORE_FTN_FREG(fd
, DT2
);
5132 check_cp1_64bitmode(ctx
);
5133 GEN_LOAD_FREG_FTN(WT0
, fs
);
5134 gen_op_float_ceill_s();
5135 GEN_STORE_FTN_FREG(fd
, DT2
);
5139 check_cp1_64bitmode(ctx
);
5140 GEN_LOAD_FREG_FTN(WT0
, fs
);
5141 gen_op_float_floorl_s();
5142 GEN_STORE_FTN_FREG(fd
, DT2
);
5146 GEN_LOAD_FREG_FTN(WT0
, fs
);
5147 gen_op_float_roundw_s();
5148 GEN_STORE_FTN_FREG(fd
, WT2
);
5152 GEN_LOAD_FREG_FTN(WT0
, fs
);
5153 gen_op_float_truncw_s();
5154 GEN_STORE_FTN_FREG(fd
, WT2
);
5158 GEN_LOAD_FREG_FTN(WT0
, fs
);
5159 gen_op_float_ceilw_s();
5160 GEN_STORE_FTN_FREG(fd
, WT2
);
5164 GEN_LOAD_FREG_FTN(WT0
, fs
);
5165 gen_op_float_floorw_s();
5166 GEN_STORE_FTN_FREG(fd
, WT2
);
5170 GEN_LOAD_REG_T0(ft
);
5171 GEN_LOAD_FREG_FTN(WT0
, fs
);
5172 GEN_LOAD_FREG_FTN(WT2
, fd
);
5173 gen_movcf_s(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5174 GEN_STORE_FTN_FREG(fd
, WT2
);
5178 GEN_LOAD_REG_T0(ft
);
5179 GEN_LOAD_FREG_FTN(WT0
, fs
);
5180 GEN_LOAD_FREG_FTN(WT2
, fd
);
5181 gen_op_float_movz_s();
5182 GEN_STORE_FTN_FREG(fd
, WT2
);
5186 GEN_LOAD_REG_T0(ft
);
5187 GEN_LOAD_FREG_FTN(WT0
, fs
);
5188 GEN_LOAD_FREG_FTN(WT2
, fd
);
5189 gen_op_float_movn_s();
5190 GEN_STORE_FTN_FREG(fd
, WT2
);
5195 GEN_LOAD_FREG_FTN(WT0
, fs
);
5196 gen_op_float_recip_s();
5197 GEN_STORE_FTN_FREG(fd
, WT2
);
5202 GEN_LOAD_FREG_FTN(WT0
, fs
);
5203 gen_op_float_rsqrt_s();
5204 GEN_STORE_FTN_FREG(fd
, WT2
);
5208 check_cp1_64bitmode(ctx
);
5209 GEN_LOAD_FREG_FTN(WT0
, fs
);
5210 GEN_LOAD_FREG_FTN(WT2
, fd
);
5211 gen_op_float_recip2_s();
5212 GEN_STORE_FTN_FREG(fd
, WT2
);
5216 check_cp1_64bitmode(ctx
);
5217 GEN_LOAD_FREG_FTN(WT0
, fs
);
5218 gen_op_float_recip1_s();
5219 GEN_STORE_FTN_FREG(fd
, WT2
);
5223 check_cp1_64bitmode(ctx
);
5224 GEN_LOAD_FREG_FTN(WT0
, fs
);
5225 gen_op_float_rsqrt1_s();
5226 GEN_STORE_FTN_FREG(fd
, WT2
);
5230 check_cp1_64bitmode(ctx
);
5231 GEN_LOAD_FREG_FTN(WT0
, fs
);
5232 GEN_LOAD_FREG_FTN(WT2
, ft
);
5233 gen_op_float_rsqrt2_s();
5234 GEN_STORE_FTN_FREG(fd
, WT2
);
5238 check_cp1_registers(ctx
, fd
);
5239 GEN_LOAD_FREG_FTN(WT0
, fs
);
5240 gen_op_float_cvtd_s();
5241 GEN_STORE_FTN_FREG(fd
, DT2
);
5245 GEN_LOAD_FREG_FTN(WT0
, fs
);
5246 gen_op_float_cvtw_s();
5247 GEN_STORE_FTN_FREG(fd
, WT2
);
5251 check_cp1_64bitmode(ctx
);
5252 GEN_LOAD_FREG_FTN(WT0
, fs
);
5253 gen_op_float_cvtl_s();
5254 GEN_STORE_FTN_FREG(fd
, DT2
);
5258 check_cp1_64bitmode(ctx
);
5259 GEN_LOAD_FREG_FTN(WT1
, fs
);
5260 GEN_LOAD_FREG_FTN(WT0
, ft
);
5261 gen_op_float_cvtps_s();
5262 GEN_STORE_FTN_FREG(fd
, DT2
);
5281 GEN_LOAD_FREG_FTN(WT0
, fs
);
5282 GEN_LOAD_FREG_FTN(WT1
, ft
);
5283 if (ctx
->opcode
& (1 << 6)) {
5285 gen_cmpabs_s(func
-48, cc
);
5286 opn
= condnames_abs
[func
-48];
5288 gen_cmp_s(func
-48, cc
);
5289 opn
= condnames
[func
-48];
5293 check_cp1_registers(ctx
, fs
| ft
| fd
);
5294 GEN_LOAD_FREG_FTN(DT0
, fs
);
5295 GEN_LOAD_FREG_FTN(DT1
, ft
);
5296 gen_op_float_add_d();
5297 GEN_STORE_FTN_FREG(fd
, DT2
);
5302 check_cp1_registers(ctx
, fs
| ft
| fd
);
5303 GEN_LOAD_FREG_FTN(DT0
, fs
);
5304 GEN_LOAD_FREG_FTN(DT1
, ft
);
5305 gen_op_float_sub_d();
5306 GEN_STORE_FTN_FREG(fd
, DT2
);
5311 check_cp1_registers(ctx
, fs
| ft
| fd
);
5312 GEN_LOAD_FREG_FTN(DT0
, fs
);
5313 GEN_LOAD_FREG_FTN(DT1
, ft
);
5314 gen_op_float_mul_d();
5315 GEN_STORE_FTN_FREG(fd
, DT2
);
5320 check_cp1_registers(ctx
, fs
| ft
| fd
);
5321 GEN_LOAD_FREG_FTN(DT0
, fs
);
5322 GEN_LOAD_FREG_FTN(DT1
, ft
);
5323 gen_op_float_div_d();
5324 GEN_STORE_FTN_FREG(fd
, DT2
);
5329 check_cp1_registers(ctx
, fs
| fd
);
5330 GEN_LOAD_FREG_FTN(DT0
, fs
);
5331 gen_op_float_sqrt_d();
5332 GEN_STORE_FTN_FREG(fd
, DT2
);
5336 check_cp1_registers(ctx
, fs
| fd
);
5337 GEN_LOAD_FREG_FTN(DT0
, fs
);
5338 gen_op_float_abs_d();
5339 GEN_STORE_FTN_FREG(fd
, DT2
);
5343 check_cp1_registers(ctx
, fs
| fd
);
5344 GEN_LOAD_FREG_FTN(DT0
, fs
);
5345 gen_op_float_mov_d();
5346 GEN_STORE_FTN_FREG(fd
, DT2
);
5350 check_cp1_registers(ctx
, fs
| fd
);
5351 GEN_LOAD_FREG_FTN(DT0
, fs
);
5352 gen_op_float_chs_d();
5353 GEN_STORE_FTN_FREG(fd
, DT2
);
5357 check_cp1_64bitmode(ctx
);
5358 GEN_LOAD_FREG_FTN(DT0
, fs
);
5359 gen_op_float_roundl_d();
5360 GEN_STORE_FTN_FREG(fd
, DT2
);
5364 check_cp1_64bitmode(ctx
);
5365 GEN_LOAD_FREG_FTN(DT0
, fs
);
5366 gen_op_float_truncl_d();
5367 GEN_STORE_FTN_FREG(fd
, DT2
);
5371 check_cp1_64bitmode(ctx
);
5372 GEN_LOAD_FREG_FTN(DT0
, fs
);
5373 gen_op_float_ceill_d();
5374 GEN_STORE_FTN_FREG(fd
, DT2
);
5378 check_cp1_64bitmode(ctx
);
5379 GEN_LOAD_FREG_FTN(DT0
, fs
);
5380 gen_op_float_floorl_d();
5381 GEN_STORE_FTN_FREG(fd
, DT2
);
5385 check_cp1_registers(ctx
, fs
);
5386 GEN_LOAD_FREG_FTN(DT0
, fs
);
5387 gen_op_float_roundw_d();
5388 GEN_STORE_FTN_FREG(fd
, WT2
);
5392 check_cp1_registers(ctx
, fs
);
5393 GEN_LOAD_FREG_FTN(DT0
, fs
);
5394 gen_op_float_truncw_d();
5395 GEN_STORE_FTN_FREG(fd
, WT2
);
5399 check_cp1_registers(ctx
, fs
);
5400 GEN_LOAD_FREG_FTN(DT0
, fs
);
5401 gen_op_float_ceilw_d();
5402 GEN_STORE_FTN_FREG(fd
, WT2
);
5406 check_cp1_registers(ctx
, fs
);
5407 GEN_LOAD_FREG_FTN(DT0
, fs
);
5408 gen_op_float_floorw_d();
5409 GEN_STORE_FTN_FREG(fd
, WT2
);
5413 GEN_LOAD_REG_T0(ft
);
5414 GEN_LOAD_FREG_FTN(DT0
, fs
);
5415 GEN_LOAD_FREG_FTN(DT2
, fd
);
5416 gen_movcf_d(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5417 GEN_STORE_FTN_FREG(fd
, DT2
);
5421 GEN_LOAD_REG_T0(ft
);
5422 GEN_LOAD_FREG_FTN(DT0
, fs
);
5423 GEN_LOAD_FREG_FTN(DT2
, fd
);
5424 gen_op_float_movz_d();
5425 GEN_STORE_FTN_FREG(fd
, DT2
);
5429 GEN_LOAD_REG_T0(ft
);
5430 GEN_LOAD_FREG_FTN(DT0
, fs
);
5431 GEN_LOAD_FREG_FTN(DT2
, fd
);
5432 gen_op_float_movn_d();
5433 GEN_STORE_FTN_FREG(fd
, DT2
);
5437 check_cp1_64bitmode(ctx
);
5438 GEN_LOAD_FREG_FTN(DT0
, fs
);
5439 gen_op_float_recip_d();
5440 GEN_STORE_FTN_FREG(fd
, DT2
);
5444 check_cp1_64bitmode(ctx
);
5445 GEN_LOAD_FREG_FTN(DT0
, fs
);
5446 gen_op_float_rsqrt_d();
5447 GEN_STORE_FTN_FREG(fd
, DT2
);
5451 check_cp1_64bitmode(ctx
);
5452 GEN_LOAD_FREG_FTN(DT0
, fs
);
5453 GEN_LOAD_FREG_FTN(DT2
, ft
);
5454 gen_op_float_recip2_d();
5455 GEN_STORE_FTN_FREG(fd
, DT2
);
5459 check_cp1_64bitmode(ctx
);
5460 GEN_LOAD_FREG_FTN(DT0
, fs
);
5461 gen_op_float_recip1_d();
5462 GEN_STORE_FTN_FREG(fd
, DT2
);
5466 check_cp1_64bitmode(ctx
);
5467 GEN_LOAD_FREG_FTN(DT0
, fs
);
5468 gen_op_float_rsqrt1_d();
5469 GEN_STORE_FTN_FREG(fd
, DT2
);
5473 check_cp1_64bitmode(ctx
);
5474 GEN_LOAD_FREG_FTN(DT0
, fs
);
5475 GEN_LOAD_FREG_FTN(DT2
, ft
);
5476 gen_op_float_rsqrt2_d();
5477 GEN_STORE_FTN_FREG(fd
, DT2
);
5496 GEN_LOAD_FREG_FTN(DT0
, fs
);
5497 GEN_LOAD_FREG_FTN(DT1
, ft
);
5498 if (ctx
->opcode
& (1 << 6)) {
5500 check_cp1_registers(ctx
, fs
| ft
);
5501 gen_cmpabs_d(func
-48, cc
);
5502 opn
= condnames_abs
[func
-48];
5504 check_cp1_registers(ctx
, fs
| ft
);
5505 gen_cmp_d(func
-48, cc
);
5506 opn
= condnames
[func
-48];
5510 check_cp1_registers(ctx
, fs
);
5511 GEN_LOAD_FREG_FTN(DT0
, fs
);
5512 gen_op_float_cvts_d();
5513 GEN_STORE_FTN_FREG(fd
, WT2
);
5517 check_cp1_registers(ctx
, fs
);
5518 GEN_LOAD_FREG_FTN(DT0
, fs
);
5519 gen_op_float_cvtw_d();
5520 GEN_STORE_FTN_FREG(fd
, WT2
);
5524 check_cp1_64bitmode(ctx
);
5525 GEN_LOAD_FREG_FTN(DT0
, fs
);
5526 gen_op_float_cvtl_d();
5527 GEN_STORE_FTN_FREG(fd
, DT2
);
5531 GEN_LOAD_FREG_FTN(WT0
, fs
);
5532 gen_op_float_cvts_w();
5533 GEN_STORE_FTN_FREG(fd
, WT2
);
5537 check_cp1_registers(ctx
, fd
);
5538 GEN_LOAD_FREG_FTN(WT0
, fs
);
5539 gen_op_float_cvtd_w();
5540 GEN_STORE_FTN_FREG(fd
, DT2
);
5544 check_cp1_64bitmode(ctx
);
5545 GEN_LOAD_FREG_FTN(DT0
, fs
);
5546 gen_op_float_cvts_l();
5547 GEN_STORE_FTN_FREG(fd
, WT2
);
5551 check_cp1_64bitmode(ctx
);
5552 GEN_LOAD_FREG_FTN(DT0
, fs
);
5553 gen_op_float_cvtd_l();
5554 GEN_STORE_FTN_FREG(fd
, DT2
);
5558 check_cp1_64bitmode(ctx
);
5559 GEN_LOAD_FREG_FTN(WT0
, fs
);
5560 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5561 gen_op_float_cvtps_pw();
5562 GEN_STORE_FTN_FREG(fd
, WT2
);
5563 GEN_STORE_FTN_FREG(fd
, WTH2
);
5567 check_cp1_64bitmode(ctx
);
5568 GEN_LOAD_FREG_FTN(WT0
, fs
);
5569 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5570 GEN_LOAD_FREG_FTN(WT1
, ft
);
5571 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5572 gen_op_float_add_ps();
5573 GEN_STORE_FTN_FREG(fd
, WT2
);
5574 GEN_STORE_FTN_FREG(fd
, WTH2
);
5578 check_cp1_64bitmode(ctx
);
5579 GEN_LOAD_FREG_FTN(WT0
, fs
);
5580 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5581 GEN_LOAD_FREG_FTN(WT1
, ft
);
5582 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5583 gen_op_float_sub_ps();
5584 GEN_STORE_FTN_FREG(fd
, WT2
);
5585 GEN_STORE_FTN_FREG(fd
, WTH2
);
5589 check_cp1_64bitmode(ctx
);
5590 GEN_LOAD_FREG_FTN(WT0
, fs
);
5591 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5592 GEN_LOAD_FREG_FTN(WT1
, ft
);
5593 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5594 gen_op_float_mul_ps();
5595 GEN_STORE_FTN_FREG(fd
, WT2
);
5596 GEN_STORE_FTN_FREG(fd
, WTH2
);
5600 check_cp1_64bitmode(ctx
);
5601 GEN_LOAD_FREG_FTN(WT0
, fs
);
5602 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5603 gen_op_float_abs_ps();
5604 GEN_STORE_FTN_FREG(fd
, WT2
);
5605 GEN_STORE_FTN_FREG(fd
, WTH2
);
5609 check_cp1_64bitmode(ctx
);
5610 GEN_LOAD_FREG_FTN(WT0
, fs
);
5611 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5612 gen_op_float_mov_ps();
5613 GEN_STORE_FTN_FREG(fd
, WT2
);
5614 GEN_STORE_FTN_FREG(fd
, WTH2
);
5618 check_cp1_64bitmode(ctx
);
5619 GEN_LOAD_FREG_FTN(WT0
, fs
);
5620 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5621 gen_op_float_chs_ps();
5622 GEN_STORE_FTN_FREG(fd
, WT2
);
5623 GEN_STORE_FTN_FREG(fd
, WTH2
);
5627 check_cp1_64bitmode(ctx
);
5628 GEN_LOAD_REG_T0(ft
);
5629 GEN_LOAD_FREG_FTN(WT0
, fs
);
5630 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5631 GEN_LOAD_FREG_FTN(WT2
, fd
);
5632 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5633 gen_movcf_ps(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5634 GEN_STORE_FTN_FREG(fd
, WT2
);
5635 GEN_STORE_FTN_FREG(fd
, WTH2
);
5639 check_cp1_64bitmode(ctx
);
5640 GEN_LOAD_REG_T0(ft
);
5641 GEN_LOAD_FREG_FTN(WT0
, fs
);
5642 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5643 GEN_LOAD_FREG_FTN(WT2
, fd
);
5644 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5645 gen_op_float_movz_ps();
5646 GEN_STORE_FTN_FREG(fd
, WT2
);
5647 GEN_STORE_FTN_FREG(fd
, WTH2
);
5651 check_cp1_64bitmode(ctx
);
5652 GEN_LOAD_REG_T0(ft
);
5653 GEN_LOAD_FREG_FTN(WT0
, fs
);
5654 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5655 GEN_LOAD_FREG_FTN(WT2
, fd
);
5656 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5657 gen_op_float_movn_ps();
5658 GEN_STORE_FTN_FREG(fd
, WT2
);
5659 GEN_STORE_FTN_FREG(fd
, WTH2
);
5663 check_cp1_64bitmode(ctx
);
5664 GEN_LOAD_FREG_FTN(WT0
, ft
);
5665 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5666 GEN_LOAD_FREG_FTN(WT1
, fs
);
5667 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5668 gen_op_float_addr_ps();
5669 GEN_STORE_FTN_FREG(fd
, WT2
);
5670 GEN_STORE_FTN_FREG(fd
, WTH2
);
5674 check_cp1_64bitmode(ctx
);
5675 GEN_LOAD_FREG_FTN(WT0
, ft
);
5676 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5677 GEN_LOAD_FREG_FTN(WT1
, fs
);
5678 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5679 gen_op_float_mulr_ps();
5680 GEN_STORE_FTN_FREG(fd
, WT2
);
5681 GEN_STORE_FTN_FREG(fd
, WTH2
);
5685 check_cp1_64bitmode(ctx
);
5686 GEN_LOAD_FREG_FTN(WT0
, fs
);
5687 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5688 GEN_LOAD_FREG_FTN(WT2
, fd
);
5689 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5690 gen_op_float_recip2_ps();
5691 GEN_STORE_FTN_FREG(fd
, WT2
);
5692 GEN_STORE_FTN_FREG(fd
, WTH2
);
5696 check_cp1_64bitmode(ctx
);
5697 GEN_LOAD_FREG_FTN(WT0
, fs
);
5698 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5699 gen_op_float_recip1_ps();
5700 GEN_STORE_FTN_FREG(fd
, WT2
);
5701 GEN_STORE_FTN_FREG(fd
, WTH2
);
5705 check_cp1_64bitmode(ctx
);
5706 GEN_LOAD_FREG_FTN(WT0
, fs
);
5707 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5708 gen_op_float_rsqrt1_ps();
5709 GEN_STORE_FTN_FREG(fd
, WT2
);
5710 GEN_STORE_FTN_FREG(fd
, WTH2
);
5714 check_cp1_64bitmode(ctx
);
5715 GEN_LOAD_FREG_FTN(WT0
, fs
);
5716 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5717 GEN_LOAD_FREG_FTN(WT2
, ft
);
5718 GEN_LOAD_FREG_FTN(WTH2
, ft
);
5719 gen_op_float_rsqrt2_ps();
5720 GEN_STORE_FTN_FREG(fd
, WT2
);
5721 GEN_STORE_FTN_FREG(fd
, WTH2
);
5725 check_cp1_64bitmode(ctx
);
5726 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5727 gen_op_float_cvts_pu();
5728 GEN_STORE_FTN_FREG(fd
, WT2
);
5732 check_cp1_64bitmode(ctx
);
5733 GEN_LOAD_FREG_FTN(WT0
, fs
);
5734 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5735 gen_op_float_cvtpw_ps();
5736 GEN_STORE_FTN_FREG(fd
, WT2
);
5737 GEN_STORE_FTN_FREG(fd
, WTH2
);
5741 check_cp1_64bitmode(ctx
);
5742 GEN_LOAD_FREG_FTN(WT0
, fs
);
5743 gen_op_float_cvts_pl();
5744 GEN_STORE_FTN_FREG(fd
, WT2
);
5748 check_cp1_64bitmode(ctx
);
5749 GEN_LOAD_FREG_FTN(WT0
, fs
);
5750 GEN_LOAD_FREG_FTN(WT1
, ft
);
5751 gen_op_float_pll_ps();
5752 GEN_STORE_FTN_FREG(fd
, DT2
);
5756 check_cp1_64bitmode(ctx
);
5757 GEN_LOAD_FREG_FTN(WT0
, fs
);
5758 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5759 gen_op_float_plu_ps();
5760 GEN_STORE_FTN_FREG(fd
, DT2
);
5764 check_cp1_64bitmode(ctx
);
5765 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5766 GEN_LOAD_FREG_FTN(WT1
, ft
);
5767 gen_op_float_pul_ps();
5768 GEN_STORE_FTN_FREG(fd
, DT2
);
5772 check_cp1_64bitmode(ctx
);
5773 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5774 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5775 gen_op_float_puu_ps();
5776 GEN_STORE_FTN_FREG(fd
, DT2
);
5795 check_cp1_64bitmode(ctx
);
5796 GEN_LOAD_FREG_FTN(WT0
, fs
);
5797 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5798 GEN_LOAD_FREG_FTN(WT1
, ft
);
5799 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5800 if (ctx
->opcode
& (1 << 6)) {
5801 gen_cmpabs_ps(func
-48, cc
);
5802 opn
= condnames_abs
[func
-48];
5804 gen_cmp_ps(func
-48, cc
);
5805 opn
= condnames
[func
-48];
5810 generate_exception (ctx
, EXCP_RI
);
5815 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
5818 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
5821 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
5826 /* Coprocessor 3 (FPU) */
5827 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
5828 int fd
, int fs
, int base
, int index
)
5830 const char *opn
= "extended float load/store";
5837 GEN_LOAD_REG_T0(index
);
5838 } else if (index
== 0) {
5839 GEN_LOAD_REG_T0(base
);
5841 GEN_LOAD_REG_T0(base
);
5842 GEN_LOAD_REG_T1(index
);
5845 /* Don't do NOP if destination is zero: we must perform the actual
5851 GEN_STORE_FTN_FREG(fd
, WT0
);
5856 check_cp1_registers(ctx
, fd
);
5858 GEN_STORE_FTN_FREG(fd
, DT0
);
5862 check_cp1_64bitmode(ctx
);
5864 GEN_STORE_FTN_FREG(fd
, DT0
);
5869 GEN_LOAD_FREG_FTN(WT0
, fs
);
5876 check_cp1_registers(ctx
, fs
);
5877 GEN_LOAD_FREG_FTN(DT0
, fs
);
5883 check_cp1_64bitmode(ctx
);
5884 GEN_LOAD_FREG_FTN(DT0
, fs
);
5891 generate_exception(ctx
, EXCP_RI
);
5894 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
5895 regnames
[index
], regnames
[base
]);
5898 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
5899 int fd
, int fr
, int fs
, int ft
)
5901 const char *opn
= "flt3_arith";
5905 check_cp1_64bitmode(ctx
);
5906 GEN_LOAD_REG_T0(fr
);
5907 GEN_LOAD_FREG_FTN(DT0
, fs
);
5908 GEN_LOAD_FREG_FTN(DT1
, ft
);
5909 gen_op_float_alnv_ps();
5910 GEN_STORE_FTN_FREG(fd
, DT2
);
5915 GEN_LOAD_FREG_FTN(WT0
, fs
);
5916 GEN_LOAD_FREG_FTN(WT1
, ft
);
5917 GEN_LOAD_FREG_FTN(WT2
, fr
);
5918 gen_op_float_muladd_s();
5919 GEN_STORE_FTN_FREG(fd
, WT2
);
5924 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
5925 GEN_LOAD_FREG_FTN(DT0
, fs
);
5926 GEN_LOAD_FREG_FTN(DT1
, ft
);
5927 GEN_LOAD_FREG_FTN(DT2
, fr
);
5928 gen_op_float_muladd_d();
5929 GEN_STORE_FTN_FREG(fd
, DT2
);
5933 check_cp1_64bitmode(ctx
);
5934 GEN_LOAD_FREG_FTN(WT0
, fs
);
5935 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5936 GEN_LOAD_FREG_FTN(WT1
, ft
);
5937 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5938 GEN_LOAD_FREG_FTN(WT2
, fr
);
5939 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5940 gen_op_float_muladd_ps();
5941 GEN_STORE_FTN_FREG(fd
, WT2
);
5942 GEN_STORE_FTN_FREG(fd
, WTH2
);
5947 GEN_LOAD_FREG_FTN(WT0
, fs
);
5948 GEN_LOAD_FREG_FTN(WT1
, ft
);
5949 GEN_LOAD_FREG_FTN(WT2
, fr
);
5950 gen_op_float_mulsub_s();
5951 GEN_STORE_FTN_FREG(fd
, WT2
);
5956 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
5957 GEN_LOAD_FREG_FTN(DT0
, fs
);
5958 GEN_LOAD_FREG_FTN(DT1
, ft
);
5959 GEN_LOAD_FREG_FTN(DT2
, fr
);
5960 gen_op_float_mulsub_d();
5961 GEN_STORE_FTN_FREG(fd
, DT2
);
5965 check_cp1_64bitmode(ctx
);
5966 GEN_LOAD_FREG_FTN(WT0
, fs
);
5967 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5968 GEN_LOAD_FREG_FTN(WT1
, ft
);
5969 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5970 GEN_LOAD_FREG_FTN(WT2
, fr
);
5971 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5972 gen_op_float_mulsub_ps();
5973 GEN_STORE_FTN_FREG(fd
, WT2
);
5974 GEN_STORE_FTN_FREG(fd
, WTH2
);
5979 GEN_LOAD_FREG_FTN(WT0
, fs
);
5980 GEN_LOAD_FREG_FTN(WT1
, ft
);
5981 GEN_LOAD_FREG_FTN(WT2
, fr
);
5982 gen_op_float_nmuladd_s();
5983 GEN_STORE_FTN_FREG(fd
, WT2
);
5988 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
5989 GEN_LOAD_FREG_FTN(DT0
, fs
);
5990 GEN_LOAD_FREG_FTN(DT1
, ft
);
5991 GEN_LOAD_FREG_FTN(DT2
, fr
);
5992 gen_op_float_nmuladd_d();
5993 GEN_STORE_FTN_FREG(fd
, DT2
);
5997 check_cp1_64bitmode(ctx
);
5998 GEN_LOAD_FREG_FTN(WT0
, fs
);
5999 GEN_LOAD_FREG_FTN(WTH0
, fs
);
6000 GEN_LOAD_FREG_FTN(WT1
, ft
);
6001 GEN_LOAD_FREG_FTN(WTH1
, ft
);
6002 GEN_LOAD_FREG_FTN(WT2
, fr
);
6003 GEN_LOAD_FREG_FTN(WTH2
, fr
);
6004 gen_op_float_nmuladd_ps();
6005 GEN_STORE_FTN_FREG(fd
, WT2
);
6006 GEN_STORE_FTN_FREG(fd
, WTH2
);
6011 GEN_LOAD_FREG_FTN(WT0
, fs
);
6012 GEN_LOAD_FREG_FTN(WT1
, ft
);
6013 GEN_LOAD_FREG_FTN(WT2
, fr
);
6014 gen_op_float_nmulsub_s();
6015 GEN_STORE_FTN_FREG(fd
, WT2
);
6020 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
6021 GEN_LOAD_FREG_FTN(DT0
, fs
);
6022 GEN_LOAD_FREG_FTN(DT1
, ft
);
6023 GEN_LOAD_FREG_FTN(DT2
, fr
);
6024 gen_op_float_nmulsub_d();
6025 GEN_STORE_FTN_FREG(fd
, DT2
);
6029 check_cp1_64bitmode(ctx
);
6030 GEN_LOAD_FREG_FTN(WT0
, fs
);
6031 GEN_LOAD_FREG_FTN(WTH0
, fs
);
6032 GEN_LOAD_FREG_FTN(WT1
, ft
);
6033 GEN_LOAD_FREG_FTN(WTH1
, ft
);
6034 GEN_LOAD_FREG_FTN(WT2
, fr
);
6035 GEN_LOAD_FREG_FTN(WTH2
, fr
);
6036 gen_op_float_nmulsub_ps();
6037 GEN_STORE_FTN_FREG(fd
, WT2
);
6038 GEN_STORE_FTN_FREG(fd
, WTH2
);
6043 generate_exception (ctx
, EXCP_RI
);
6046 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
6047 fregnames
[fs
], fregnames
[ft
]);
6050 /* ISA extensions (ASEs) */
6051 /* MIPS16 extension to MIPS32 */
6052 /* SmartMIPS extension to MIPS32 */
6054 #if defined(TARGET_MIPS64)
6056 /* MDMX extension to MIPS64 */
6060 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
6064 uint32_t op
, op1
, op2
;
6067 /* make sure instructions are on a word boundary */
6068 if (ctx
->pc
& 0x3) {
6069 env
->CP0_BadVAddr
= ctx
->pc
;
6070 generate_exception(ctx
, EXCP_AdEL
);
6074 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
6076 /* Handle blikely not taken case */
6077 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
6078 l1
= gen_new_label();
6080 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
6081 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
6084 op
= MASK_OP_MAJOR(ctx
->opcode
);
6085 rs
= (ctx
->opcode
>> 21) & 0x1f;
6086 rt
= (ctx
->opcode
>> 16) & 0x1f;
6087 rd
= (ctx
->opcode
>> 11) & 0x1f;
6088 sa
= (ctx
->opcode
>> 6) & 0x1f;
6089 imm
= (int16_t)ctx
->opcode
;
6092 op1
= MASK_SPECIAL(ctx
->opcode
);
6094 case OPC_SLL
: /* Arithmetic with immediate */
6095 case OPC_SRL
... OPC_SRA
:
6096 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
6098 case OPC_MOVZ
... OPC_MOVN
:
6099 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6100 case OPC_SLLV
: /* Arithmetic */
6101 case OPC_SRLV
... OPC_SRAV
:
6102 case OPC_ADD
... OPC_NOR
:
6103 case OPC_SLT
... OPC_SLTU
:
6104 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6106 case OPC_MULT
... OPC_DIVU
:
6108 check_insn(env
, ctx
, INSN_VR54XX
);
6109 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
6110 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
6112 gen_muldiv(ctx
, op1
, rs
, rt
);
6114 case OPC_JR
... OPC_JALR
:
6115 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
6117 case OPC_TGE
... OPC_TEQ
: /* Traps */
6119 gen_trap(ctx
, op1
, rs
, rt
, -1);
6121 case OPC_MFHI
: /* Move from HI/LO */
6123 gen_HILO(ctx
, op1
, rd
);
6126 case OPC_MTLO
: /* Move to HI/LO */
6127 gen_HILO(ctx
, op1
, rs
);
6129 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
6130 #ifdef MIPS_STRICT_STANDARD
6131 MIPS_INVAL("PMON / selsl");
6132 generate_exception(ctx
, EXCP_RI
);
6138 generate_exception(ctx
, EXCP_SYSCALL
);
6141 generate_exception(ctx
, EXCP_BREAK
);
6144 #ifdef MIPS_STRICT_STANDARD
6146 generate_exception(ctx
, EXCP_RI
);
6148 /* Implemented as RI exception for now. */
6149 MIPS_INVAL("spim (unofficial)");
6150 generate_exception(ctx
, EXCP_RI
);
6158 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6159 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6160 save_cpu_state(ctx
, 1);
6161 check_cp1_enabled(ctx
);
6162 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
6163 (ctx
->opcode
>> 16) & 1);
6165 generate_exception_err(ctx
, EXCP_CpU
, 1);
6169 #if defined(TARGET_MIPS64)
6170 /* MIPS64 specific opcodes */
6172 case OPC_DSRL
... OPC_DSRA
:
6174 case OPC_DSRL32
... OPC_DSRA32
:
6175 check_insn(env
, ctx
, ISA_MIPS3
);
6177 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
6180 case OPC_DSRLV
... OPC_DSRAV
:
6181 case OPC_DADD
... OPC_DSUBU
:
6182 check_insn(env
, ctx
, ISA_MIPS3
);
6184 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6186 case OPC_DMULT
... OPC_DDIVU
:
6187 check_insn(env
, ctx
, ISA_MIPS3
);
6189 gen_muldiv(ctx
, op1
, rs
, rt
);
6192 default: /* Invalid */
6193 MIPS_INVAL("special");
6194 generate_exception(ctx
, EXCP_RI
);
6199 op1
= MASK_SPECIAL2(ctx
->opcode
);
6201 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
6202 case OPC_MSUB
... OPC_MSUBU
:
6203 check_insn(env
, ctx
, ISA_MIPS32
);
6204 gen_muldiv(ctx
, op1
, rs
, rt
);
6207 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6209 case OPC_CLZ
... OPC_CLO
:
6210 check_insn(env
, ctx
, ISA_MIPS32
);
6211 gen_cl(ctx
, op1
, rd
, rs
);
6214 /* XXX: not clear which exception should be raised
6215 * when in debug mode...
6217 check_insn(env
, ctx
, ISA_MIPS32
);
6218 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
6219 generate_exception(ctx
, EXCP_DBp
);
6221 generate_exception(ctx
, EXCP_DBp
);
6225 #if defined(TARGET_MIPS64)
6226 case OPC_DCLZ
... OPC_DCLO
:
6227 check_insn(env
, ctx
, ISA_MIPS64
);
6229 gen_cl(ctx
, op1
, rd
, rs
);
6232 default: /* Invalid */
6233 MIPS_INVAL("special2");
6234 generate_exception(ctx
, EXCP_RI
);
6239 op1
= MASK_SPECIAL3(ctx
->opcode
);
6243 check_insn(env
, ctx
, ISA_MIPS32R2
);
6244 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6247 check_insn(env
, ctx
, ISA_MIPS32R2
);
6248 op2
= MASK_BSHFL(ctx
->opcode
);
6251 GEN_LOAD_REG_T1(rt
);
6255 GEN_LOAD_REG_T1(rt
);
6259 GEN_LOAD_REG_T1(rt
);
6262 default: /* Invalid */
6263 MIPS_INVAL("bshfl");
6264 generate_exception(ctx
, EXCP_RI
);
6267 GEN_STORE_T0_REG(rd
);
6270 check_insn(env
, ctx
, ISA_MIPS32R2
);
6273 save_cpu_state(ctx
, 1);
6274 gen_op_rdhwr_cpunum();
6277 save_cpu_state(ctx
, 1);
6278 gen_op_rdhwr_synci_step();
6281 save_cpu_state(ctx
, 1);
6285 save_cpu_state(ctx
, 1);
6286 gen_op_rdhwr_ccres();
6289 #if defined (CONFIG_USER_ONLY)
6293 default: /* Invalid */
6294 MIPS_INVAL("rdhwr");
6295 generate_exception(ctx
, EXCP_RI
);
6298 GEN_STORE_T0_REG(rt
);
6301 check_insn(env
, ctx
, ASE_MT
);
6302 GEN_LOAD_REG_T0(rt
);
6303 GEN_LOAD_REG_T1(rs
);
6307 check_insn(env
, ctx
, ASE_MT
);
6308 GEN_LOAD_REG_T0(rs
);
6310 GEN_STORE_T0_REG(rd
);
6312 #if defined(TARGET_MIPS64)
6313 case OPC_DEXTM
... OPC_DEXT
:
6314 case OPC_DINSM
... OPC_DINS
:
6315 check_insn(env
, ctx
, ISA_MIPS64R2
);
6317 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6320 check_insn(env
, ctx
, ISA_MIPS64R2
);
6322 op2
= MASK_DBSHFL(ctx
->opcode
);
6325 GEN_LOAD_REG_T1(rt
);
6329 GEN_LOAD_REG_T1(rt
);
6332 default: /* Invalid */
6333 MIPS_INVAL("dbshfl");
6334 generate_exception(ctx
, EXCP_RI
);
6337 GEN_STORE_T0_REG(rd
);
6340 default: /* Invalid */
6341 MIPS_INVAL("special3");
6342 generate_exception(ctx
, EXCP_RI
);
6347 op1
= MASK_REGIMM(ctx
->opcode
);
6349 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
6350 case OPC_BLTZAL
... OPC_BGEZALL
:
6351 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
6353 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
6355 gen_trap(ctx
, op1
, rs
, -1, imm
);
6358 check_insn(env
, ctx
, ISA_MIPS32R2
);
6361 default: /* Invalid */
6362 MIPS_INVAL("regimm");
6363 generate_exception(ctx
, EXCP_RI
);
6368 check_cp0_enabled(ctx
);
6369 op1
= MASK_CP0(ctx
->opcode
);
6375 #if defined(TARGET_MIPS64)
6379 gen_cp0(env
, ctx
, op1
, rt
, rd
);
6381 case OPC_C0_FIRST
... OPC_C0_LAST
:
6382 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
6385 op2
= MASK_MFMC0(ctx
->opcode
);
6388 check_insn(env
, ctx
, ASE_MT
);
6392 check_insn(env
, ctx
, ASE_MT
);
6396 check_insn(env
, ctx
, ASE_MT
);
6400 check_insn(env
, ctx
, ASE_MT
);
6404 check_insn(env
, ctx
, ISA_MIPS32R2
);
6405 save_cpu_state(ctx
, 1);
6407 /* Stop translation as we may have switched the execution mode */
6408 ctx
->bstate
= BS_STOP
;
6411 check_insn(env
, ctx
, ISA_MIPS32R2
);
6412 save_cpu_state(ctx
, 1);
6414 /* Stop translation as we may have switched the execution mode */
6415 ctx
->bstate
= BS_STOP
;
6417 default: /* Invalid */
6418 MIPS_INVAL("mfmc0");
6419 generate_exception(ctx
, EXCP_RI
);
6422 GEN_STORE_T0_REG(rt
);
6425 check_insn(env
, ctx
, ISA_MIPS32R2
);
6426 GEN_LOAD_SRSREG_TN(T0
, rt
);
6427 GEN_STORE_T0_REG(rd
);
6430 check_insn(env
, ctx
, ISA_MIPS32R2
);
6431 GEN_LOAD_REG_T0(rt
);
6432 GEN_STORE_TN_SRSREG(rd
, T0
);
6436 generate_exception(ctx
, EXCP_RI
);
6440 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
6441 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
6443 case OPC_J
... OPC_JAL
: /* Jump */
6444 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
6445 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
6447 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
6448 case OPC_BEQL
... OPC_BGTZL
:
6449 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
6451 case OPC_LB
... OPC_LWR
: /* Load and stores */
6452 case OPC_SB
... OPC_SW
:
6456 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6459 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
6463 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6467 /* Floating point (COP1). */
6472 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6473 save_cpu_state(ctx
, 1);
6474 check_cp1_enabled(ctx
);
6475 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
6477 generate_exception_err(ctx
, EXCP_CpU
, 1);
6482 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6483 save_cpu_state(ctx
, 1);
6484 check_cp1_enabled(ctx
);
6485 op1
= MASK_CP1(ctx
->opcode
);
6489 check_insn(env
, ctx
, ISA_MIPS32R2
);
6494 gen_cp1(ctx
, op1
, rt
, rd
);
6496 #if defined(TARGET_MIPS64)
6499 check_insn(env
, ctx
, ISA_MIPS3
);
6500 gen_cp1(ctx
, op1
, rt
, rd
);
6506 check_insn(env
, ctx
, ASE_MIPS3D
);
6509 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
6510 (rt
>> 2) & 0x7, imm
<< 2);
6517 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
6522 generate_exception (ctx
, EXCP_RI
);
6526 generate_exception_err(ctx
, EXCP_CpU
, 1);
6536 /* COP2: Not implemented. */
6537 generate_exception_err(ctx
, EXCP_CpU
, 2);
6541 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6542 save_cpu_state(ctx
, 1);
6543 check_cp1_enabled(ctx
);
6544 op1
= MASK_CP3(ctx
->opcode
);
6552 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
6570 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
6574 generate_exception (ctx
, EXCP_RI
);
6578 generate_exception_err(ctx
, EXCP_CpU
, 1);
6582 #if defined(TARGET_MIPS64)
6583 /* MIPS64 opcodes */
6585 case OPC_LDL
... OPC_LDR
:
6586 case OPC_SDL
... OPC_SDR
:
6591 check_insn(env
, ctx
, ISA_MIPS3
);
6593 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6595 case OPC_DADDI
... OPC_DADDIU
:
6596 check_insn(env
, ctx
, ISA_MIPS3
);
6598 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
6602 check_insn(env
, ctx
, ASE_MIPS16
);
6603 /* MIPS16: Not implemented. */
6605 check_insn(env
, ctx
, ASE_MDMX
);
6606 /* MDMX: Not implemented. */
6607 default: /* Invalid */
6608 MIPS_INVAL("major opcode");
6609 generate_exception(ctx
, EXCP_RI
);
6612 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
6613 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
6614 /* Branches completion */
6615 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
6616 ctx
->bstate
= BS_BRANCH
;
6617 save_cpu_state(ctx
, 0);
6620 /* unconditional branch */
6621 MIPS_DEBUG("unconditional branch");
6622 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6625 /* blikely taken case */
6626 MIPS_DEBUG("blikely branch taken");
6627 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6630 /* Conditional branch */
6631 MIPS_DEBUG("conditional branch");
6634 l1
= gen_new_label();
6636 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
6638 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6642 /* unconditional branch to register */
6643 MIPS_DEBUG("branch to register");
6649 MIPS_DEBUG("unknown branch");
6655 static always_inline
int
6656 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
6660 target_ulong pc_start
;
6661 uint16_t *gen_opc_end
;
6664 if (search_pc
&& loglevel
)
6665 fprintf (logfile
, "search pc %d\n", search_pc
);
6668 gen_opc_ptr
= gen_opc_buf
;
6669 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6670 gen_opparam_ptr
= gen_opparam_buf
;
6675 ctx
.bstate
= BS_NONE
;
6676 /* Restore delay slot state from the tb context. */
6677 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
6678 restore_cpu_state(env
, &ctx
);
6679 #if defined(CONFIG_USER_ONLY)
6680 ctx
.mem_idx
= MIPS_HFLAG_UM
;
6682 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
6685 if (loglevel
& CPU_LOG_TB_CPU
) {
6686 fprintf(logfile
, "------------------------------------------------\n");
6687 /* FIXME: This may print out stale hflags from env... */
6688 cpu_dump_state(env
, logfile
, fprintf
, 0);
6691 #ifdef MIPS_DEBUG_DISAS
6692 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6693 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
6694 tb
, ctx
.mem_idx
, ctx
.hflags
);
6696 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6697 if (env
->nb_breakpoints
> 0) {
6698 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
6699 if (env
->breakpoints
[j
] == ctx
.pc
) {
6700 save_cpu_state(&ctx
, 1);
6701 ctx
.bstate
= BS_BRANCH
;
6703 /* Include the breakpoint location or the tb won't
6704 * be flushed when it must be. */
6706 goto done_generating
;
6712 j
= gen_opc_ptr
- gen_opc_buf
;
6716 gen_opc_instr_start
[lj
++] = 0;
6718 gen_opc_pc
[lj
] = ctx
.pc
;
6719 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
6720 gen_opc_instr_start
[lj
] = 1;
6722 ctx
.opcode
= ldl_code(ctx
.pc
);
6723 decode_opc(env
, &ctx
);
6726 if (env
->singlestep_enabled
)
6729 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
6732 #if defined (MIPS_SINGLE_STEP)
6736 if (env
->singlestep_enabled
) {
6737 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
6740 switch (ctx
.bstate
) {
6742 gen_op_interrupt_restart();
6743 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6746 save_cpu_state(&ctx
, 0);
6747 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6750 gen_op_interrupt_restart();
6760 ctx
.last_T0_store
= NULL
;
6761 *gen_opc_ptr
= INDEX_op_end
;
6763 j
= gen_opc_ptr
- gen_opc_buf
;
6766 gen_opc_instr_start
[lj
++] = 0;
6768 tb
->size
= ctx
.pc
- pc_start
;
6771 #if defined MIPS_DEBUG_DISAS
6772 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6773 fprintf(logfile
, "\n");
6775 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6776 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6777 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
6778 fprintf(logfile
, "\n");
6780 if (loglevel
& CPU_LOG_TB_OP
) {
6781 fprintf(logfile
, "OP:\n");
6782 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6783 fprintf(logfile
, "\n");
6785 if (loglevel
& CPU_LOG_TB_CPU
) {
6786 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
6793 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6795 return gen_intermediate_code_internal(env
, tb
, 0);
6798 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6800 return gen_intermediate_code_internal(env
, tb
, 1);
6803 void fpu_dump_state(CPUState
*env
, FILE *f
,
6804 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6808 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
6810 #define printfpr(fp) \
6813 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
6814 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
6815 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
6818 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
6819 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
6820 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
6821 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
6822 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
6827 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
6828 env
->fpu
->fcr0
, env
->fpu
->fcr31
, is_fpu64
, env
->fpu
->fp_status
,
6829 get_float_exception_flags(&env
->fpu
->fp_status
));
6830 fpu_fprintf(f
, "FT0: "); printfpr(&env
->fpu
->ft0
);
6831 fpu_fprintf(f
, "FT1: "); printfpr(&env
->fpu
->ft1
);
6832 fpu_fprintf(f
, "FT2: "); printfpr(&env
->fpu
->ft2
);
6833 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
6834 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
6835 printfpr(&env
->fpu
->fpr
[i
]);
6841 void dump_fpu (CPUState
*env
)
6844 fprintf(logfile
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6845 env
->PC
[env
->current_tc
], env
->HI
[0][env
->current_tc
], env
->LO
[0][env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
6846 fpu_dump_state(env
, logfile
, fprintf
, 0);
6850 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6851 /* Debug help: The architecture requires 32bit code to maintain proper
6852 sign-extened values on 64bit machines. */
6854 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
6856 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
6857 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6862 if (!SIGN_EXT_P(env
->PC
[env
->current_tc
]))
6863 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->PC
[env
->current_tc
]);
6864 if (!SIGN_EXT_P(env
->HI
[0][env
->current_tc
]))
6865 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->HI
[0][env
->current_tc
]);
6866 if (!SIGN_EXT_P(env
->LO
[0][env
->current_tc
]))
6867 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->LO
[0][env
->current_tc
]);
6868 if (!SIGN_EXT_P(env
->btarget
))
6869 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
6871 for (i
= 0; i
< 32; i
++) {
6872 if (!SIGN_EXT_P(env
->gpr
[i
][env
->current_tc
]))
6873 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->gpr
[i
][env
->current_tc
]);
6876 if (!SIGN_EXT_P(env
->CP0_EPC
))
6877 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
6878 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
6879 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
6883 void cpu_dump_state (CPUState
*env
, FILE *f
,
6884 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6889 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6890 env
->PC
[env
->current_tc
], env
->HI
[env
->current_tc
], env
->LO
[env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
6891 for (i
= 0; i
< 32; i
++) {
6893 cpu_fprintf(f
, "GPR%02d:", i
);
6894 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->gpr
[i
][env
->current_tc
]);
6896 cpu_fprintf(f
, "\n");
6899 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
6900 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
6901 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
6902 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
6903 if (env
->hflags
& MIPS_HFLAG_FPU
)
6904 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
6905 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6906 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
6910 #include "translate_init.c"
6912 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
6915 const mips_def_t
*def
;
6917 def
= cpu_mips_find_by_name(cpu_model
);
6920 env
= qemu_mallocz(sizeof(CPUMIPSState
));
6923 env
->cpu_model
= def
;
6926 env
->cpu_model_str
= cpu_model
;
6931 void cpu_reset (CPUMIPSState
*env
)
6933 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
6938 #if !defined(CONFIG_USER_ONLY)
6939 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
6940 /* If the exception was raised from a delay slot,
6941 * come back to the jump. */
6942 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
] - 4;
6944 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
];
6946 env
->PC
[env
->current_tc
] = (int32_t)0xBFC00000;
6948 /* SMP not implemented */
6949 env
->CP0_EBase
= 0x80000000;
6950 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
6951 /* vectored interrupts not implemented, timer on int 7,
6952 no performance counters. */
6953 env
->CP0_IntCtl
= 0xe0000000;
6957 for (i
= 0; i
< 7; i
++) {
6958 env
->CP0_WatchLo
[i
] = 0;
6959 env
->CP0_WatchHi
[i
] = 0x80000000;
6961 env
->CP0_WatchLo
[7] = 0;
6962 env
->CP0_WatchHi
[7] = 0;
6964 /* Count register increments in debug mode, EJTAG version 1 */
6965 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
6967 env
->exception_index
= EXCP_NONE
;
6968 #if defined(CONFIG_USER_ONLY)
6969 env
->hflags
= MIPS_HFLAG_UM
;
6970 env
->user_mode_only
= 1;
6972 env
->hflags
= MIPS_HFLAG_CP0
;
6974 cpu_mips_register(env
, env
->cpu_model
);