hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "isa.h"
  10
  11 /* imported from <linux/pci.h> */
  12 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  13 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  14
  15 /* PCI bus */
  16 extern target_phys_addr_t pci_mem_base;
  17
  18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21
  22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  23 #include "pci_ids.h"
  24
  25 /* QEMU-specific Vendor and Device ID definitions */
  26
  27 /* IBM (0x1014) */
  28 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  29 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  30
  31 /* Hitachi (0x1054) */
  32 #define PCI_VENDOR_ID_HITACHI            0x1054
  33 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  34
  35 /* Apple (0x106b) */
  36 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  40 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  41
  42 /* Realtek (0x10ec) */
  43 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  44
  45 /* Xilinx (0x10ee) */
  46 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  47
  48 /* Marvell (0x11ab) */
  49 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  50
  51 /* QEMU/Bochs VGA (0x1234) */
  52 #define PCI_VENDOR_ID_QEMU               0x1234
  53 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  54
  55 /* VMWare (0x15ad) */
  56 #define PCI_VENDOR_ID_VMWARE             0x15ad
  57 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  58 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  59 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  60 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  61 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  62
  63 /* Intel (0x8086) */
  64 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  65
  66 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  67 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  68 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  69 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  70
  71 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  72 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  73 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  74 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 uint32_t addr, uint32_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, uint32_t val, int len);
  86 typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev,
  87                                       uint32_t address, int len);
  88 typedef int PCICapConfigInitFunc(PCIDevice *pci_dev);
  89
  90 #define PCI_ADDRESS_SPACE_MEM           0x00
  91 #define PCI_ADDRESS_SPACE_IO            0x01
  92 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  93
  94 typedef struct PCIIORegion {
  95     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  96     uint32_t size;
  97     uint8_t type;
  98     PCIMapIORegionFunc *map_func;
  99 } PCIIORegion;
 100
 101 #define PCI_ROM_SLOT 6
 102 #define PCI_NUM_REGIONS 7
 103
 104 /* Declarations from linux/pci_regs.h */
 105 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 106 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 107 #define PCI_COMMAND             0x04    /* 16 bits */
 108 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 109 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 110 #define PCI_STATUS              0x06    /* 16 bits */
 111 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 112 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 113 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 114 #define  PCI_HEADER_TYPE_NORMAL         0
 115 #define  PCI_HEADER_TYPE_BRIDGE         1
 116 #define  PCI_HEADER_TYPE_CARDBUS        2
 117 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 118 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 119 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 120 #define PCI_CAPABILITY_LIST     0x34
 121 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 122 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 123 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 124 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 125
 126 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 127 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 128 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 129
 130 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 131 #define PCI_STATUS_RESERVED1    0x007
 132 #define PCI_STATUS_INT_STATUS   0x008
 133 #define PCI_STATUS_CAPABILITIES 0x010
 134
 135 #ifndef PCI_STATUS_66MHZ
 136 #define PCI_STATUS_66MHZ        0x020
 137 #endif
 138
 139 #define PCI_STATUS_RESERVED2    0x040
 140
 141 #ifndef PCI_STATUS_FAST_BACK
 142 #define PCI_STATUS_FAST_BACK    0x080
 143 #endif
 144
 145 #define PCI_STATUS_DEVSEL       0x600
 146
 147 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 148                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 149                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 150
 151 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 152
 153 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 154 #define PCI_COMMAND_RESERVED    0xf800
 155
 156 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 157
 158 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 159 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 160 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 161 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 162
 163 struct PCIDevice {
 164     DeviceState qdev;
 165     /* PCI config space */
 166     uint8_t config[256];
 167
 168     /* the following fields are read only */
 169     PCIBus *bus;
 170     int devfn;
 171     char name[64];
 172     PCIIORegion io_regions[PCI_NUM_REGIONS];
 173
 174     /* do not access the following fields */
 175     PCIConfigReadFunc *config_read;
 176     PCIConfigWriteFunc *config_write;
 177     PCIUnregisterFunc *unregister;
 178
 179     /* IRQ objects for the INTA-INTD pins.  */
 180     qemu_irq *irq;
 181
 182     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 183     int irq_state[4];
 184
 185     /* Device capability configuration space */
 186     struct {
 187         int supported;
 188         unsigned int start, length;
 189         PCICapConfigReadFunc *config_read;
 190         PCICapConfigWriteFunc *config_write;
 191     } cap;
 192 };
 193
 194 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 195                                int instance_size, int devfn,
 196                                PCIConfigReadFunc *config_read,
 197                                PCIConfigWriteFunc *config_write);
 198 int pci_unregister_device(PCIDevice *pci_dev, int assigned);
 199
 200 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 201                             uint32_t size, int type,
 202                             PCIMapIORegionFunc *map_func);
 203
 204 int pci_enable_capability_support(PCIDevice *pci_dev,
 205                                   uint32_t config_start,
 206                                   PCICapConfigReadFunc *config_read,
 207                                   PCICapConfigWriteFunc *config_write,
 208                                   PCICapConfigInitFunc *config_init);
 209
 210 int pci_map_irq(PCIDevice *pci_dev, int pin);
 211 uint32_t pci_default_read_config(PCIDevice *d,
 212                                  uint32_t address, int len);
 213 void pci_default_write_config(PCIDevice *d,
 214                               uint32_t address, uint32_t val, int len);
 215 void pci_device_save(PCIDevice *s, QEMUFile *f);
 216 int pci_device_load(PCIDevice *s, QEMUFile *f);
 217 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 218                                      uint32_t address, int len);
 219 void pci_default_cap_write_config(PCIDevice *pci_dev,
 220                                   uint32_t address, uint32_t val, int len);
 221 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);
 222
 223 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 224 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 225 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 226                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 227                          qemu_irq *pic, int devfn_min, int nirq);
 228
 229 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 230                   const char *default_model);
 231 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 232 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 233 int pci_bus_num(PCIBus *s);
 234 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 235 PCIBus *pci_find_bus(int bus_num);
 236 PCIDevice *pci_find_device(int bus_num, int slot, int function);
 237
 238 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
 239 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
 240
 241 int pci_parse_host_devaddr(const char *addr, int *busp,
 242                            int *slotp, int *funcp);
 243
 244 void pci_info(Monitor *mon);
 245 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 246                         pci_map_irq_fn map_irq, const char *name);
 247
 248 static inline void
 249 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 250 {
 251     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 252 }
 253
 254 static inline void
 255 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 256 {
 257     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 258 }
 259
 260 static inline void
 261 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 262 {
 263     cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
 264 }
 265
 266 typedef void (*pci_qdev_initfn)(PCIDevice *dev);
 267 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init);
 268
 269 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 270
 271 /* lsi53c895a.c */
 272 #define LSI_MAX_DEVS 7
 273 void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id);
 274
 275 /* vmware_vga.c */
 276 void pci_vmsvga_init(PCIBus *bus);
 277
 278 /* usb-uhci.c */
 279 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 280 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 281
 282 /* usb-ohci.c */
 283 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 284
 285 /* prep_pci.c */
 286 PCIBus *pci_prep_init(qemu_irq *pic);
 287
 288 /* apb_pci.c */
 289 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 290                      target_phys_addr_t mem_base,
 291                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 292
 293 /* sh_pci.c */
 294 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 295                             qemu_irq *pic, int devfn_min, int nirq);
 296
 297 #endif