hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "pc.h"
  30 #include "qemu-kvm.h"
  31 #include "device-assignment.h"
  32
  33 //#define DEBUG_PCI
  34
  35 struct PCIBus {
  36     BusState qbus;
  37     int bus_num;
  38     int devfn_min;
  39     pci_set_irq_fn set_irq;
  40     pci_map_irq_fn map_irq;
  41     uint32_t config_reg; /* XXX: suppress */
  42     /* low level pic */
  43     SetIRQFunc *low_set_irq;
  44     qemu_irq *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47     PCIBus *next;
  48     /* The bus IRQ state is the logical OR of the connected devices.
  49        Keep a count of the number of devices with raised IRQs.  */
  50     int nirq;
  51     int irq_count[];
  52 };
  53
  54 static void pci_update_mappings(PCIDevice *d);
  55 static void pci_set_irq(void *opaque, int irq_num, int level);
  56
  57 target_phys_addr_t pci_mem_base;
  58 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  59 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  60 static PCIBus *first_bus;
  61
  62 static void pcibus_save(QEMUFile *f, void *opaque)
  63 {
  64     PCIBus *bus = (PCIBus *)opaque;
  65     int i;
  66
  67     qemu_put_be32(f, bus->nirq);
  68     for (i = 0; i < bus->nirq; i++)
  69         qemu_put_be32(f, bus->irq_count[i]);
  70 }
  71
  72 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  73 {
  74     PCIBus *bus = (PCIBus *)opaque;
  75     int i, nirq;
  76
  77     if (version_id != 1)
  78         return -EINVAL;
  79
  80     nirq = qemu_get_be32(f);
  81     if (bus->nirq != nirq) {
  82         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  83                 nirq, bus->nirq);
  84         return -EINVAL;
  85     }
  86
  87     for (i = 0; i < nirq; i++)
  88         bus->irq_count[i] = qemu_get_be32(f);
  89
  90     return 0;
  91 }
  92
  93 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
  94                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  95                          qemu_irq *pic, int devfn_min, int nirq)
  96 {
  97     PCIBus *bus;
  98     static int nbus = 0;
  99
 100     bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
 101                                         sizeof(PCIBus) + (nirq * sizeof(int)),
 102                                         parent, name));
 103     bus->set_irq = set_irq;
 104     bus->map_irq = map_irq;
 105     bus->irq_opaque = pic;
 106     bus->devfn_min = devfn_min;
 107     bus->nirq = nirq;
 108     bus->next = first_bus;
 109     first_bus = bus;
 110     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 111     return bus;
 112 }
 113
 114 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 115 {
 116     PCIBus *bus;
 117     bus = qemu_mallocz(sizeof(PCIBus));
 118     bus->map_irq = map_irq;
 119     bus->parent_dev = dev;
 120     bus->next = dev->bus->next;
 121     dev->bus->next = bus;
 122     return bus;
 123 }
 124
 125 int pci_bus_num(PCIBus *s)
 126 {
 127     return s->bus_num;
 128 }
 129
 130 void pci_device_save(PCIDevice *s, QEMUFile *f)
 131 {
 132     int i;
 133
 134     qemu_put_be32(f, 2); /* PCI device version */
 135     qemu_put_buffer(f, s->config, 256);
 136     for (i = 0; i < 4; i++)
 137         qemu_put_be32(f, s->irq_state[i]);
 138 }
 139
 140 int pci_device_load(PCIDevice *s, QEMUFile *f)
 141 {
 142     uint32_t version_id;
 143     int i;
 144
 145     version_id = qemu_get_be32(f);
 146     if (version_id > 2)
 147         return -EINVAL;
 148     qemu_get_buffer(f, s->config, 256);
 149     pci_update_mappings(s);
 150
 151     if (version_id >= 2)
 152         for (i = 0; i < 4; i ++)
 153             s->irq_state[i] = qemu_get_be32(f);
 154
 155     return 0;
 156 }
 157
 158 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 159 {
 160     uint16_t *id;
 161
 162     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 163     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 164     id[1] = cpu_to_le16(pci_default_sub_device_id);
 165     return 0;
 166 }
 167
 168 /*
 169  * Parse pci address in qemu command
 170  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 171  */
 172 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 173 {
 174     const char *p;
 175     char *e;
 176     unsigned long val;
 177     unsigned long dom = 0, bus = 0;
 178     unsigned slot = 0;
 179
 180     p = addr;
 181     val = strtoul(p, &e, 16);
 182     if (e == p)
 183         return -1;
 184     if (*e == ':') {
 185         bus = val;
 186         p = e + 1;
 187         val = strtoul(p, &e, 16);
 188         if (e == p)
 189             return -1;
 190         if (*e == ':') {
 191             dom = bus;
 192             bus = val;
 193             p = e + 1;
 194             val = strtoul(p, &e, 16);
 195             if (e == p)
 196                 return -1;
 197         }
 198     }
 199
 200     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 201         return -1;
 202
 203     slot = val;
 204
 205     if (*e)
 206         return -1;
 207
 208     /* Note: QEMU doesn't implement domains other than 0 */
 209     if (dom != 0 || pci_find_bus(bus) == NULL)
 210         return -1;
 211
 212     *domp = dom;
 213     *busp = bus;
 214     *slotp = slot;
 215     return 0;
 216 }
 217
 218 /*
 219  * Parse device bdf in device assignment command:
 220  *
 221  * -pcidevice host=bus:dev.func
 222  *
 223  * Parse <bus>:<slot>.<func> return -1 on error
 224  */
 225 int pci_parse_host_devaddr(const char *addr, int *busp,
 226                            int *slotp, int *funcp)
 227 {
 228     const char *p;
 229     char *e;
 230     int val;
 231     int bus = 0, slot = 0, func = 0;
 232
 233     p = addr;
 234     val = strtoul(p, &e, 16);
 235     if (e == p)
 236         return -1;
 237     if (*e == ':') {
 238         bus = val;
 239         p = e + 1;
 240         val = strtoul(p, &e, 16);
 241         if (e == p)
 242             return -1;
 243         if (*e == '.') {
 244             slot = val;
 245             p = e + 1;
 246             val = strtoul(p, &e, 16);
 247             if (e == p)
 248                 return -1;
 249             func = val;
 250         } else
 251             return -1;
 252     } else
 253         return -1;
 254
 255     if (bus > 0xff || slot > 0x1f || func > 0x7)
 256         return -1;
 257
 258     if (*e)
 259         return -1;
 260
 261     *busp = bus;
 262     *slotp = slot;
 263     *funcp = func;
 264     return 0;
 265 }
 266
 267 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 268 {
 269     char devaddr[32];
 270
 271     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 272         return -1;
 273
 274     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 275 }
 276
 277 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 278 {
 279     char devaddr[32];
 280
 281     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 282         return -1;
 283
 284     if (!strcmp(devaddr, "auto")) {
 285         *domp = *busp = 0;
 286         *slotp = -1;
 287         /* want to support dom/bus auto-assign at some point */
 288         return 0;
 289     }
 290
 291     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 292 }
 293
 294 /* -1 for devfn means auto assign */
 295 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 296                                          const char *name, int devfn,
 297                                          PCIConfigReadFunc *config_read,
 298                                          PCIConfigWriteFunc *config_write)
 299 {
 300     if (devfn < 0) {
 301         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 302             if (!bus->devices[devfn])
 303                 goto found;
 304         }
 305         return NULL;
 306     found: ;
 307     }
 308     pci_dev->bus = bus;
 309     pci_dev->devfn = devfn;
 310     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 311     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 312     pci_set_default_subsystem_id(pci_dev);
 313
 314     if (!config_read)
 315         config_read = pci_default_read_config;
 316     if (!config_write)
 317         config_write = pci_default_write_config;
 318     pci_dev->config_read = config_read;
 319     pci_dev->config_write = config_write;
 320     bus->devices[devfn] = pci_dev;
 321     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 322     return pci_dev;
 323 }
 324
 325 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 326                                int instance_size, int devfn,
 327                                PCIConfigReadFunc *config_read,
 328                                PCIConfigWriteFunc *config_write)
 329 {
 330     PCIDevice *pci_dev;
 331
 332     pci_dev = qemu_mallocz(instance_size);
 333     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 334                                      config_read, config_write);
 335     return pci_dev;
 336 }
 337 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 338 {
 339     return addr + pci_mem_base;
 340 }
 341
 342 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 343 {
 344     PCIIORegion *r;
 345     int i;
 346
 347     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 348         r = &pci_dev->io_regions[i];
 349         if (!r->size || r->addr == -1)
 350             continue;
 351         if (r->type == PCI_ADDRESS_SPACE_IO) {
 352             isa_unassign_ioport(r->addr, r->size);
 353         } else {
 354             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 355                                                      r->size,
 356                                                      IO_MEM_UNASSIGNED);
 357         }
 358     }
 359 }
 360
 361 int pci_unregister_device(PCIDevice *pci_dev, int assigned)
 362 {
 363     int ret = 0;
 364
 365     if (pci_dev->unregister)
 366         ret = pci_dev->unregister(pci_dev);
 367     if (ret)
 368         return ret;
 369
 370     pci_unregister_io_regions(pci_dev);
 371
 372     qemu_free_irqs(pci_dev->irq);
 373     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 374
 375     if (assigned)
 376         qemu_free(pci_dev);
 377     else
 378         qdev_free(&pci_dev->qdev);
 379     return 0;
 380 }
 381
 382 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 383                             uint32_t size, int type,
 384                             PCIMapIORegionFunc *map_func)
 385 {
 386     PCIIORegion *r;
 387     uint32_t addr;
 388
 389     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 390         return;
 391
 392     if (size & (size-1)) {
 393         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 394                     "type=0x%x, size=0x%x\n", type, size);
 395         exit(1);
 396     }
 397
 398     r = &pci_dev->io_regions[region_num];
 399     r->addr = -1;
 400     r->size = size;
 401     r->type = type;
 402     r->map_func = map_func;
 403     if (region_num == PCI_ROM_SLOT) {
 404         addr = 0x30;
 405     } else {
 406         addr = 0x10 + region_num * 4;
 407     }
 408     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 409 }
 410
 411 static void pci_update_mappings(PCIDevice *d)
 412 {
 413     PCIIORegion *r;
 414     int cmd, i;
 415     uint32_t last_addr, new_addr, config_ofs;
 416
 417     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 418     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 419         r = &d->io_regions[i];
 420         if (i == PCI_ROM_SLOT) {
 421             config_ofs = 0x30;
 422         } else {
 423             config_ofs = 0x10 + i * 4;
 424         }
 425         if (r->size != 0) {
 426             if (r->type & PCI_ADDRESS_SPACE_IO) {
 427                 if (cmd & PCI_COMMAND_IO) {
 428                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 429                                                          config_ofs));
 430                     new_addr = new_addr & ~(r->size - 1);
 431                     last_addr = new_addr + r->size - 1;
 432                     /* NOTE: we have only 64K ioports on PC */
 433                     if (last_addr <= new_addr || new_addr == 0 ||
 434                         last_addr >= 0x10000) {
 435                         new_addr = -1;
 436                     }
 437                 } else {
 438                     new_addr = -1;
 439                 }
 440             } else {
 441                 if (cmd & PCI_COMMAND_MEMORY) {
 442                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 443                                                          config_ofs));
 444                     /* the ROM slot has a specific enable bit */
 445                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 446                         goto no_mem_map;
 447                     new_addr = new_addr & ~(r->size - 1);
 448                     last_addr = new_addr + r->size - 1;
 449                     /* NOTE: we do not support wrapping */
 450                     /* XXX: as we cannot support really dynamic
 451                        mappings, we handle specific values as invalid
 452                        mappings. */
 453                     if (last_addr <= new_addr || new_addr == 0 ||
 454                         last_addr == -1) {
 455                         new_addr = -1;
 456                     }
 457                 } else {
 458                 no_mem_map:
 459                     new_addr = -1;
 460                 }
 461             }
 462             /* now do the real mapping */
 463             if (new_addr != r->addr) {
 464                 if (r->addr != -1) {
 465                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 466                         int class;
 467                         /* NOTE: specific hack for IDE in PC case:
 468                            only one byte must be mapped. */
 469                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 470                         if (class == 0x0101 && r->size == 4) {
 471                             isa_unassign_ioport(r->addr + 2, 1);
 472                         } else {
 473                             isa_unassign_ioport(r->addr, r->size);
 474                         }
 475                     } else {
 476                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 477                                                      r->size,
 478                                                      IO_MEM_UNASSIGNED);
 479                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 480                     }
 481                 }
 482                 r->addr = new_addr;
 483                 if (r->addr != -1) {
 484                     r->map_func(d, i, r->addr, r->size, r->type);
 485                 }
 486             }
 487         }
 488     }
 489 }
 490
 491 static uint32_t pci_read_config(PCIDevice *d,
 492                                 uint32_t address, int len)
 493 {
 494     uint32_t val;
 495
 496     switch(len) {
 497     default:
 498     case 4:
 499         if (address <= 0xfc) {
 500             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 501             break;
 502         }
 503         /* fall through */
 504     case 2:
 505         if (address <= 0xfe) {
 506             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 507             break;
 508         }
 509         /* fall through */
 510     case 1:
 511         val = d->config[address];
 512         break;
 513     }
 514     return val;
 515 }
 516
 517 static void pci_write_config(PCIDevice *pci_dev,
 518                              uint32_t address, uint32_t val, int len)
 519 {
 520     int i;
 521     for (i = 0; i < len; i++) {
 522         pci_dev->config[address + i] = val & 0xff;
 523         val >>= 8;
 524     }
 525 }
 526
 527 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 528 {
 529     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 530             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 531         return 1;
 532     return 0;
 533 }
 534
 535 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 536                                      uint32_t address, int len)
 537 {
 538     return pci_read_config(pci_dev, address, len);
 539 }
 540
 541 void pci_default_cap_write_config(PCIDevice *pci_dev,
 542                                   uint32_t address, uint32_t val, int len)
 543 {
 544     pci_write_config(pci_dev, address, val, len);
 545 }
 546
 547 uint32_t pci_default_read_config(PCIDevice *d,
 548                                  uint32_t address, int len)
 549 {
 550     if (pci_access_cap_config(d, address, len))
 551         return d->cap.config_read(d, address, len);
 552
 553     return pci_read_config(d, address, len);
 554 }
 555
 556 void pci_default_write_config(PCIDevice *d,
 557                               uint32_t address, uint32_t val, int len)
 558 {
 559     int can_write, i;
 560     uint32_t end, addr;
 561
 562     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 563                      (address >= 0x30 && address < 0x34))) {
 564         PCIIORegion *r;
 565         int reg;
 566
 567         if ( address >= 0x30 ) {
 568             reg = PCI_ROM_SLOT;
 569         }else{
 570             reg = (address - 0x10) >> 2;
 571         }
 572         r = &d->io_regions[reg];
 573         if (r->size == 0)
 574             goto default_config;
 575         /* compute the stored value */
 576         if (reg == PCI_ROM_SLOT) {
 577             /* keep ROM enable bit */
 578             val &= (~(r->size - 1)) | 1;
 579         } else {
 580             val &= ~(r->size - 1);
 581             val |= r->type;
 582         }
 583         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 584         pci_update_mappings(d);
 585         return;
 586     }
 587  default_config:
 588     if (pci_access_cap_config(d, address, len)) {
 589         d->cap.config_write(d, address, val, len);
 590         return;
 591     }
 592
 593     /* not efficient, but simple */
 594     addr = address;
 595     for(i = 0; i < len; i++) {
 596         /* default read/write accesses */
 597         switch(d->config[0x0e]) {
 598         case 0x00:
 599         case 0x80:
 600             switch(addr) {
 601             case 0x00:
 602             case 0x01:
 603             case 0x02:
 604             case 0x03:
 605             case 0x06:
 606             case 0x07:
 607             case 0x08:
 608             case 0x09:
 609             case 0x0a:
 610             case 0x0b:
 611             case 0x0e:
 612             case 0x10 ... 0x27: /* base */
 613             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 614             case 0x30 ... 0x33: /* rom */
 615             case 0x3d:
 616                 can_write = 0;
 617                 break;
 618             default:
 619                 can_write = 1;
 620                 break;
 621             }
 622             break;
 623         default:
 624         case 0x01:
 625             switch(addr) {
 626             case 0x00:
 627             case 0x01:
 628             case 0x02:
 629             case 0x03:
 630             case 0x06:
 631             case 0x07:
 632             case 0x08:
 633             case 0x09:
 634             case 0x0a:
 635             case 0x0b:
 636             case 0x0e:
 637             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 638             case 0x38 ... 0x3b: /* rom */
 639             case 0x3d:
 640                 can_write = 0;
 641                 break;
 642             default:
 643                 can_write = 1;
 644                 break;
 645             }
 646             break;
 647         }
 648         if (can_write) {
 649             /* Mask out writes to reserved bits in registers */
 650             switch (addr) {
 651             case 0x05:
 652                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 653                 break;
 654             case 0x06:
 655                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 656                 break;
 657             case 0x07:
 658                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 659                 break;
 660             }
 661             d->config[addr] = val;
 662         }
 663         if (++addr > 0xff)
 664                 break;
 665         val >>= 8;
 666     }
 667
 668 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 669     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel() &&
 670         address >= PIIX_CONFIG_IRQ_ROUTE &&
 671         address < PIIX_CONFIG_IRQ_ROUTE + 4)
 672         assigned_dev_update_irqs();
 673 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 674
 675     end = address + len;
 676     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 677         /* if the command register is modified, we must modify the mappings */
 678         pci_update_mappings(d);
 679     }
 680 }
 681
 682 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 683 {
 684     PCIBus *s = opaque;
 685     PCIDevice *pci_dev;
 686     int config_addr, bus_num;
 687
 688 #if defined(DEBUG_PCI) && 0
 689     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 690            addr, val, len);
 691 #endif
 692     bus_num = (addr >> 16) & 0xff;
 693     while (s && s->bus_num != bus_num)
 694         s = s->next;
 695     if (!s)
 696         return;
 697     pci_dev = s->devices[(addr >> 8) & 0xff];
 698     if (!pci_dev)
 699         return;
 700     config_addr = addr & 0xff;
 701 #if defined(DEBUG_PCI)
 702     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 703            pci_dev->name, config_addr, val, len);
 704 #endif
 705     pci_dev->config_write(pci_dev, config_addr, val, len);
 706 }
 707
 708 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 709 {
 710     PCIBus *s = opaque;
 711     PCIDevice *pci_dev;
 712     int config_addr, bus_num;
 713     uint32_t val;
 714
 715     bus_num = (addr >> 16) & 0xff;
 716     while (s && s->bus_num != bus_num)
 717         s= s->next;
 718     if (!s)
 719         goto fail;
 720     pci_dev = s->devices[(addr >> 8) & 0xff];
 721     if (!pci_dev) {
 722     fail:
 723         switch(len) {
 724         case 1:
 725             val = 0xff;
 726             break;
 727         case 2:
 728             val = 0xffff;
 729             break;
 730         default:
 731         case 4:
 732             val = 0xffffffff;
 733             break;
 734         }
 735         goto the_end;
 736     }
 737     config_addr = addr & 0xff;
 738     val = pci_dev->config_read(pci_dev, config_addr, len);
 739 #if defined(DEBUG_PCI)
 740     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 741            pci_dev->name, config_addr, val, len);
 742 #endif
 743  the_end:
 744 #if defined(DEBUG_PCI) && 0
 745     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 746            addr, val, len);
 747 #endif
 748     return val;
 749 }
 750
 751 /***********************************************************/
 752 /* generic PCI irq support */
 753
 754 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 755 static void pci_set_irq(void *opaque, int irq_num, int level)
 756 {
 757     PCIDevice *pci_dev = (PCIDevice *)opaque;
 758     PCIBus *bus;
 759     int change;
 760
 761     change = level - pci_dev->irq_state[irq_num];
 762     if (!change)
 763         return;
 764
 765     pci_dev->irq_state[irq_num] = level;
 766
 767 #if defined(TARGET_IA64)
 768     ioapic_set_irq(pci_dev, irq_num, level);
 769 #endif
 770
 771     for (;;) {
 772         bus = pci_dev->bus;
 773         irq_num = bus->map_irq(pci_dev, irq_num);
 774         if (bus->set_irq)
 775             break;
 776         pci_dev = bus->parent_dev;
 777     }
 778     bus->irq_count[irq_num] += change;
 779     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 780 }
 781
 782 int pci_map_irq(PCIDevice *pci_dev, int pin)
 783 {
 784     return pci_dev->bus->map_irq(pci_dev, pin);
 785 }
 786
 787 /***********************************************************/
 788 /* monitor info on PCI */
 789
 790 typedef struct {
 791     uint16_t class;
 792     const char *desc;
 793 } pci_class_desc;
 794
 795 static const pci_class_desc pci_class_descriptions[] =
 796 {
 797     { 0x0100, "SCSI controller"},
 798     { 0x0101, "IDE controller"},
 799     { 0x0102, "Floppy controller"},
 800     { 0x0103, "IPI controller"},
 801     { 0x0104, "RAID controller"},
 802     { 0x0106, "SATA controller"},
 803     { 0x0107, "SAS controller"},
 804     { 0x0180, "Storage controller"},
 805     { 0x0200, "Ethernet controller"},
 806     { 0x0201, "Token Ring controller"},
 807     { 0x0202, "FDDI controller"},
 808     { 0x0203, "ATM controller"},
 809     { 0x0280, "Network controller"},
 810     { 0x0300, "VGA controller"},
 811     { 0x0301, "XGA controller"},
 812     { 0x0302, "3D controller"},
 813     { 0x0380, "Display controller"},
 814     { 0x0400, "Video controller"},
 815     { 0x0401, "Audio controller"},
 816     { 0x0402, "Phone"},
 817     { 0x0480, "Multimedia controller"},
 818     { 0x0500, "RAM controller"},
 819     { 0x0501, "Flash controller"},
 820     { 0x0580, "Memory controller"},
 821     { 0x0600, "Host bridge"},
 822     { 0x0601, "ISA bridge"},
 823     { 0x0602, "EISA bridge"},
 824     { 0x0603, "MC bridge"},
 825     { 0x0604, "PCI bridge"},
 826     { 0x0605, "PCMCIA bridge"},
 827     { 0x0606, "NUBUS bridge"},
 828     { 0x0607, "CARDBUS bridge"},
 829     { 0x0608, "RACEWAY bridge"},
 830     { 0x0680, "Bridge"},
 831     { 0x0c03, "USB controller"},
 832     { 0, NULL}
 833 };
 834
 835 static void pci_info_device(PCIDevice *d)
 836 {
 837     Monitor *mon = cur_mon;
 838     int i, class;
 839     PCIIORegion *r;
 840     const pci_class_desc *desc;
 841
 842     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 843                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 844     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 845     monitor_printf(mon, "    ");
 846     desc = pci_class_descriptions;
 847     while (desc->desc && class != desc->class)
 848         desc++;
 849     if (desc->desc) {
 850         monitor_printf(mon, "%s", desc->desc);
 851     } else {
 852         monitor_printf(mon, "Class %04x", class);
 853     }
 854     monitor_printf(mon, ": PCI device %04x:%04x\n",
 855            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 856            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 857
 858     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 859         monitor_printf(mon, "      IRQ %d.\n",
 860                        d->config[PCI_INTERRUPT_LINE]);
 861     }
 862     if (class == 0x0604) {
 863         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 864     }
 865     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 866         r = &d->io_regions[i];
 867         if (r->size != 0) {
 868             monitor_printf(mon, "      BAR%d: ", i);
 869             if (r->type & PCI_ADDRESS_SPACE_IO) {
 870                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 871                                r->addr, r->addr + r->size - 1);
 872             } else {
 873                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 874                                r->addr, r->addr + r->size - 1);
 875             }
 876         }
 877     }
 878     if (class == 0x0604 && d->config[0x19] != 0) {
 879         pci_for_each_device(d->config[0x19], pci_info_device);
 880     }
 881 }
 882
 883 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 884 {
 885     PCIBus *bus = first_bus;
 886     PCIDevice *d;
 887     int devfn;
 888
 889     while (bus && bus->bus_num != bus_num)
 890         bus = bus->next;
 891     if (bus) {
 892         for(devfn = 0; devfn < 256; devfn++) {
 893             d = bus->devices[devfn];
 894             if (d)
 895                 fn(d);
 896         }
 897     }
 898 }
 899
 900 void pci_info(Monitor *mon)
 901 {
 902     pci_for_each_device(0, pci_info_device);
 903 }
 904
 905 static const char * const pci_nic_models[] = {
 906     "ne2k_pci",
 907     "i82551",
 908     "i82557b",
 909     "i82559er",
 910     "rtl8139",
 911     "e1000",
 912     "pcnet",
 913     "virtio",
 914     NULL
 915 };
 916
 917 static const char * const pci_nic_names[] = {
 918     "ne2k_pci",
 919     "i82551",
 920     "i82557b",
 921     "i82559er",
 922     "rtl8139",
 923     "e1000",
 924     "pcnet",
 925     "virtio-net-pci",
 926     NULL
 927 };
 928
 929 /* Initialize a PCI NIC.  */
 930 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 931                   const char *default_model)
 932 {
 933     DeviceState *dev;
 934     int i;
 935
 936     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 937
 938     for (i = 0; pci_nic_models[i]; i++) {
 939         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 940             dev = qdev_create(&bus->qbus, pci_nic_names[i]);
 941             qdev_set_prop_int(dev, "devfn", devfn);
 942             qdev_set_netdev(dev, nd);
 943             qdev_init(dev);
 944             nd->private = dev;
 945             return (PCIDevice *)dev;
 946         }
 947     }
 948
 949     return NULL;
 950 }
 951
 952 typedef struct {
 953     PCIDevice dev;
 954     PCIBus *bus;
 955 } PCIBridge;
 956
 957 static void pci_bridge_write_config(PCIDevice *d,
 958                              uint32_t address, uint32_t val, int len)
 959 {
 960     PCIBridge *s = (PCIBridge *)d;
 961
 962     if (address == 0x19 || (address == 0x18 && len > 1)) {
 963         if (address == 0x19)
 964             s->bus->bus_num = val & 0xff;
 965         else
 966             s->bus->bus_num = (val >> 8) & 0xff;
 967 #if defined(DEBUG_PCI)
 968         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 969 #endif
 970     }
 971     pci_default_write_config(d, address, val, len);
 972 }
 973
 974 PCIBus *pci_find_bus(int bus_num)
 975 {
 976     PCIBus *bus = first_bus;
 977
 978     while (bus && bus->bus_num != bus_num)
 979         bus = bus->next;
 980
 981     return bus;
 982 }
 983
 984 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 985 {
 986     PCIBus *bus = pci_find_bus(bus_num);
 987
 988     if (!bus)
 989         return NULL;
 990
 991     return bus->devices[PCI_DEVFN(slot, function)];
 992 }
 993
 994 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 995                         pci_map_irq_fn map_irq, const char *name)
 996 {
 997     PCIBridge *s;
 998     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 999                                          devfn, NULL, pci_bridge_write_config);
1000
1001     pci_config_set_vendor_id(s->dev.config, vid);
1002     pci_config_set_device_id(s->dev.config, did);
1003
1004     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
1005     s->dev.config[0x05] = 0x00;
1006     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
1007     s->dev.config[0x07] = 0x00; // status = fast devsel
1008     s->dev.config[0x08] = 0x00; // revision
1009     s->dev.config[0x09] = 0x00; // programming i/f
1010     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
1011     s->dev.config[0x0D] = 0x10; // latency_timer
1012     s->dev.config[PCI_HEADER_TYPE] =
1013         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
1014     s->dev.config[0x1E] = 0xa0; // secondary status
1015
1016     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
1017     return s->bus;
1018 }
1019
1020 typedef struct {
1021     DeviceInfo qdev;
1022     pci_qdev_initfn init;
1023 } PCIDeviceInfo;
1024
1025 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1026 {
1027     PCIDevice *pci_dev = (PCIDevice *)qdev;
1028     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1029     PCIBus *bus;
1030     int devfn;
1031
1032     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1033     devfn = qdev_get_prop_int(qdev, "devfn", -1);
1034     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
1035                                      NULL, NULL);//FIXME:config_read, config_write);
1036     assert(pci_dev);
1037     info->init(pci_dev);
1038 }
1039
1040 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
1041 {
1042     PCIDeviceInfo *info;
1043
1044     info = qemu_mallocz(sizeof(*info));
1045     info->qdev.name = qemu_strdup(name);
1046     info->qdev.size = size;
1047     info->init = init;
1048     info->qdev.init = pci_qdev_init;
1049     info->qdev.bus_type = BUS_TYPE_PCI;
1050
1051     qdev_register(&info->qdev);
1052 }
1053
1054 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1055 {
1056     DeviceState *dev;
1057
1058     dev = qdev_create(&bus->qbus, name);
1059     qdev_set_prop_int(dev, "devfn", devfn);
1060     qdev_init(dev);
1061
1062     return (PCIDevice *)dev;
1063 }
1064
1065 int pci_enable_capability_support(PCIDevice *pci_dev,
1066                                   uint32_t config_start,
1067                                   PCICapConfigReadFunc *config_read,
1068                                   PCICapConfigWriteFunc *config_write,
1069                                   PCICapConfigInitFunc *config_init)
1070 {
1071     if (!pci_dev)
1072         return -ENODEV;
1073
1074     pci_dev->config[0x06] |= 0x10; // status = capabilities
1075
1076     if (config_start == 0)
1077         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1078     else if (config_start >= 0x40 && config_start < 0xff)
1079         pci_dev->cap.start = config_start;
1080     else
1081         return -EINVAL;
1082
1083     if (config_read)
1084         pci_dev->cap.config_read = config_read;
1085     else
1086         pci_dev->cap.config_read = pci_default_cap_read_config;
1087     if (config_write)
1088         pci_dev->cap.config_write = config_write;
1089     else
1090         pci_dev->cap.config_write = pci_default_cap_write_config;
1091     pci_dev->cap.supported = 1;
1092     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1093     return config_init(pci_dev);
1094 }