hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28
  29 /* APIC Local Vector Table */
  30 #define APIC_LVT_TIMER   0
  31 #define APIC_LVT_THERMAL 1
  32 #define APIC_LVT_PERFORM 2
  33 #define APIC_LVT_LINT0   3
  34 #define APIC_LVT_LINT1   4
  35 #define APIC_LVT_ERROR   5
  36 #define APIC_LVT_NB      6
  37
  38 /* APIC delivery modes */
  39 #define APIC_DM_FIXED   0
  40 #define APIC_DM_LOWPRI  1
  41 #define APIC_DM_SMI     2
  42 #define APIC_DM_NMI     4
  43 #define APIC_DM_INIT    5
  44 #define APIC_DM_SIPI    6
  45 #define APIC_DM_EXTINT  7
  46
  47 /* APIC destination mode */
  48 #define APIC_DESTMODE_FLAT      0xf
  49 #define APIC_DESTMODE_CLUSTER   1
  50
  51 #define APIC_TRIGGER_EDGE  0
  52 #define APIC_TRIGGER_LEVEL 1
  53
  54 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  55 #define APIC_LVT_MASKED                 (1<<16)
  56 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  57 #define APIC_LVT_REMOTE_IRR             (1<<14)
  58 #define APIC_INPUT_POLARITY             (1<<13)
  59 #define APIC_SEND_PENDING               (1<<12)
  60
  61 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  62
  63 #define APIC_SV_ENABLE (1 << 8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 typedef struct APICState {
  69     CPUState *cpu_env;
  70     uint32_t apicbase;
  71     uint8_t id;
  72     uint8_t arb_id;
  73     uint8_t tpr;
  74     uint32_t spurious_vec;
  75     uint8_t log_dest;
  76     uint8_t dest_mode;
  77     uint32_t isr[8];  /* in service register */
  78     uint32_t tmr[8];  /* trigger mode register */
  79     uint32_t irr[8]; /* interrupt request register */
  80     uint32_t lvt[APIC_LVT_NB];
  81     uint32_t esr; /* error register */
  82     uint32_t icr[2];
  83
  84     uint32_t divide_conf;
  85     int count_shift;
  86     uint32_t initial_count;
  87     int64_t initial_count_load_time, next_time;
  88     uint32_t idx;
  89     QEMUTimer *timer;
  90 } APICState;
  91
  92 static int apic_io_memory;
  93 static APICState *local_apics[MAX_APICS + 1];
  94 static int last_apic_idx = 0;
  95 static int apic_irq_delivered;
  96
  97
  98 static void apic_init_ipi(APICState *s);
  99 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 100 static void apic_update_irq(APICState *s);
 101 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 102                                       uint8_t dest, uint8_t dest_mode);
 103
 104 /* Find first bit starting from msb */
 105 static int fls_bit(uint32_t value)
 106 {
 107     return 31 - clz32(value);
 108 }
 109
 110 /* Find first bit starting from lsb */
 111 static int ffs_bit(uint32_t value)
 112 {
 113     return ctz32(value);
 114 }
 115
 116 static inline void set_bit(uint32_t *tab, int index)
 117 {
 118     int i, mask;
 119     i = index >> 5;
 120     mask = 1 << (index & 0x1f);
 121     tab[i] |= mask;
 122 }
 123
 124 static inline void reset_bit(uint32_t *tab, int index)
 125 {
 126     int i, mask;
 127     i = index >> 5;
 128     mask = 1 << (index & 0x1f);
 129     tab[i] &= ~mask;
 130 }
 131
 132 static inline int get_bit(uint32_t *tab, int index)
 133 {
 134     int i, mask;
 135     i = index >> 5;
 136     mask = 1 << (index & 0x1f);
 137     return !!(tab[i] & mask);
 138 }
 139
 140 static void apic_local_deliver(CPUState *env, int vector)
 141 {
 142     APICState *s = env->apic_state;
 143     uint32_t lvt = s->lvt[vector];
 144     int trigger_mode;
 145
 146     if (lvt & APIC_LVT_MASKED)
 147         return;
 148
 149     switch ((lvt >> 8) & 7) {
 150     case APIC_DM_SMI:
 151         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 152         break;
 153
 154     case APIC_DM_NMI:
 155         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 156         break;
 157
 158     case APIC_DM_EXTINT:
 159         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 160         break;
 161
 162     case APIC_DM_FIXED:
 163         trigger_mode = APIC_TRIGGER_EDGE;
 164         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 165             (lvt & APIC_LVT_LEVEL_TRIGGER))
 166             trigger_mode = APIC_TRIGGER_LEVEL;
 167         apic_set_irq(s, lvt & 0xff, trigger_mode);
 168     }
 169 }
 170
 171 void apic_deliver_pic_intr(CPUState *env, int level)
 172 {
 173     if (level)
 174         apic_local_deliver(env, APIC_LVT_LINT0);
 175     else {
 176         APICState *s = env->apic_state;
 177         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 178
 179         switch ((lvt >> 8) & 7) {
 180         case APIC_DM_FIXED:
 181             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 182                 break;
 183             reset_bit(s->irr, lvt & 0xff);
 184             /* fall through */
 185         case APIC_DM_EXTINT:
 186             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 187             break;
 188         }
 189     }
 190 }
 191
 192 #define foreach_apic(apic, deliver_bitmask, code) \
 193 {\
 194     int __i, __j, __mask;\
 195     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 196         __mask = deliver_bitmask[__i];\
 197         if (__mask) {\
 198             for(__j = 0; __j < 32; __j++) {\
 199                 if (__mask & (1 << __j)) {\
 200                     apic = local_apics[__i * 32 + __j];\
 201                     if (apic) {\
 202                         code;\
 203                     }\
 204                 }\
 205             }\
 206         }\
 207     }\
 208 }
 209
 210 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 211                              uint8_t delivery_mode,
 212                              uint8_t vector_num, uint8_t polarity,
 213                              uint8_t trigger_mode)
 214 {
 215     APICState *apic_iter;
 216
 217     switch (delivery_mode) {
 218         case APIC_DM_LOWPRI:
 219             /* XXX: search for focus processor, arbitration */
 220             {
 221                 int i, d;
 222                 d = -1;
 223                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 224                     if (deliver_bitmask[i]) {
 225                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 226                         break;
 227                     }
 228                 }
 229                 if (d >= 0) {
 230                     apic_iter = local_apics[d];
 231                     if (apic_iter) {
 232                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 233                     }
 234                 }
 235             }
 236             return;
 237
 238         case APIC_DM_FIXED:
 239             break;
 240
 241         case APIC_DM_SMI:
 242             foreach_apic(apic_iter, deliver_bitmask,
 243                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 244             return;
 245
 246         case APIC_DM_NMI:
 247             foreach_apic(apic_iter, deliver_bitmask,
 248                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 249             return;
 250
 251         case APIC_DM_INIT:
 252             /* normal INIT IPI sent to processors */
 253             foreach_apic(apic_iter, deliver_bitmask,
 254                          apic_init_ipi(apic_iter) );
 255             return;
 256
 257         case APIC_DM_EXTINT:
 258             /* handled in I/O APIC code */
 259             break;
 260
 261         default:
 262             return;
 263     }
 264
 265     foreach_apic(apic_iter, deliver_bitmask,
 266                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 267 }
 268
 269 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 270                       uint8_t delivery_mode, uint8_t vector_num,
 271                       uint8_t polarity, uint8_t trigger_mode)
 272 {
 273     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 274
 275     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 276     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 277                      trigger_mode);
 278 }
 279
 280 void cpu_set_apic_base(CPUState *env, uint64_t val)
 281 {
 282     APICState *s = env->apic_state;
 283 #ifdef DEBUG_APIC
 284     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 285 #endif
 286     if (!s)
 287         return;
 288     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 289         s->apicbase = val;
 290     else
 291         s->apicbase = (val & 0xfffff000) |
 292             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 293     /* if disabled, cannot be enabled again */
 294     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 295         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 296         env->cpuid_features &= ~CPUID_APIC;
 297         s->spurious_vec &= ~APIC_SV_ENABLE;
 298     }
 299 }
 300
 301 uint64_t cpu_get_apic_base(CPUState *env)
 302 {
 303     APICState *s = env->apic_state;
 304 #ifdef DEBUG_APIC
 305     printf("cpu_get_apic_base: %016" PRIx64 "\n",
 306            s ? (uint64_t)s->apicbase: 0);
 307 #endif
 308     return s ? s->apicbase : 0;
 309 }
 310
 311 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 312 {
 313     APICState *s = env->apic_state;
 314     if (!s)
 315         return;
 316     s->tpr = (val & 0x0f) << 4;
 317     apic_update_irq(s);
 318 }
 319
 320 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 321 {
 322     APICState *s = env->apic_state;
 323     return s ? s->tpr >> 4 : 0;
 324 }
 325
 326 /* return -1 if no bit is set */
 327 static int get_highest_priority_int(uint32_t *tab)
 328 {
 329     int i;
 330     for(i = 7; i >= 0; i--) {
 331         if (tab[i] != 0) {
 332             return i * 32 + fls_bit(tab[i]);
 333         }
 334     }
 335     return -1;
 336 }
 337
 338 static int apic_get_ppr(APICState *s)
 339 {
 340     int tpr, isrv, ppr;
 341
 342     tpr = (s->tpr >> 4);
 343     isrv = get_highest_priority_int(s->isr);
 344     if (isrv < 0)
 345         isrv = 0;
 346     isrv >>= 4;
 347     if (tpr >= isrv)
 348         ppr = s->tpr;
 349     else
 350         ppr = isrv << 4;
 351     return ppr;
 352 }
 353
 354 static int apic_get_arb_pri(APICState *s)
 355 {
 356     /* XXX: arbitration */
 357     return 0;
 358 }
 359
 360 /* signal the CPU if an irq is pending */
 361 static void apic_update_irq(APICState *s)
 362 {
 363     int irrv, ppr;
 364     if (!(s->spurious_vec & APIC_SV_ENABLE))
 365         return;
 366     irrv = get_highest_priority_int(s->irr);
 367     if (irrv < 0)
 368         return;
 369     ppr = apic_get_ppr(s);
 370     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 371         return;
 372     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 373 }
 374
 375 void apic_reset_irq_delivered(void)
 376 {
 377     apic_irq_delivered = 0;
 378 }
 379
 380 int apic_get_irq_delivered(void)
 381 {
 382     return apic_irq_delivered;
 383 }
 384
 385 void apic_set_irq_delivered(void)
 386 {
 387     apic_irq_delivered = 1;
 388 }
 389
 390 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 391 {
 392     apic_irq_delivered += !get_bit(s->irr, vector_num);
 393
 394     set_bit(s->irr, vector_num);
 395     if (trigger_mode)
 396         set_bit(s->tmr, vector_num);
 397     else
 398         reset_bit(s->tmr, vector_num);
 399     apic_update_irq(s);
 400 }
 401
 402 static void apic_eoi(APICState *s)
 403 {
 404     int isrv;
 405     isrv = get_highest_priority_int(s->isr);
 406     if (isrv < 0)
 407         return;
 408     reset_bit(s->isr, isrv);
 409     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 410             set the remote IRR bit for level triggered interrupts. */
 411     apic_update_irq(s);
 412 }
 413
 414 static int apic_find_dest(uint8_t dest)
 415 {
 416     APICState *apic = local_apics[dest];
 417     int i;
 418
 419     if (apic && apic->id == dest)
 420         return dest;  /* shortcut in case apic->id == apic->idx */
 421
 422     for (i = 0; i < MAX_APICS; i++) {
 423         apic = local_apics[i];
 424         if (apic && apic->id == dest)
 425             return i;
 426     }
 427
 428     return -1;
 429 }
 430
 431 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 432                                       uint8_t dest, uint8_t dest_mode)
 433 {
 434     APICState *apic_iter;
 435     int i;
 436
 437     if (dest_mode == 0) {
 438         if (dest == 0xff) {
 439             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 440         } else {
 441             int idx = apic_find_dest(dest);
 442             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 443             if (idx >= 0)
 444                 set_bit(deliver_bitmask, idx);
 445         }
 446     } else {
 447         /* XXX: cluster mode */
 448         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 449         for(i = 0; i < MAX_APICS; i++) {
 450             apic_iter = local_apics[i];
 451             if (apic_iter) {
 452                 if (apic_iter->dest_mode == 0xf) {
 453                     if (dest & apic_iter->log_dest)
 454                         set_bit(deliver_bitmask, i);
 455                 } else if (apic_iter->dest_mode == 0x0) {
 456                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 457                         (dest & apic_iter->log_dest & 0x0f)) {
 458                         set_bit(deliver_bitmask, i);
 459                     }
 460                 }
 461             }
 462         }
 463     }
 464 }
 465
 466
 467 static void apic_init_ipi(APICState *s)
 468 {
 469     int i;
 470
 471     s->tpr = 0;
 472     s->spurious_vec = 0xff;
 473     s->log_dest = 0;
 474     s->dest_mode = 0xf;
 475     memset(s->isr, 0, sizeof(s->isr));
 476     memset(s->tmr, 0, sizeof(s->tmr));
 477     memset(s->irr, 0, sizeof(s->irr));
 478     for(i = 0; i < APIC_LVT_NB; i++)
 479         s->lvt[i] = 1 << 16; /* mask LVT */
 480     s->esr = 0;
 481     memset(s->icr, 0, sizeof(s->icr));
 482     s->divide_conf = 0;
 483     s->count_shift = 0;
 484     s->initial_count = 0;
 485     s->initial_count_load_time = 0;
 486     s->next_time = 0;
 487
 488     cpu_reset(s->cpu_env);
 489
 490     s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
 491
 492     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 493         kvm_apic_init(s->cpu_env);
 494 }
 495
 496 /* send a SIPI message to the CPU to start it */
 497 static void apic_startup(APICState *s, int vector_num)
 498 {
 499     CPUState *env = s->cpu_env;
 500     if (!env->halted)
 501         return;
 502     env->eip = 0;
 503     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 504                            0xffff, 0);
 505     env->halted = 0;
 506     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 507         kvm_update_after_sipi(env);
 508 }
 509
 510 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 511                          uint8_t delivery_mode, uint8_t vector_num,
 512                          uint8_t polarity, uint8_t trigger_mode)
 513 {
 514     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 515     int dest_shorthand = (s->icr[0] >> 18) & 3;
 516     APICState *apic_iter;
 517
 518     switch (dest_shorthand) {
 519     case 0:
 520         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 521         break;
 522     case 1:
 523         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 524         set_bit(deliver_bitmask, s->idx);
 525         break;
 526     case 2:
 527         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 528         break;
 529     case 3:
 530         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 531         reset_bit(deliver_bitmask, s->idx);
 532         break;
 533     }
 534
 535     switch (delivery_mode) {
 536         case APIC_DM_INIT:
 537             {
 538                 int trig_mode = (s->icr[0] >> 15) & 1;
 539                 int level = (s->icr[0] >> 14) & 1;
 540                 if (level == 0 && trig_mode == 1) {
 541                     foreach_apic(apic_iter, deliver_bitmask,
 542                                  apic_iter->arb_id = apic_iter->id );
 543                     return;
 544                 }
 545             }
 546             break;
 547
 548         case APIC_DM_SIPI:
 549             foreach_apic(apic_iter, deliver_bitmask,
 550                          apic_startup(apic_iter, vector_num) );
 551             return;
 552     }
 553
 554     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 555                      trigger_mode);
 556 }
 557
 558 int apic_get_interrupt(CPUState *env)
 559 {
 560     APICState *s = env->apic_state;
 561     int intno;
 562
 563     /* if the APIC is installed or enabled, we let the 8259 handle the
 564        IRQs */
 565     if (!s)
 566         return -1;
 567     if (!(s->spurious_vec & APIC_SV_ENABLE))
 568         return -1;
 569
 570     /* XXX: spurious IRQ handling */
 571     intno = get_highest_priority_int(s->irr);
 572     if (intno < 0)
 573         return -1;
 574     if (s->tpr && intno <= s->tpr)
 575         return s->spurious_vec & 0xff;
 576     reset_bit(s->irr, intno);
 577     set_bit(s->isr, intno);
 578     apic_update_irq(s);
 579     return intno;
 580 }
 581
 582 int apic_accept_pic_intr(CPUState *env)
 583 {
 584     APICState *s = env->apic_state;
 585     uint32_t lvt0;
 586
 587     if (!s)
 588         return -1;
 589
 590     lvt0 = s->lvt[APIC_LVT_LINT0];
 591
 592     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 593         (lvt0 & APIC_LVT_MASKED) == 0)
 594         return 1;
 595
 596     return 0;
 597 }
 598
 599 static uint32_t apic_get_current_count(APICState *s)
 600 {
 601     int64_t d;
 602     uint32_t val;
 603     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 604         s->count_shift;
 605     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 606         /* periodic */
 607         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 608     } else {
 609         if (d >= s->initial_count)
 610             val = 0;
 611         else
 612             val = s->initial_count - d;
 613     }
 614     return val;
 615 }
 616
 617 static void apic_timer_update(APICState *s, int64_t current_time)
 618 {
 619     int64_t next_time, d;
 620
 621     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 622         d = (current_time - s->initial_count_load_time) >>
 623             s->count_shift;
 624         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 625             if (!s->initial_count)
 626                 goto no_timer;
 627             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 628         } else {
 629             if (d >= s->initial_count)
 630                 goto no_timer;
 631             d = (uint64_t)s->initial_count + 1;
 632         }
 633         next_time = s->initial_count_load_time + (d << s->count_shift);
 634         qemu_mod_timer(s->timer, next_time);
 635         s->next_time = next_time;
 636     } else {
 637     no_timer:
 638         qemu_del_timer(s->timer);
 639     }
 640 }
 641
 642 static void apic_timer(void *opaque)
 643 {
 644     APICState *s = opaque;
 645
 646     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 647     apic_timer_update(s, s->next_time);
 648 }
 649
 650 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 651 {
 652     return 0;
 653 }
 654
 655 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 656 {
 657     return 0;
 658 }
 659
 660 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 661 {
 662 }
 663
 664 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 665 {
 666 }
 667
 668 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 669 {
 670     CPUState *env;
 671     APICState *s;
 672     uint32_t val;
 673     int index;
 674
 675     env = cpu_single_env;
 676     if (!env)
 677         return 0;
 678     s = env->apic_state;
 679
 680     index = (addr >> 4) & 0xff;
 681     switch(index) {
 682     case 0x02: /* id */
 683         val = s->id << 24;
 684         break;
 685     case 0x03: /* version */
 686         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 687         break;
 688     case 0x08:
 689         val = s->tpr;
 690         break;
 691     case 0x09:
 692         val = apic_get_arb_pri(s);
 693         break;
 694     case 0x0a:
 695         /* ppr */
 696         val = apic_get_ppr(s);
 697         break;
 698     case 0x0b:
 699         val = 0;
 700         break;
 701     case 0x0d:
 702         val = s->log_dest << 24;
 703         break;
 704     case 0x0e:
 705         val = s->dest_mode << 28;
 706         break;
 707     case 0x0f:
 708         val = s->spurious_vec;
 709         break;
 710     case 0x10 ... 0x17:
 711         val = s->isr[index & 7];
 712         break;
 713     case 0x18 ... 0x1f:
 714         val = s->tmr[index & 7];
 715         break;
 716     case 0x20 ... 0x27:
 717         val = s->irr[index & 7];
 718         break;
 719     case 0x28:
 720         val = s->esr;
 721         break;
 722     case 0x30:
 723     case 0x31:
 724         val = s->icr[index & 1];
 725         break;
 726     case 0x32 ... 0x37:
 727         val = s->lvt[index - 0x32];
 728         break;
 729     case 0x38:
 730         val = s->initial_count;
 731         break;
 732     case 0x39:
 733         val = apic_get_current_count(s);
 734         break;
 735     case 0x3e:
 736         val = s->divide_conf;
 737         break;
 738     default:
 739         s->esr |= ESR_ILLEGAL_ADDRESS;
 740         val = 0;
 741         break;
 742     }
 743 #ifdef DEBUG_APIC
 744     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 745 #endif
 746     return val;
 747 }
 748
 749 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 750 {
 751     CPUState *env;
 752     APICState *s;
 753     int index;
 754
 755     env = cpu_single_env;
 756     if (!env)
 757         return;
 758     s = env->apic_state;
 759
 760 #ifdef DEBUG_APIC
 761     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 762 #endif
 763
 764     index = (addr >> 4) & 0xff;
 765     switch(index) {
 766     case 0x02:
 767         s->id = (val >> 24);
 768         break;
 769     case 0x03:
 770         break;
 771     case 0x08:
 772         s->tpr = val;
 773         apic_update_irq(s);
 774         break;
 775     case 0x09:
 776     case 0x0a:
 777         break;
 778     case 0x0b: /* EOI */
 779         apic_eoi(s);
 780         break;
 781     case 0x0d:
 782         s->log_dest = val >> 24;
 783         break;
 784     case 0x0e:
 785         s->dest_mode = val >> 28;
 786         break;
 787     case 0x0f:
 788         s->spurious_vec = val & 0x1ff;
 789         apic_update_irq(s);
 790         break;
 791     case 0x10 ... 0x17:
 792     case 0x18 ... 0x1f:
 793     case 0x20 ... 0x27:
 794     case 0x28:
 795         break;
 796     case 0x30:
 797         s->icr[0] = val;
 798         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 799                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 800                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 801         break;
 802     case 0x31:
 803         s->icr[1] = val;
 804         break;
 805     case 0x32 ... 0x37:
 806         {
 807             int n = index - 0x32;
 808             s->lvt[n] = val;
 809             if (n == APIC_LVT_TIMER)
 810                 apic_timer_update(s, qemu_get_clock(vm_clock));
 811         }
 812         break;
 813     case 0x38:
 814         s->initial_count = val;
 815         s->initial_count_load_time = qemu_get_clock(vm_clock);
 816         apic_timer_update(s, s->initial_count_load_time);
 817         break;
 818     case 0x39:
 819         break;
 820     case 0x3e:
 821         {
 822             int v;
 823             s->divide_conf = val & 0xb;
 824             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 825             s->count_shift = (v + 1) & 7;
 826         }
 827         break;
 828     default:
 829         s->esr |= ESR_ILLEGAL_ADDRESS;
 830         break;
 831     }
 832 }
 833
 834 #ifdef KVM_CAP_IRQCHIP
 835
 836 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 837 {
 838     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 839 }
 840
 841 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 842                                  int reg_id, uint32_t val)
 843 {
 844     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 845 }
 846
 847 static void kvm_kernel_lapic_save_to_user(APICState *s)
 848 {
 849     struct kvm_lapic_state apic;
 850     struct kvm_lapic_state *kapic = &apic;
 851     int i, v;
 852
 853     kvm_get_lapic(s->cpu_env->kvm_cpu_state.vcpu_ctx, kapic);
 854
 855     s->id = kapic_reg(kapic, 0x2) >> 24;
 856     s->tpr = kapic_reg(kapic, 0x8);
 857     s->arb_id = kapic_reg(kapic, 0x9);
 858     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 859     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 860     s->spurious_vec = kapic_reg(kapic, 0xf);
 861     for (i = 0; i < 8; i++) {
 862         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 863         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 864         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 865     }
 866     s->esr = kapic_reg(kapic, 0x28);
 867     s->icr[0] = kapic_reg(kapic, 0x30);
 868     s->icr[1] = kapic_reg(kapic, 0x31);
 869     for (i = 0; i < APIC_LVT_NB; i++)
 870         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 871     s->initial_count = kapic_reg(kapic, 0x38);
 872     s->divide_conf = kapic_reg(kapic, 0x3e);
 873
 874     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 875     s->count_shift = (v + 1) & 7;
 876
 877     s->initial_count_load_time = qemu_get_clock(vm_clock);
 878     apic_timer_update(s, s->initial_count_load_time);
 879 }
 880
 881 static void kvm_kernel_lapic_load_from_user(APICState *s)
 882 {
 883     struct kvm_lapic_state apic;
 884     struct kvm_lapic_state *klapic = &apic;
 885     int i;
 886
 887     memset(klapic, 0, sizeof apic);
 888     kapic_set_reg(klapic, 0x2, s->id << 24);
 889     kapic_set_reg(klapic, 0x8, s->tpr);
 890     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 891     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 892     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 893     for (i = 0; i < 8; i++) {
 894         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 895         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 896         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 897     }
 898     kapic_set_reg(klapic, 0x28, s->esr);
 899     kapic_set_reg(klapic, 0x30, s->icr[0]);
 900     kapic_set_reg(klapic, 0x31, s->icr[1]);
 901     for (i = 0; i < APIC_LVT_NB; i++)
 902         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 903     kapic_set_reg(klapic, 0x38, s->initial_count);
 904     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 905
 906     kvm_set_lapic(s->cpu_env->kvm_cpu_state.vcpu_ctx, klapic);
 907 }
 908
 909 #endif
 910
 911 void qemu_kvm_load_lapic(CPUState *env)
 912 {
 913 #ifdef KVM_CAP_IRQCHIP
 914     if (kvm_enabled() && kvm_vcpu_inited(env) && qemu_kvm_irqchip_in_kernel()) {
 915         kvm_kernel_lapic_load_from_user(env->apic_state);
 916     }
 917 #endif
 918 }
 919
 920 static void apic_save(QEMUFile *f, void *opaque)
 921 {
 922     APICState *s = opaque;
 923     int i;
 924
 925 #ifdef KVM_CAP_IRQCHIP
 926     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 927         kvm_kernel_lapic_save_to_user(s);
 928     }
 929 #endif
 930
 931     qemu_put_be32s(f, &s->apicbase);
 932     qemu_put_8s(f, &s->id);
 933     qemu_put_8s(f, &s->arb_id);
 934     qemu_put_8s(f, &s->tpr);
 935     qemu_put_be32s(f, &s->spurious_vec);
 936     qemu_put_8s(f, &s->log_dest);
 937     qemu_put_8s(f, &s->dest_mode);
 938     for (i = 0; i < 8; i++) {
 939         qemu_put_be32s(f, &s->isr[i]);
 940         qemu_put_be32s(f, &s->tmr[i]);
 941         qemu_put_be32s(f, &s->irr[i]);
 942     }
 943     for (i = 0; i < APIC_LVT_NB; i++) {
 944         qemu_put_be32s(f, &s->lvt[i]);
 945     }
 946     qemu_put_be32s(f, &s->esr);
 947     qemu_put_be32s(f, &s->icr[0]);
 948     qemu_put_be32s(f, &s->icr[1]);
 949     qemu_put_be32s(f, &s->divide_conf);
 950     qemu_put_be32(f, s->count_shift);
 951     qemu_put_be32s(f, &s->initial_count);
 952     qemu_put_be64(f, s->initial_count_load_time);
 953     qemu_put_be64(f, s->next_time);
 954
 955     qemu_put_timer(f, s->timer);
 956 }
 957
 958 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 959 {
 960     APICState *s = opaque;
 961     int i;
 962
 963     if (version_id > 2)
 964         return -EINVAL;
 965
 966     /* XXX: what if the base changes? (registered memory regions) */
 967     qemu_get_be32s(f, &s->apicbase);
 968     qemu_get_8s(f, &s->id);
 969     qemu_get_8s(f, &s->arb_id);
 970     qemu_get_8s(f, &s->tpr);
 971     qemu_get_be32s(f, &s->spurious_vec);
 972     qemu_get_8s(f, &s->log_dest);
 973     qemu_get_8s(f, &s->dest_mode);
 974     for (i = 0; i < 8; i++) {
 975         qemu_get_be32s(f, &s->isr[i]);
 976         qemu_get_be32s(f, &s->tmr[i]);
 977         qemu_get_be32s(f, &s->irr[i]);
 978     }
 979     for (i = 0; i < APIC_LVT_NB; i++) {
 980         qemu_get_be32s(f, &s->lvt[i]);
 981     }
 982     qemu_get_be32s(f, &s->esr);
 983     qemu_get_be32s(f, &s->icr[0]);
 984     qemu_get_be32s(f, &s->icr[1]);
 985     qemu_get_be32s(f, &s->divide_conf);
 986     s->count_shift=qemu_get_be32(f);
 987     qemu_get_be32s(f, &s->initial_count);
 988     s->initial_count_load_time=qemu_get_be64(f);
 989     s->next_time=qemu_get_be64(f);
 990
 991     if (version_id >= 2)
 992         qemu_get_timer(f, s->timer);
 993
 994     qemu_kvm_load_lapic(s->cpu_env);
 995
 996     return 0;
 997 }
 998
 999 static void apic_reset(void *opaque)
1000 {
1001     APICState *s = opaque;
1002     int bsp = cpu_is_bsp(s->cpu_env);
1003
1004     s->apicbase = 0xfee00000 |
1005         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1006
1007     apic_init_ipi(s);
1008
1009     if (bsp) {
1010         /*
1011          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1012          * time typically by BIOS, so PIC interrupt can be delivered to the
1013          * processor when local APIC is enabled.
1014          */
1015         s->lvt[APIC_LVT_LINT0] = 0x700;
1016     }
1017     qemu_kvm_load_lapic(s->cpu_env);
1018 }
1019
1020 static CPUReadMemoryFunc *apic_mem_read[3] = {
1021     apic_mem_readb,
1022     apic_mem_readw,
1023     apic_mem_readl,
1024 };
1025
1026 static CPUWriteMemoryFunc *apic_mem_write[3] = {
1027     apic_mem_writeb,
1028     apic_mem_writew,
1029     apic_mem_writel,
1030 };
1031
1032 int apic_init(CPUState *env)
1033 {
1034     APICState *s;
1035
1036     if (last_apic_idx >= MAX_APICS)
1037         return -1;
1038     s = qemu_mallocz(sizeof(APICState));
1039     env->apic_state = s;
1040     s->idx = last_apic_idx++;
1041     s->id = env->cpuid_apic_id;
1042     s->cpu_env = env;
1043
1044     apic_reset(s);
1045
1046     /* XXX: mapping more APICs at the same memory location */
1047     if (apic_io_memory == 0) {
1048         /* NOTE: the APIC is directly connected to the CPU - it is not
1049            on the global memory bus. */
1050         apic_io_memory = cpu_register_io_memory(apic_mem_read,
1051                                                 apic_mem_write, NULL);
1052         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1053                                      apic_io_memory);
1054     }
1055     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1056
1057     register_savevm("apic", s->idx, 2, apic_save, apic_load, s);
1058     qemu_register_reset(apic_reset, 0, s);
1059
1060     local_apics[s->idx] = s;
1061     return 0;
1062 }
1063