2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
23 #include "qemu-common.h"
24 #include "cpu-common.h"
26 /* some important defines:
28 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
31 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
32 * otherwise little endian.
34 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
36 * TARGET_WORDS_BIGENDIAN : same for target cpu
39 #include "softfloat.h"
41 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
47 static inline uint16_t tswap16(uint16_t s
)
52 static inline uint32_t tswap32(uint32_t s
)
57 static inline uint64_t tswap64(uint64_t s
)
62 static inline void tswap16s(uint16_t *s
)
67 static inline void tswap32s(uint32_t *s
)
72 static inline void tswap64s(uint64_t *s
)
79 static inline uint16_t tswap16(uint16_t s
)
84 static inline uint32_t tswap32(uint32_t s
)
89 static inline uint64_t tswap64(uint64_t s
)
94 static inline void tswap16s(uint16_t *s
)
98 static inline void tswap32s(uint32_t *s
)
102 static inline void tswap64s(uint64_t *s
)
108 #if TARGET_LONG_SIZE == 4
109 #define tswapl(s) tswap32(s)
110 #define tswapls(s) tswap32s((uint32_t *)(s))
111 #define bswaptls(s) bswap32s(s)
113 #define tswapl(s) tswap64(s)
114 #define tswapls(s) tswap64s((uint64_t *)(s))
115 #define bswaptls(s) bswap64s(s)
123 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
127 #if defined(WORDS_BIGENDIAN) \
128 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
145 #if defined(WORDS_BIGENDIAN) \
146 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
172 /* CPU memory access without any memory or io remapping */
175 * the generic syntax for the memory accesses is:
177 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
179 * store: st{type}{size}{endian}_{access_type}(ptr, val)
182 * (empty): integer access
186 * (empty): for floats or 32 bit size
197 * (empty): target cpu endianness or 8 bit access
198 * r : reversed target cpu endianness (not implemented yet)
199 * be : big endian (not implemented yet)
200 * le : little endian (not implemented yet)
203 * raw : host memory access
204 * user : user mode access using soft MMU
205 * kernel : kernel mode access using soft MMU
207 static inline int ldub_p(const void *ptr
)
209 return *(uint8_t *)ptr
;
212 static inline int ldsb_p(const void *ptr
)
214 return *(int8_t *)ptr
;
217 static inline void stb_p(void *ptr
, int v
)
222 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
223 kernel handles unaligned load/stores may give better results, but
224 it is a system wide setting : bad */
225 #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
227 /* conservative code for little endian unaligned accesses */
228 static inline int lduw_le_p(const void *ptr
)
232 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
235 const uint8_t *p
= ptr
;
236 return p
[0] | (p
[1] << 8);
240 static inline int ldsw_le_p(const void *ptr
)
244 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
247 const uint8_t *p
= ptr
;
248 return (int16_t)(p
[0] | (p
[1] << 8));
252 static inline int ldl_le_p(const void *ptr
)
256 __asm__
__volatile__ ("lwbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
259 const uint8_t *p
= ptr
;
260 return p
[0] | (p
[1] << 8) | (p
[2] << 16) | (p
[3] << 24);
264 static inline uint64_t ldq_le_p(const void *ptr
)
266 const uint8_t *p
= ptr
;
269 v2
= ldl_le_p(p
+ 4);
270 return v1
| ((uint64_t)v2
<< 32);
273 static inline void stw_le_p(void *ptr
, int v
)
276 __asm__
__volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr
) : "r" (v
), "r" (ptr
));
284 static inline void stl_le_p(void *ptr
, int v
)
287 __asm__
__volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr
) : "r" (v
), "r" (ptr
));
297 static inline void stq_le_p(void *ptr
, uint64_t v
)
300 stl_le_p(p
, (uint32_t)v
);
301 stl_le_p(p
+ 4, v
>> 32);
306 static inline float32
ldfl_le_p(const void *ptr
)
316 static inline void stfl_le_p(void *ptr
, float32 v
)
326 static inline float64
ldfq_le_p(const void *ptr
)
329 u
.l
.lower
= ldl_le_p(ptr
);
330 u
.l
.upper
= ldl_le_p(ptr
+ 4);
334 static inline void stfq_le_p(void *ptr
, float64 v
)
338 stl_le_p(ptr
, u
.l
.lower
);
339 stl_le_p(ptr
+ 4, u
.l
.upper
);
344 static inline int lduw_le_p(const void *ptr
)
346 return *(uint16_t *)ptr
;
349 static inline int ldsw_le_p(const void *ptr
)
351 return *(int16_t *)ptr
;
354 static inline int ldl_le_p(const void *ptr
)
356 return *(uint32_t *)ptr
;
359 static inline uint64_t ldq_le_p(const void *ptr
)
361 return *(uint64_t *)ptr
;
364 static inline void stw_le_p(void *ptr
, int v
)
366 *(uint16_t *)ptr
= v
;
369 static inline void stl_le_p(void *ptr
, int v
)
371 *(uint32_t *)ptr
= v
;
374 static inline void stq_le_p(void *ptr
, uint64_t v
)
376 *(uint64_t *)ptr
= v
;
381 static inline float32
ldfl_le_p(const void *ptr
)
383 return *(float32
*)ptr
;
386 static inline float64
ldfq_le_p(const void *ptr
)
388 return *(float64
*)ptr
;
391 static inline void stfl_le_p(void *ptr
, float32 v
)
396 static inline void stfq_le_p(void *ptr
, float64 v
)
402 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
404 static inline int lduw_be_p(const void *ptr
)
406 #if defined(__i386__)
408 asm volatile ("movzwl %1, %0\n"
411 : "m" (*(uint16_t *)ptr
));
414 const uint8_t *b
= ptr
;
415 return ((b
[0] << 8) | b
[1]);
419 static inline int ldsw_be_p(const void *ptr
)
421 #if defined(__i386__)
423 asm volatile ("movzwl %1, %0\n"
426 : "m" (*(uint16_t *)ptr
));
429 const uint8_t *b
= ptr
;
430 return (int16_t)((b
[0] << 8) | b
[1]);
434 static inline int ldl_be_p(const void *ptr
)
436 #if defined(__i386__) || defined(__x86_64__)
438 asm volatile ("movl %1, %0\n"
441 : "m" (*(uint32_t *)ptr
));
444 const uint8_t *b
= ptr
;
445 return (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | b
[3];
449 static inline uint64_t ldq_be_p(const void *ptr
)
453 b
= ldl_be_p((uint8_t *)ptr
+ 4);
454 return (((uint64_t)a
<<32)|b
);
457 static inline void stw_be_p(void *ptr
, int v
)
459 #if defined(__i386__)
460 asm volatile ("xchgb %b0, %h0\n"
463 : "m" (*(uint16_t *)ptr
), "0" (v
));
465 uint8_t *d
= (uint8_t *) ptr
;
471 static inline void stl_be_p(void *ptr
, int v
)
473 #if defined(__i386__) || defined(__x86_64__)
474 asm volatile ("bswap %0\n"
477 : "m" (*(uint32_t *)ptr
), "0" (v
));
479 uint8_t *d
= (uint8_t *) ptr
;
487 static inline void stq_be_p(void *ptr
, uint64_t v
)
489 stl_be_p(ptr
, v
>> 32);
490 stl_be_p((uint8_t *)ptr
+ 4, v
);
495 static inline float32
ldfl_be_p(const void *ptr
)
505 static inline void stfl_be_p(void *ptr
, float32 v
)
515 static inline float64
ldfq_be_p(const void *ptr
)
518 u
.l
.upper
= ldl_be_p(ptr
);
519 u
.l
.lower
= ldl_be_p((uint8_t *)ptr
+ 4);
523 static inline void stfq_be_p(void *ptr
, float64 v
)
527 stl_be_p(ptr
, u
.l
.upper
);
528 stl_be_p((uint8_t *)ptr
+ 4, u
.l
.lower
);
533 static inline int lduw_be_p(const void *ptr
)
535 return *(uint16_t *)ptr
;
538 static inline int ldsw_be_p(const void *ptr
)
540 return *(int16_t *)ptr
;
543 static inline int ldl_be_p(const void *ptr
)
545 return *(uint32_t *)ptr
;
548 static inline uint64_t ldq_be_p(const void *ptr
)
550 return *(uint64_t *)ptr
;
553 static inline void stw_be_p(void *ptr
, int v
)
555 *(uint16_t *)ptr
= v
;
558 static inline void stl_be_p(void *ptr
, int v
)
560 *(uint32_t *)ptr
= v
;
563 static inline void stq_be_p(void *ptr
, uint64_t v
)
565 *(uint64_t *)ptr
= v
;
570 static inline float32
ldfl_be_p(const void *ptr
)
572 return *(float32
*)ptr
;
575 static inline float64
ldfq_be_p(const void *ptr
)
577 return *(float64
*)ptr
;
580 static inline void stfl_be_p(void *ptr
, float32 v
)
585 static inline void stfq_be_p(void *ptr
, float64 v
)
592 /* target CPU memory access functions */
593 #if defined(TARGET_WORDS_BIGENDIAN)
594 #define lduw_p(p) lduw_be_p(p)
595 #define ldsw_p(p) ldsw_be_p(p)
596 #define ldl_p(p) ldl_be_p(p)
597 #define ldq_p(p) ldq_be_p(p)
598 #define ldfl_p(p) ldfl_be_p(p)
599 #define ldfq_p(p) ldfq_be_p(p)
600 #define stw_p(p, v) stw_be_p(p, v)
601 #define stl_p(p, v) stl_be_p(p, v)
602 #define stq_p(p, v) stq_be_p(p, v)
603 #define stfl_p(p, v) stfl_be_p(p, v)
604 #define stfq_p(p, v) stfq_be_p(p, v)
606 #define lduw_p(p) lduw_le_p(p)
607 #define ldsw_p(p) ldsw_le_p(p)
608 #define ldl_p(p) ldl_le_p(p)
609 #define ldq_p(p) ldq_le_p(p)
610 #define ldfl_p(p) ldfl_le_p(p)
611 #define ldfq_p(p) ldfq_le_p(p)
612 #define stw_p(p, v) stw_le_p(p, v)
613 #define stl_p(p, v) stl_le_p(p, v)
614 #define stq_p(p, v) stq_le_p(p, v)
615 #define stfl_p(p, v) stfl_le_p(p, v)
616 #define stfq_p(p, v) stfq_le_p(p, v)
619 /* MMU memory access macros */
621 #if defined(CONFIG_USER_ONLY)
623 #include "qemu-types.h"
625 /* On some host systems the guest address space is reserved on the host.
626 * This allows the guest address space to be offset to a convenient location.
628 //#define GUEST_BASE 0x20000000
631 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
632 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
634 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
635 /* Check if given address fits target address space */ \
636 assert(__ret == (abi_ulong)__ret); \
639 #define h2g_valid(x) ({ \
640 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
641 (__guest == (abi_ulong)__guest); \
644 #define saddr(x) g2h(x)
645 #define laddr(x) g2h(x)
647 #else /* !CONFIG_USER_ONLY */
648 /* NOTE: we use double casts if pointers and target_ulong have
650 #define saddr(x) (uint8_t *)(long)(x)
651 #define laddr(x) (uint8_t *)(long)(x)
654 #define ldub_raw(p) ldub_p(laddr((p)))
655 #define ldsb_raw(p) ldsb_p(laddr((p)))
656 #define lduw_raw(p) lduw_p(laddr((p)))
657 #define ldsw_raw(p) ldsw_p(laddr((p)))
658 #define ldl_raw(p) ldl_p(laddr((p)))
659 #define ldq_raw(p) ldq_p(laddr((p)))
660 #define ldfl_raw(p) ldfl_p(laddr((p)))
661 #define ldfq_raw(p) ldfq_p(laddr((p)))
662 #define stb_raw(p, v) stb_p(saddr((p)), v)
663 #define stw_raw(p, v) stw_p(saddr((p)), v)
664 #define stl_raw(p, v) stl_p(saddr((p)), v)
665 #define stq_raw(p, v) stq_p(saddr((p)), v)
666 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
667 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
670 #if defined(CONFIG_USER_ONLY)
672 /* if user mode, no other memory access functions */
673 #define ldub(p) ldub_raw(p)
674 #define ldsb(p) ldsb_raw(p)
675 #define lduw(p) lduw_raw(p)
676 #define ldsw(p) ldsw_raw(p)
677 #define ldl(p) ldl_raw(p)
678 #define ldq(p) ldq_raw(p)
679 #define ldfl(p) ldfl_raw(p)
680 #define ldfq(p) ldfq_raw(p)
681 #define stb(p, v) stb_raw(p, v)
682 #define stw(p, v) stw_raw(p, v)
683 #define stl(p, v) stl_raw(p, v)
684 #define stq(p, v) stq_raw(p, v)
685 #define stfl(p, v) stfl_raw(p, v)
686 #define stfq(p, v) stfq_raw(p, v)
688 #define ldub_code(p) ldub_raw(p)
689 #define ldsb_code(p) ldsb_raw(p)
690 #define lduw_code(p) lduw_raw(p)
691 #define ldsw_code(p) ldsw_raw(p)
692 #define ldl_code(p) ldl_raw(p)
693 #define ldq_code(p) ldq_raw(p)
695 #define ldub_kernel(p) ldub_raw(p)
696 #define ldsb_kernel(p) ldsb_raw(p)
697 #define lduw_kernel(p) lduw_raw(p)
698 #define ldsw_kernel(p) ldsw_raw(p)
699 #define ldl_kernel(p) ldl_raw(p)
700 #define ldq_kernel(p) ldq_raw(p)
701 #define ldfl_kernel(p) ldfl_raw(p)
702 #define ldfq_kernel(p) ldfq_raw(p)
703 #define stb_kernel(p, v) stb_raw(p, v)
704 #define stw_kernel(p, v) stw_raw(p, v)
705 #define stl_kernel(p, v) stl_raw(p, v)
706 #define stq_kernel(p, v) stq_raw(p, v)
707 #define stfl_kernel(p, v) stfl_raw(p, v)
708 #define stfq_kernel(p, vt) stfq_raw(p, v)
710 #endif /* defined(CONFIG_USER_ONLY) */
712 /* page related stuff */
714 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
715 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
716 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
718 /* ??? These should be the larger of unsigned long and target_ulong. */
719 extern unsigned long qemu_real_host_page_size
;
720 extern unsigned long qemu_host_page_bits
;
721 extern unsigned long qemu_host_page_size
;
722 extern unsigned long qemu_host_page_mask
;
724 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
726 /* same as PROT_xxx */
727 #define PAGE_READ 0x0001
728 #define PAGE_WRITE 0x0002
729 #define PAGE_EXEC 0x0004
730 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
731 #define PAGE_VALID 0x0008
732 /* original state of the write flag (used when tracking self-modifying
734 #define PAGE_WRITE_ORG 0x0010
735 #define PAGE_RESERVED 0x0020
737 void page_dump(FILE *f
);
738 int walk_memory_regions(void *,
739 int (*fn
)(void *, unsigned long, unsigned long, unsigned long));
740 int page_get_flags(target_ulong address
);
741 void page_set_flags(target_ulong start
, target_ulong end
, int flags
);
742 int page_check_range(target_ulong start
, target_ulong len
, int flags
);
744 void cpu_exec_init_all(unsigned long tb_size
);
745 CPUState
*cpu_copy(CPUState
*env
);
746 CPUState
*qemu_get_cpu(int cpu
);
748 void cpu_dump_state(CPUState
*env
, FILE *f
,
749 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
751 void cpu_dump_statistics (CPUState
*env
, FILE *f
,
752 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
755 void QEMU_NORETURN
cpu_abort(CPUState
*env
, const char *fmt
, ...)
756 __attribute__ ((__format__ (__printf__
, 2, 3)));
757 extern CPUState
*first_cpu
;
758 extern CPUState
*cpu_single_env
;
759 extern int64_t qemu_icount
;
760 extern int use_icount
;
762 #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
763 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
764 #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
765 #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
766 #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
767 #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
768 #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
769 #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
770 #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
772 void cpu_interrupt(CPUState
*s
, int mask
);
773 void cpu_reset_interrupt(CPUState
*env
, int mask
);
775 void cpu_exit(CPUState
*s
);
777 int qemu_cpu_has_work(CPUState
*env
);
779 /* Breakpoint/watchpoint flags */
780 #define BP_MEM_READ 0x01
781 #define BP_MEM_WRITE 0x02
782 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
783 #define BP_STOP_BEFORE_ACCESS 0x04
784 #define BP_WATCHPOINT_HIT 0x08
788 int cpu_breakpoint_insert(CPUState
*env
, target_ulong pc
, int flags
,
789 CPUBreakpoint
**breakpoint
);
790 int cpu_breakpoint_remove(CPUState
*env
, target_ulong pc
, int flags
);
791 void cpu_breakpoint_remove_by_ref(CPUState
*env
, CPUBreakpoint
*breakpoint
);
792 void cpu_breakpoint_remove_all(CPUState
*env
, int mask
);
793 int cpu_watchpoint_insert(CPUState
*env
, target_ulong addr
, target_ulong len
,
794 int flags
, CPUWatchpoint
**watchpoint
);
795 int cpu_watchpoint_remove(CPUState
*env
, target_ulong addr
,
796 target_ulong len
, int flags
);
797 void cpu_watchpoint_remove_by_ref(CPUState
*env
, CPUWatchpoint
*watchpoint
);
798 void cpu_watchpoint_remove_all(CPUState
*env
, int mask
);
800 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
801 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
802 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
804 void cpu_single_step(CPUState
*env
, int enabled
);
805 void cpu_reset(CPUState
*s
);
807 /* Return the physical page corresponding to a virtual one. Use it
808 only for debugging because no protection checks are done. Return -1
810 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
);
812 #define CPU_LOG_TB_OUT_ASM (1 << 0)
813 #define CPU_LOG_TB_IN_ASM (1 << 1)
814 #define CPU_LOG_TB_OP (1 << 2)
815 #define CPU_LOG_TB_OP_OPT (1 << 3)
816 #define CPU_LOG_INT (1 << 4)
817 #define CPU_LOG_EXEC (1 << 5)
818 #define CPU_LOG_PCALL (1 << 6)
819 #define CPU_LOG_IOPORT (1 << 7)
820 #define CPU_LOG_TB_CPU (1 << 8)
821 #define CPU_LOG_RESET (1 << 9)
823 /* define log items */
824 typedef struct CPULogItem
{
830 extern const CPULogItem cpu_log_items
[];
832 void cpu_set_log(int log_flags
);
833 void cpu_set_log_filename(const char *filename
);
834 int cpu_str_to_log_mask(const char *str
);
838 /* NOTE: as these functions may be even used when there is an isa
839 brige on non x86 targets, we always defined them */
840 #ifndef NO_CPU_IO_DEFS
841 void cpu_outb(CPUState
*env
, int addr
, int val
);
842 void cpu_outw(CPUState
*env
, int addr
, int val
);
843 void cpu_outl(CPUState
*env
, int addr
, int val
);
844 int cpu_inb(CPUState
*env
, int addr
);
845 int cpu_inw(CPUState
*env
, int addr
);
846 int cpu_inl(CPUState
*env
, int addr
);
851 extern int phys_ram_fd
;
852 extern uint8_t *phys_ram_dirty
;
853 extern ram_addr_t ram_size
;
854 extern ram_addr_t last_ram_offset
;
855 extern uint8_t *bios_mem
;
857 /* physical memory access */
859 /* MMIO pages are identified by a combination of an IO device index and
860 3 flags. The ROMD code stores the page ram offset in iotlb entry,
861 so only a limited number of ids are avaiable. */
863 #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
865 /* Flags stored in the low bits of the TLB virtual address. These are
866 defined so that fast path ram access is all zeros. */
867 /* Zero if TLB entry is valid. */
868 #define TLB_INVALID_MASK (1 << 3)
869 /* Set if TLB entry references a clean RAM page. The iotlb entry will
870 contain the page physical address. */
871 #define TLB_NOTDIRTY (1 << 4)
872 /* Set if TLB entry is an IO callback. */
873 #define TLB_MMIO (1 << 5)
875 int cpu_memory_rw_debug(CPUState
*env
, target_ulong addr
,
876 uint8_t *buf
, int len
, int is_write
);
878 #define VGA_DIRTY_FLAG 0x01
879 #define CODE_DIRTY_FLAG 0x02
880 #define KQEMU_DIRTY_FLAG 0x04
881 #define MIGRATION_DIRTY_FLAG 0x08
883 /* read dirty bit (return 0 or 1) */
884 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr
)
886 return phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] == 0xff;
889 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr
,
892 return phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] & dirty_flags
;
895 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr
)
897 phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] = 0xff;
900 void cpu_physical_memory_reset_dirty(ram_addr_t start
, ram_addr_t end
,
902 void cpu_tlb_update_dirty(CPUState
*env
);
904 int cpu_physical_memory_set_dirty_tracking(int enable
);
906 int cpu_physical_memory_get_dirty_tracking(void);
908 int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr
,
909 target_phys_addr_t end_addr
);
911 void dump_exec_info(FILE *f
,
912 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
914 /* Coalesced MMIO regions are areas where write operations can be reordered.
915 * This usually implies that write operations are side-effect free. This allows
916 * batching which can make a major impact on performance when using
919 void qemu_register_coalesced_mmio(target_phys_addr_t addr
, ram_addr_t size
);
921 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr
, ram_addr_t size
);
923 /*******************************************/
924 /* host CPU ticks (if available) */
926 #if defined(_ARCH_PPC)
928 static inline int64_t cpu_get_real_ticks(void)
932 /* This reads timebase in one 64bit go and includes Cell workaround from:
933 http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html
935 __asm__
__volatile__ (
941 /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */
943 __asm__
__volatile__ (
949 : "=r" (retval
), "=r" (junk
));
954 #elif defined(__i386__)
956 static inline int64_t cpu_get_real_ticks(void)
959 asm volatile ("rdtsc" : "=A" (val
));
963 #elif defined(__x86_64__)
965 static inline int64_t cpu_get_real_ticks(void)
969 asm volatile("rdtsc" : "=a" (low
), "=d" (high
));
976 #elif defined(__hppa__)
978 static inline int64_t cpu_get_real_ticks(void)
981 asm volatile ("mfctl %%cr16, %0" : "=r"(val
));
985 #elif defined(__ia64)
987 static inline int64_t cpu_get_real_ticks(void)
990 asm volatile ("mov %0 = ar.itc" : "=r"(val
) :: "memory");
994 #elif defined(__s390__)
996 static inline int64_t cpu_get_real_ticks(void)
999 asm volatile("stck 0(%1)" : "=m" (val
) : "a" (&val
) : "cc");
1003 #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
1005 static inline int64_t cpu_get_real_ticks (void)
1009 asm volatile("rd %%tick,%0" : "=r"(rval
));
1019 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1020 : "=r"(rval
.i32
.high
), "=r"(rval
.i32
.low
));
1025 #elif defined(__mips__)
1027 static inline int64_t cpu_get_real_ticks(void)
1029 #if __mips_isa_rev >= 2
1031 static uint32_t cyc_per_count
= 0;
1034 __asm__
__volatile__("rdhwr %0, $3" : "=r" (cyc_per_count
));
1036 __asm__
__volatile__("rdhwr %1, $2" : "=r" (count
));
1037 return (int64_t)(count
* cyc_per_count
);
1040 static int64_t ticks
= 0;
1046 /* The host CPU doesn't have an easily accessible cycle counter.
1047 Just return a monotonically increasing value. This will be
1048 totally wrong, but hopefully better than nothing. */
1049 static inline int64_t cpu_get_real_ticks (void)
1051 static int64_t ticks
= 0;
1057 #ifdef CONFIG_PROFILER
1058 static inline int64_t profile_getclock(void)
1060 return cpu_get_real_ticks();
1063 extern int64_t kqemu_time
, kqemu_time_start
;
1064 extern int64_t qemu_time
, qemu_time_start
;
1065 extern int64_t tlb_flush_time
;
1066 extern int64_t kqemu_exec_count
;
1067 extern int64_t dev_time
;
1068 extern int64_t kqemu_ret_int_count
;
1069 extern int64_t kqemu_ret_excp_count
;
1070 extern int64_t kqemu_ret_intr_count
;
1073 #endif /* CPU_ALL_H */