hw/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21 #ifndef hw_omap_h
  22 # define hw_omap_h              "omap.h"
  23
  24 # define OMAP_EMIFS_BASE        0x00000000
  25 # define OMAP_CS0_BASE          0x00000000
  26 # define OMAP_CS1_BASE          0x04000000
  27 # define OMAP_CS2_BASE          0x08000000
  28 # define OMAP_CS3_BASE          0x0c000000
  29 # define OMAP_EMIFF_BASE        0x10000000
  30 # define OMAP_IMIF_BASE         0x20000000
  31 # define OMAP_LOCALBUS_BASE     0x30000000
  32 # define OMAP_MPUI_BASE         0xe1000000
  33
  34 # define OMAP730_SRAM_SIZE      0x00032000
  35 # define OMAP15XX_SRAM_SIZE     0x00030000
  36 # define OMAP16XX_SRAM_SIZE     0x00004000
  37 # define OMAP1611_SRAM_SIZE     0x0003e800
  38 # define OMAP_CS0_SIZE          0x04000000
  39 # define OMAP_CS1_SIZE          0x04000000
  40 # define OMAP_CS2_SIZE          0x04000000
  41 # define OMAP_CS3_SIZE          0x04000000
  42
  43 /* omap1_clk.c */
  44 struct omap_mpu_state_s;
  45 typedef struct clk *omap_clk;
  46 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  47 void omap_clk_init(struct omap_mpu_state_s *mpu);
  48 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  49 void omap_clk_get(omap_clk clk);
  50 void omap_clk_put(omap_clk clk);
  51 void omap_clk_onoff(omap_clk clk, int on);
  52 void omap_clk_canidle(omap_clk clk, int can);
  53 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  54 int64_t omap_clk_getrate(omap_clk clk);
  55 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  56
  57 /* omap.c */
  58 struct omap_intr_handler_s;
  59 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
  60                 unsigned long size, unsigned char nbanks,
  61                 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
  62
  63 /*
  64  * Common IRQ numbers for level 1 interrupt handler
  65  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
  66  */
  67 # define OMAP_INT_CAMERA                1
  68 # define OMAP_INT_FIQ                   3
  69 # define OMAP_INT_RTDX                  6
  70 # define OMAP_INT_DSP_MMU_ABORT         7
  71 # define OMAP_INT_HOST                  8
  72 # define OMAP_INT_ABORT                 9
  73 # define OMAP_INT_BRIDGE_PRIV           13
  74 # define OMAP_INT_GPIO_BANK1            14
  75 # define OMAP_INT_UART3                 15
  76 # define OMAP_INT_TIMER3                16
  77 # define OMAP_INT_DMA_CH0_6             19
  78 # define OMAP_INT_DMA_CH1_7             20
  79 # define OMAP_INT_DMA_CH2_8             21
  80 # define OMAP_INT_DMA_CH3               22
  81 # define OMAP_INT_DMA_CH4               23
  82 # define OMAP_INT_DMA_CH5               24
  83 # define OMAP_INT_DMA_LCD               25
  84 # define OMAP_INT_TIMER1                26
  85 # define OMAP_INT_WD_TIMER              27
  86 # define OMAP_INT_BRIDGE_PUB            28
  87 # define OMAP_INT_TIMER2                30
  88 # define OMAP_INT_LCD_CTRL              31
  89
  90 /*
  91  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
  92  */
  93 # define OMAP_INT_15XX_IH2_IRQ          0
  94 # define OMAP_INT_15XX_LB_MMU           17
  95 # define OMAP_INT_15XX_LOCAL_BUS        29
  96
  97 /*
  98  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
  99  */
 100 # define OMAP_INT_1510_SPI_TX           4
 101 # define OMAP_INT_1510_SPI_RX           5
 102 # define OMAP_INT_1510_DSP_MAILBOX1     10
 103 # define OMAP_INT_1510_DSP_MAILBOX2     11
 104
 105 /*
 106  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 107  */
 108 # define OMAP_INT_310_McBSP2_TX         4
 109 # define OMAP_INT_310_McBSP2_RX         5
 110 # define OMAP_INT_310_HSB_MAILBOX1      12
 111 # define OMAP_INT_310_HSAB_MMU          18
 112
 113 /*
 114  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 115  */
 116 # define OMAP_INT_1610_IH2_IRQ          0
 117 # define OMAP_INT_1610_IH2_FIQ          2
 118 # define OMAP_INT_1610_McBSP2_TX        4
 119 # define OMAP_INT_1610_McBSP2_RX        5
 120 # define OMAP_INT_1610_DSP_MAILBOX1     10
 121 # define OMAP_INT_1610_DSP_MAILBOX2     11
 122 # define OMAP_INT_1610_LCD_LINE         12
 123 # define OMAP_INT_1610_GPTIMER1         17
 124 # define OMAP_INT_1610_GPTIMER2         18
 125 # define OMAP_INT_1610_SSR_FIFO_0       29
 126
 127 /*
 128  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 129  */
 130 # define OMAP_INT_730_IH2_FIQ           0
 131 # define OMAP_INT_730_IH2_IRQ           1
 132 # define OMAP_INT_730_USB_NON_ISO       2
 133 # define OMAP_INT_730_USB_ISO           3
 134 # define OMAP_INT_730_ICR               4
 135 # define OMAP_INT_730_EAC               5
 136 # define OMAP_INT_730_GPIO_BANK1        6
 137 # define OMAP_INT_730_GPIO_BANK2        7
 138 # define OMAP_INT_730_GPIO_BANK3        8
 139 # define OMAP_INT_730_McBSP2TX          10
 140 # define OMAP_INT_730_McBSP2RX          11
 141 # define OMAP_INT_730_McBSP2RX_OVF      12
 142 # define OMAP_INT_730_LCD_LINE          14
 143 # define OMAP_INT_730_GSM_PROTECT       15
 144 # define OMAP_INT_730_TIMER3            16
 145 # define OMAP_INT_730_GPIO_BANK5        17
 146 # define OMAP_INT_730_GPIO_BANK6        18
 147 # define OMAP_INT_730_SPGIO_WR          29
 148
 149 /*
 150  * Common IRQ numbers for level 2 interrupt handler
 151  */
 152 # define OMAP_INT_KEYBOARD              1
 153 # define OMAP_INT_uWireTX               2
 154 # define OMAP_INT_uWireRX               3
 155 # define OMAP_INT_I2C                   4
 156 # define OMAP_INT_MPUIO                 5
 157 # define OMAP_INT_USB_HHC_1             6
 158 # define OMAP_INT_McBSP3TX              10
 159 # define OMAP_INT_McBSP3RX              11
 160 # define OMAP_INT_McBSP1TX              12
 161 # define OMAP_INT_McBSP1RX              13
 162 # define OMAP_INT_UART1                 14
 163 # define OMAP_INT_UART2                 15
 164 # define OMAP_INT_USB_W2FC              20
 165 # define OMAP_INT_1WIRE                 21
 166 # define OMAP_INT_OS_TIMER              22
 167 # define OMAP_INT_OQN                   23
 168 # define OMAP_INT_GAUGE_32K             24
 169 # define OMAP_INT_RTC_TIMER             25
 170 # define OMAP_INT_RTC_ALARM             26
 171 # define OMAP_INT_DSP_MMU               28
 172
 173 /*
 174  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 175  */
 176 # define OMAP_INT_1510_BT_MCSI1TX       16
 177 # define OMAP_INT_1510_BT_MCSI1RX       17
 178 # define OMAP_INT_1510_SoSSI_MATCH      19
 179 # define OMAP_INT_1510_MEM_STICK        27
 180 # define OMAP_INT_1510_COM_SPI_RO       31
 181
 182 /*
 183  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 184  */
 185 # define OMAP_INT_310_FAC               0
 186 # define OMAP_INT_310_USB_HHC_2         7
 187 # define OMAP_INT_310_MCSI1_FE          16
 188 # define OMAP_INT_310_MCSI2_FE          17
 189 # define OMAP_INT_310_USB_W2FC_ISO      29
 190 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 191 # define OMAP_INT_310_McBSP2RX_OF       31
 192
 193 /*
 194  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 195  */
 196 # define OMAP_INT_1610_FAC              0
 197 # define OMAP_INT_1610_USB_HHC_2        7
 198 # define OMAP_INT_1610_USB_OTG          8
 199 # define OMAP_INT_1610_SoSSI            9
 200 # define OMAP_INT_1610_BT_MCSI1TX       16
 201 # define OMAP_INT_1610_BT_MCSI1RX       17
 202 # define OMAP_INT_1610_SoSSI_MATCH      19
 203 # define OMAP_INT_1610_MEM_STICK        27
 204 # define OMAP_INT_1610_McBSP2RX_OF      31
 205 # define OMAP_INT_1610_STI              32
 206 # define OMAP_INT_1610_STI_WAKEUP       33
 207 # define OMAP_INT_1610_GPTIMER3         34
 208 # define OMAP_INT_1610_GPTIMER4         35
 209 # define OMAP_INT_1610_GPTIMER5         36
 210 # define OMAP_INT_1610_GPTIMER6         37
 211 # define OMAP_INT_1610_GPTIMER7         38
 212 # define OMAP_INT_1610_GPTIMER8         39
 213 # define OMAP_INT_1610_GPIO_BANK2       40
 214 # define OMAP_INT_1610_GPIO_BANK3       41
 215 # define OMAP_INT_1610_MMC2             42
 216 # define OMAP_INT_1610_CF               43
 217 # define OMAP_INT_1610_WAKE_UP_REQ      46
 218 # define OMAP_INT_1610_GPIO_BANK4       48
 219 # define OMAP_INT_1610_SPI              49
 220 # define OMAP_INT_1610_DMA_CH6          53
 221 # define OMAP_INT_1610_DMA_CH7          54
 222 # define OMAP_INT_1610_DMA_CH8          55
 223 # define OMAP_INT_1610_DMA_CH9          56
 224 # define OMAP_INT_1610_DMA_CH10         57
 225 # define OMAP_INT_1610_DMA_CH11         58
 226 # define OMAP_INT_1610_DMA_CH12         59
 227 # define OMAP_INT_1610_DMA_CH13         60
 228 # define OMAP_INT_1610_DMA_CH14         61
 229 # define OMAP_INT_1610_DMA_CH15         62
 230 # define OMAP_INT_1610_NAND             63
 231
 232 /*
 233  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 234  */
 235 # define OMAP_INT_730_HW_ERRORS         0
 236 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 237 # define OMAP_INT_730_CFCD              2
 238 # define OMAP_INT_730_CFIREQ            3
 239 # define OMAP_INT_730_I2C               4
 240 # define OMAP_INT_730_PCC               5
 241 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 242 # define OMAP_INT_730_SPI_100K_1        7
 243 # define OMAP_INT_730_SYREN_SPI         8
 244 # define OMAP_INT_730_VLYNQ             9
 245 # define OMAP_INT_730_GPIO_BANK4        10
 246 # define OMAP_INT_730_McBSP1TX          11
 247 # define OMAP_INT_730_McBSP1RX          12
 248 # define OMAP_INT_730_McBSP1RX_OF       13
 249 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 250 # define OMAP_INT_730_UART_MODEM_1      15
 251 # define OMAP_INT_730_MCSI              16
 252 # define OMAP_INT_730_uWireTX           17
 253 # define OMAP_INT_730_uWireRX           18
 254 # define OMAP_INT_730_SMC_CD            19
 255 # define OMAP_INT_730_SMC_IREQ          20
 256 # define OMAP_INT_730_HDQ_1WIRE         21
 257 # define OMAP_INT_730_TIMER32K          22
 258 # define OMAP_INT_730_MMC_SDIO          23
 259 # define OMAP_INT_730_UPLD              24
 260 # define OMAP_INT_730_USB_HHC_1         27
 261 # define OMAP_INT_730_USB_HHC_2         28
 262 # define OMAP_INT_730_USB_GENI          29
 263 # define OMAP_INT_730_USB_OTG           30
 264 # define OMAP_INT_730_CAMERA_IF         31
 265 # define OMAP_INT_730_RNG               32
 266 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 267 # define OMAP_INT_730_DBB_RF_EN         34
 268 # define OMAP_INT_730_MPUIO_KEYPAD      35
 269 # define OMAP_INT_730_SHA1_MD5          36
 270 # define OMAP_INT_730_SPI_100K_2        37
 271 # define OMAP_INT_730_RNG_IDLE          38
 272 # define OMAP_INT_730_MPUIO             39
 273 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 274 # define OMAP_INT_730_LLPC_OE_FALLING   41
 275 # define OMAP_INT_730_LLPC_OE_RISING    42
 276 # define OMAP_INT_730_LLPC_VSYNC        43
 277 # define OMAP_INT_730_WAKE_UP_REQ       46
 278 # define OMAP_INT_730_DMA_CH6           53
 279 # define OMAP_INT_730_DMA_CH7           54
 280 # define OMAP_INT_730_DMA_CH8           55
 281 # define OMAP_INT_730_DMA_CH9           56
 282 # define OMAP_INT_730_DMA_CH10          57
 283 # define OMAP_INT_730_DMA_CH11          58
 284 # define OMAP_INT_730_DMA_CH12          59
 285 # define OMAP_INT_730_DMA_CH13          60
 286 # define OMAP_INT_730_DMA_CH14          61
 287 # define OMAP_INT_730_DMA_CH15          62
 288 # define OMAP_INT_730_NAND              63
 289
 290 /*
 291  * OMAP-24xx common IRQ numbers
 292  */
 293 # define OMAP_INT_24XX_SYS_NIRQ         7
 294 # define OMAP_INT_24XX_SDMA_IRQ0        12
 295 # define OMAP_INT_24XX_SDMA_IRQ1        13
 296 # define OMAP_INT_24XX_SDMA_IRQ2        14
 297 # define OMAP_INT_24XX_SDMA_IRQ3        15
 298 # define OMAP_INT_24XX_CAM_IRQ          24
 299 # define OMAP_INT_24XX_DSS_IRQ          25
 300 # define OMAP_INT_24XX_MAIL_U0_MPU      26
 301 # define OMAP_INT_24XX_DSP_UMA          27
 302 # define OMAP_INT_24XX_DSP_MMU          28
 303 # define OMAP_INT_24XX_GPIO_BANK1       29
 304 # define OMAP_INT_24XX_GPIO_BANK2       30
 305 # define OMAP_INT_24XX_GPIO_BANK3       31
 306 # define OMAP_INT_24XX_GPIO_BANK4       32
 307 # define OMAP_INT_24XX_GPIO_BANK5       33
 308 # define OMAP_INT_24XX_MAIL_U3_MPU      34
 309 # define OMAP_INT_24XX_GPTIMER1         37
 310 # define OMAP_INT_24XX_GPTIMER2         38
 311 # define OMAP_INT_24XX_GPTIMER3         39
 312 # define OMAP_INT_24XX_GPTIMER4         40
 313 # define OMAP_INT_24XX_GPTIMER5         41
 314 # define OMAP_INT_24XX_GPTIMER6         42
 315 # define OMAP_INT_24XX_GPTIMER7         43
 316 # define OMAP_INT_24XX_GPTIMER8         44
 317 # define OMAP_INT_24XX_GPTIMER9         45
 318 # define OMAP_INT_24XX_GPTIMER10        46
 319 # define OMAP_INT_24XX_GPTIMER11        47
 320 # define OMAP_INT_24XX_GPTIMER12        48
 321 # define OMAP_INT_24XX_MCBSP1_IRQ_TX    59
 322 # define OMAP_INT_24XX_MCBSP1_IRQ_RX    60
 323 # define OMAP_INT_24XX_MCBSP2_IRQ_TX    62
 324 # define OMAP_INT_24XX_MCBSP2_IRQ_RX    63
 325 # define OMAP_INT_24XX_UART1_IRQ        72
 326 # define OMAP_INT_24XX_UART2_IRQ        73
 327 # define OMAP_INT_24XX_UART3_IRQ        74
 328 # define OMAP_INT_24XX_USB_IRQ_GEN      75
 329 # define OMAP_INT_24XX_USB_IRQ_NISO     76
 330 # define OMAP_INT_24XX_USB_IRQ_ISO      77
 331 # define OMAP_INT_24XX_USB_IRQ_HGEN     78
 332 # define OMAP_INT_24XX_USB_IRQ_HSOF     79
 333 # define OMAP_INT_24XX_USB_IRQ_OTG      80
 334 # define OMAP_INT_24XX_MMC_IRQ          83
 335 # define OMAP_INT_243X_HS_USB_MC        92
 336 # define OMAP_INT_243X_HS_USB_DMA       93
 337 # define OMAP_INT_243X_CARKIT           94
 338
 339 enum omap_dma_model {
 340     omap_dma_3_1 = 0,
 341     omap_dma_3_2
 342 };
 343
 344 struct omap_dma_s;
 345 struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
 346                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 347                 enum omap_dma_model model);
 348
 349 enum omap_dma_port {
 350     emiff = 0,
 351     emifs,
 352     imif,       /* omap16xx: ocp_t1 */
 353     tipb,
 354     local,      /* omap16xx: ocp_t2 */
 355     tipb_mpui,
 356     omap_dma_port_last,
 357 };
 358
 359 typedef enum {
 360     constant = 0,
 361     post_incremented,
 362     single_index,
 363     double_index,
 364 } omap_dma_addressing_t;
 365
 366 struct omap_dma_lcd_channel_s {
 367     enum omap_dma_port src;
 368     target_phys_addr_t src_f1_top;
 369     target_phys_addr_t src_f1_bottom;
 370     target_phys_addr_t src_f2_top;
 371     target_phys_addr_t src_f2_bottom;
 372
 373     /* Used in OMAP DMA 3.2 gigacell */
 374     unsigned char brust_f1;
 375     unsigned char pack_f1;
 376     unsigned char data_type_f1;
 377     unsigned char brust_f2;
 378     unsigned char pack_f2;
 379     unsigned char data_type_f2;
 380     unsigned char end_prog;
 381     unsigned char repeat;
 382     unsigned char auto_init;
 383     unsigned char priority;
 384     unsigned char fs;
 385     unsigned char running;
 386     unsigned char bs;
 387     unsigned char omap_3_1_compatible_disable;
 388     unsigned char dst;
 389     unsigned char lch_type;
 390     int16_t element_index_f1;
 391     int16_t element_index_f2;
 392     int32_t frame_index_f1;
 393     int32_t frame_index_f2;
 394     uint16_t elements_f1;
 395     uint16_t frames_f1;
 396     uint16_t elements_f2;
 397     uint16_t frames_f2;
 398     omap_dma_addressing_t mode_f1;
 399     omap_dma_addressing_t mode_f2;
 400
 401     /* Destination port is fixed.  */
 402     int interrupts;
 403     int condition;
 404     int dual;
 405
 406     int current_frame;
 407     ram_addr_t phys_framebuffer[2];
 408     qemu_irq irq;
 409     struct omap_mpu_state_s *mpu;
 410 };
 411
 412 /*
 413  * DMA request numbers for OMAP1
 414  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 415  */
 416 # define OMAP_DMA_NO_DEVICE             0
 417 # define OMAP_DMA_MCSI1_TX              1
 418 # define OMAP_DMA_MCSI1_RX              2
 419 # define OMAP_DMA_I2C_RX                3
 420 # define OMAP_DMA_I2C_TX                4
 421 # define OMAP_DMA_EXT_NDMA_REQ0         5
 422 # define OMAP_DMA_EXT_NDMA_REQ1         6
 423 # define OMAP_DMA_UWIRE_TX              7
 424 # define OMAP_DMA_MCBSP1_TX             8
 425 # define OMAP_DMA_MCBSP1_RX             9
 426 # define OMAP_DMA_MCBSP3_TX             10
 427 # define OMAP_DMA_MCBSP3_RX             11
 428 # define OMAP_DMA_UART1_TX              12
 429 # define OMAP_DMA_UART1_RX              13
 430 # define OMAP_DMA_UART2_TX              14
 431 # define OMAP_DMA_UART2_RX              15
 432 # define OMAP_DMA_MCBSP2_TX             16
 433 # define OMAP_DMA_MCBSP2_RX             17
 434 # define OMAP_DMA_UART3_TX              18
 435 # define OMAP_DMA_UART3_RX              19
 436 # define OMAP_DMA_CAMERA_IF_RX          20
 437 # define OMAP_DMA_MMC_TX                21
 438 # define OMAP_DMA_MMC_RX                22
 439 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 440 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 441 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 442 # define OMAP_DMA_USB_W2FC_RX0          26
 443 # define OMAP_DMA_USB_W2FC_RX1          27
 444 # define OMAP_DMA_USB_W2FC_RX2          28
 445 # define OMAP_DMA_USB_W2FC_TX0          29
 446 # define OMAP_DMA_USB_W2FC_TX1          30
 447 # define OMAP_DMA_USB_W2FC_TX2          31
 448
 449 /* These are only for 1610 */
 450 # define OMAP_DMA_CRYPTO_DES_IN         32
 451 # define OMAP_DMA_SPI_TX                33
 452 # define OMAP_DMA_SPI_RX                34
 453 # define OMAP_DMA_CRYPTO_HASH           35
 454 # define OMAP_DMA_CCP_ATTN              36
 455 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 456 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 457 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 458 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 459 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 460 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 461 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 462 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 463 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 464 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 465 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 466 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 467 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 468 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 469 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 470 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 471 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 472 # define OMAP_DMA_MMC2_TX               54
 473 # define OMAP_DMA_MMC2_RX               55
 474 # define OMAP_DMA_CRYPTO_DES_OUT        56
 475
 476 struct omap_mpu_timer_s;
 477 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
 478                 qemu_irq irq, omap_clk clk);
 479
 480 struct omap_watchdog_timer_s;
 481 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
 482                 qemu_irq irq, omap_clk clk);
 483
 484 struct omap_32khz_timer_s;
 485 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
 486                 qemu_irq irq, omap_clk clk);
 487
 488 struct omap_tipb_bridge_s;
 489 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
 490                 qemu_irq abort_irq, omap_clk clk);
 491
 492 struct omap_uart_s;
 493 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
 494                 qemu_irq irq, omap_clk clk, CharDriverState *chr);
 495
 496 struct omap_mpuio_s;
 497 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
 498                 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
 499                 omap_clk clk);
 500 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 501 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 502 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 503
 504 struct omap_gpio_s;
 505 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
 506                 qemu_irq irq, omap_clk clk);
 507 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
 508 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
 509
 510 struct uwire_slave_s {
 511     uint16_t (*receive)(void *opaque);
 512     void (*send)(void *opaque, uint16_t data);
 513     void *opaque;
 514 };
 515 struct omap_uwire_s;
 516 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
 517                 qemu_irq *irq, qemu_irq dma, omap_clk clk);
 518 void omap_uwire_attach(struct omap_uwire_s *s,
 519                 struct uwire_slave_s *slave, int chipselect);
 520
 521 struct omap_rtc_s;
 522 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
 523                 qemu_irq *irq, omap_clk clk);
 524
 525 struct i2s_codec_s {
 526     void *opaque;
 527
 528     /* The CPU can call this if it is generating the clock signal on the
 529      * i2s port.  The CODEC can ignore it if it is set up as a clock
 530      * master and generates its own clock.  */
 531     void (*set_rate)(void *opaque, int in, int out);
 532
 533     void (*tx_swallow)(void *opaque);
 534     qemu_irq rx_swallow;
 535     qemu_irq tx_start;
 536
 537     int tx_rate;
 538     int cts;
 539     int rx_rate;
 540     int rts;
 541
 542     struct i2s_fifo_s {
 543         uint8_t *fifo;
 544         int len;
 545         int start;
 546         int size;
 547     } in, out;
 548 };
 549 struct omap_mcbsp_s;
 550 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
 551                 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
 552 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
 553
 554 struct omap_lpg_s;
 555 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
 556
 557 /* omap_lcdc.c */
 558 struct omap_lcd_panel_s;
 559 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 560 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
 561                 struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
 562                 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
 563
 564 /* omap_mmc.c */
 565 struct omap_mmc_s;
 566 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
 567                 BlockDriverState *bd,
 568                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 569 void omap_mmc_reset(struct omap_mmc_s *s);
 570 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
 571
 572 /* omap_i2c.c */
 573 struct omap_i2c_s;
 574 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
 575                 qemu_irq irq, qemu_irq *dma, omap_clk clk);
 576 void omap_i2c_reset(struct omap_i2c_s *s);
 577 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
 578
 579 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 580 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 581 # define cpu_is_omap15xx(cpu)           \
 582         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 583 # define cpu_class_omap1(cpu)           1
 584
 585 struct omap_mpu_state_s {
 586     enum omap1_mpu_model {
 587         omap310,
 588         omap1510,
 589     } mpu_model;
 590
 591     CPUState *env;
 592
 593     qemu_irq *irq[2];
 594     qemu_irq *drq;
 595
 596     qemu_irq wakeup;
 597
 598     struct omap_dma_port_if_s {
 599         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 600                         target_phys_addr_t offset);
 601         void (*write[3])(struct omap_mpu_state_s *s,
 602                         target_phys_addr_t offset, uint32_t value);
 603         int (*addr_valid)(struct omap_mpu_state_s *s,
 604                         target_phys_addr_t addr);
 605     } port[omap_dma_port_last];
 606
 607     unsigned long sdram_size;
 608     unsigned long sram_size;
 609
 610     /* MPUI-TIPB peripherals */
 611     struct omap_uart_s *uart[3];
 612
 613     struct omap_gpio_s *gpio;
 614
 615     struct omap_mcbsp_s *mcbsp1;
 616     struct omap_mcbsp_s *mcbsp3;
 617
 618     /* MPU public TIPB peripherals */
 619     struct omap_32khz_timer_s *os_timer;
 620
 621     struct omap_mmc_s *mmc;
 622
 623     struct omap_mpuio_s *mpuio;
 624
 625     struct omap_uwire_s *microwire;
 626
 627     struct {
 628         uint8_t output;
 629         uint8_t level;
 630         uint8_t enable;
 631         int clk;
 632     } pwl;
 633
 634     struct {
 635         uint8_t frc;
 636         uint8_t vrc;
 637         uint8_t gcr;
 638         omap_clk clk;
 639     } pwt;
 640
 641     struct omap_i2c_s *i2c;
 642
 643     struct omap_rtc_s *rtc;
 644
 645     struct omap_mcbsp_s *mcbsp2;
 646
 647     struct omap_lpg_s *led[2];
 648
 649     /* MPU private TIPB peripherals */
 650     struct omap_intr_handler_s *ih[2];
 651
 652     struct omap_dma_s *dma;
 653
 654     struct omap_mpu_timer_s *timer[3];
 655     struct omap_watchdog_timer_s *wdt;
 656
 657     struct omap_lcd_panel_s *lcd;
 658
 659     target_phys_addr_t ulpd_pm_base;
 660     uint32_t ulpd_pm_regs[21];
 661     int64_t ulpd_gauge_start;
 662
 663     target_phys_addr_t pin_cfg_base;
 664     uint32_t func_mux_ctrl[14];
 665     uint32_t comp_mode_ctrl[1];
 666     uint32_t pull_dwn_ctrl[4];
 667     uint32_t gate_inh_ctrl[1];
 668     uint32_t voltage_ctrl[1];
 669     uint32_t test_dbg_ctrl[1];
 670     uint32_t mod_conf_ctrl[1];
 671     int compat1509;
 672
 673     uint32_t mpui_ctrl;
 674     target_phys_addr_t mpui_base;
 675
 676     struct omap_tipb_bridge_s *private_tipb;
 677     struct omap_tipb_bridge_s *public_tipb;
 678
 679     target_phys_addr_t tcmi_base;
 680     uint32_t tcmi_regs[17];
 681
 682     struct dpll_ctl_s {
 683         target_phys_addr_t base;
 684         uint16_t mode;
 685         omap_clk dpll;
 686     } dpll[3];
 687
 688     omap_clk clks;
 689     struct {
 690         target_phys_addr_t mpu_base;
 691         target_phys_addr_t dsp_base;
 692
 693         int cold_start;
 694         int clocking_scheme;
 695         uint16_t arm_ckctl;
 696         uint16_t arm_idlect1;
 697         uint16_t arm_idlect2;
 698         uint16_t arm_ewupct;
 699         uint16_t arm_rstct1;
 700         uint16_t arm_rstct2;
 701         uint16_t arm_ckout1;
 702         int dpll1_mode;
 703         uint16_t dsp_idlect1;
 704         uint16_t dsp_idlect2;
 705         uint16_t dsp_rstct2;
 706     } clkm;
 707 } *omap310_mpu_init(unsigned long sdram_size,
 708                 DisplayState *ds, const char *core);
 709
 710 # if TARGET_PHYS_ADDR_BITS == 32
 711 #  define OMAP_FMT_plx "%#08x"
 712 # elif TARGET_PHYS_ADDR_BITS == 64
 713 #  define OMAP_FMT_plx "%#08" PRIx64
 714 # else
 715 #  error TARGET_PHYS_ADDR_BITS undefined
 716 # endif
 717
 718 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
 719 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
 720                 uint32_t value);
 721 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
 722 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
 723                 uint32_t value);
 724 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
 725 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
 726                 uint32_t value);
 727
 728 # define OMAP_BAD_REG(paddr)            \
 729         printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
 730 # define OMAP_RO_REG(paddr)             \
 731         printf("%s: Read-only register " OMAP_FMT_plx "\n",     \
 732                         __FUNCTION__, paddr)
 733
 734 # define TCMI_VERBOSE                   1
 735 //# define MEM_VERBOSE                  1
 736
 737 # ifdef TCMI_VERBOSE
 738 #  define OMAP_8B_REG(paddr)            \
 739         printf("%s: 8-bit register " OMAP_FMT_plx "\n", \
 740                         __FUNCTION__, paddr)
 741 #  define OMAP_16B_REG(paddr)           \
 742         printf("%s: 16-bit register " OMAP_FMT_plx "\n",        \
 743                         __FUNCTION__, paddr)
 744 #  define OMAP_32B_REG(paddr)           \
 745         printf("%s: 32-bit register " OMAP_FMT_plx "\n",        \
 746                         __FUNCTION__, paddr)
 747 # else
 748 #  define OMAP_8B_REG(paddr)
 749 #  define OMAP_16B_REG(paddr)
 750 #  define OMAP_32B_REG(paddr)
 751 # endif
 752
 753 # define OMAP_MPUI_REG_MASK             0x000007ff
 754
 755 # ifdef MEM_VERBOSE
 756 struct io_fn {
 757     CPUReadMemoryFunc **mem_read;
 758     CPUWriteMemoryFunc **mem_write;
 759     void *opaque;
 760     int in;
 761 };
 762
 763 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
 764 {
 765     struct io_fn *s = opaque;
 766     uint32_t ret;
 767
 768     s->in ++;
 769     ret = s->mem_read[0](s->opaque, addr);
 770     s->in --;
 771     if (!s->in)
 772         fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
 773     return ret;
 774 }
 775 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
 776 {
 777     struct io_fn *s = opaque;
 778     uint32_t ret;
 779
 780     s->in ++;
 781     ret = s->mem_read[1](s->opaque, addr);
 782     s->in --;
 783     if (!s->in)
 784         fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
 785     return ret;
 786 }
 787 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
 788 {
 789     struct io_fn *s = opaque;
 790     uint32_t ret;
 791
 792     s->in ++;
 793     ret = s->mem_read[2](s->opaque, addr);
 794     s->in --;
 795     if (!s->in)
 796         fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
 797     return ret;
 798 }
 799 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
 800 {
 801     struct io_fn *s = opaque;
 802
 803     if (!s->in)
 804         fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
 805     s->in ++;
 806     s->mem_write[0](s->opaque, addr, value);
 807     s->in --;
 808 }
 809 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
 810 {
 811     struct io_fn *s = opaque;
 812
 813     if (!s->in)
 814         fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
 815     s->in ++;
 816     s->mem_write[1](s->opaque, addr, value);
 817     s->in --;
 818 }
 819 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
 820 {
 821     struct io_fn *s = opaque;
 822
 823     if (!s->in)
 824         fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
 825     s->in ++;
 826     s->mem_write[2](s->opaque, addr, value);
 827     s->in --;
 828 }
 829
 830 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
 831 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
 832
 833 inline static int debug_register_io_memory(int io_index,
 834                 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
 835                 void *opaque)
 836 {
 837     struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
 838
 839     s->mem_read = mem_read;
 840     s->mem_write = mem_write;
 841     s->opaque = opaque;
 842     s->in = 0;
 843     return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
 844 }
 845 #  define cpu_register_io_memory        debug_register_io_memory
 846 # endif
 847
 848 /* Not really omap specific, but is the only thing that uses the
 849    uwire interface.  */
 850 /* tsc210x.c */
 851 struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
 852 struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
 853
 854 #endif /* hw_omap_h */