2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "host-utils.h"
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
28 void do_raise_exception_err (uint32_t exception
, int error_code
)
31 if (logfile
&& exception
< 0x100)
32 fprintf(logfile
, "%s: %d %d\n", __func__
, exception
, error_code
);
34 env
->exception_index
= exception
;
35 env
->error_code
= error_code
;
40 void do_raise_exception (uint32_t exception
)
42 do_raise_exception_err(exception
, 0);
45 void do_interrupt_restart (void)
47 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
48 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
49 !(env
->hflags
& MIPS_HFLAG_DM
) &&
50 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
51 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
)) {
52 env
->CP0_Cause
&= ~(0x1f << CP0Ca_EC
);
53 do_raise_exception(EXCP_EXT_INTERRUPT
);
57 void do_restore_state (void *pc_ptr
)
60 unsigned long pc
= (unsigned long) pc_ptr
;
64 cpu_restore_state (tb
, env
, pc
, NULL
);
78 #if defined(TARGET_MIPS64)
79 #if TARGET_LONG_BITS > HOST_LONG_BITS
80 /* Those might call libgcc functions. */
93 T0
= (int64_t)T0
>> T1
;
98 T0
= (int64_t)T0
>> (T1
+ 32);
106 void do_dsrl32 (void)
108 T0
= T0
>> (T1
+ 32);
116 tmp
= T0
<< (0x40 - T1
);
117 T0
= (T0
>> T1
) | tmp
;
121 void do_drotr32 (void)
125 tmp
= T0
<< (0x40 - (32 + T1
));
126 T0
= (T0
>> (32 + T1
)) | tmp
;
131 T0
= T1
<< (T0
& 0x3F);
136 T0
= (int64_t)T1
>> (T0
& 0x3F);
141 T0
= T1
>> (T0
& 0x3F);
144 void do_drotrv (void)
150 tmp
= T1
<< (0x40 - T0
);
151 T0
= (T1
>> T0
) | tmp
;
156 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
168 #endif /* TARGET_MIPS64 */
170 /* 64 bits arithmetic for 32 bits hosts */
171 #if TARGET_LONG_BITS > HOST_LONG_BITS
172 static always_inline
uint64_t get_HILO (void)
174 return (env
->HI
[env
->current_tc
][0] << 32) | (uint32_t)env
->LO
[env
->current_tc
][0];
177 static always_inline
void set_HILO (uint64_t HILO
)
179 env
->LO
[env
->current_tc
][0] = (int32_t)HILO
;
180 env
->HI
[env
->current_tc
][0] = (int32_t)(HILO
>> 32);
183 static always_inline
void set_HIT0_LO (uint64_t HILO
)
185 env
->LO
[env
->current_tc
][0] = (int32_t)(HILO
& 0xFFFFFFFF);
186 T0
= env
->HI
[env
->current_tc
][0] = (int32_t)(HILO
>> 32);
189 static always_inline
void set_HI_LOT0 (uint64_t HILO
)
191 T0
= env
->LO
[env
->current_tc
][0] = (int32_t)(HILO
& 0xFFFFFFFF);
192 env
->HI
[env
->current_tc
][0] = (int32_t)(HILO
>> 32);
197 set_HILO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
202 set_HILO((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
209 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
210 set_HILO((int64_t)get_HILO() + tmp
);
217 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
218 set_HILO(get_HILO() + tmp
);
225 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
226 set_HILO((int64_t)get_HILO() - tmp
);
233 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
234 set_HILO(get_HILO() - tmp
);
237 /* Multiplication variants of the vr54xx. */
240 set_HI_LOT0(0 - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
245 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
250 set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
253 void do_macchi (void)
255 set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
260 set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
263 void do_macchiu (void)
265 set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
270 set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
273 void do_msachi (void)
275 set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
280 set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
283 void do_msachiu (void)
285 set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
290 set_HIT0_LO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
293 void do_mulhiu (void)
295 set_HIT0_LO((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
298 void do_mulshi (void)
300 set_HIT0_LO(0 - ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
));
303 void do_mulshiu (void)
305 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
));
307 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
309 #ifdef CONFIG_USER_ONLY
310 void do_mfc0_random (void)
312 cpu_abort(env
, "mfc0 random\n");
315 void do_mfc0_count (void)
317 cpu_abort(env
, "mfc0 count\n");
320 void cpu_mips_store_count(CPUState
*env
, uint32_t value
)
322 cpu_abort(env
, "mtc0 count\n");
325 void cpu_mips_store_compare(CPUState
*env
, uint32_t value
)
327 cpu_abort(env
, "mtc0 compare\n");
330 void cpu_mips_start_count(CPUState
*env
)
332 cpu_abort(env
, "start count\n");
335 void cpu_mips_stop_count(CPUState
*env
)
337 cpu_abort(env
, "stop count\n");
340 void cpu_mips_update_irq(CPUState
*env
)
342 cpu_abort(env
, "mtc0 status / mtc0 cause\n");
345 void do_mtc0_status_debug(uint32_t old
, uint32_t val
)
347 cpu_abort(env
, "mtc0 status debug\n");
350 void do_mtc0_status_irqraise_debug (void)
352 cpu_abort(env
, "mtc0 status irqraise debug\n");
355 void cpu_mips_tlb_flush (CPUState
*env
, int flush_global
)
357 cpu_abort(env
, "mips_tlb_flush\n");
363 void do_mfc0_mvpcontrol (void)
365 T0
= env
->mvp
->CP0_MVPControl
;
368 void do_mfc0_mvpconf0 (void)
370 T0
= env
->mvp
->CP0_MVPConf0
;
373 void do_mfc0_mvpconf1 (void)
375 T0
= env
->mvp
->CP0_MVPConf1
;
378 void do_mfc0_random (void)
380 T0
= (int32_t)cpu_mips_get_random(env
);
383 void do_mfc0_tcstatus (void)
385 T0
= env
->CP0_TCStatus
[env
->current_tc
];
388 void do_mftc0_tcstatus(void)
390 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
392 T0
= env
->CP0_TCStatus
[other_tc
];
395 void do_mfc0_tcbind (void)
397 T0
= env
->CP0_TCBind
[env
->current_tc
];
400 void do_mftc0_tcbind(void)
402 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
404 T0
= env
->CP0_TCBind
[other_tc
];
407 void do_mfc0_tcrestart (void)
409 T0
= env
->PC
[env
->current_tc
];
412 void do_mftc0_tcrestart(void)
414 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
416 T0
= env
->PC
[other_tc
];
419 void do_mfc0_tchalt (void)
421 T0
= env
->CP0_TCHalt
[env
->current_tc
];
424 void do_mftc0_tchalt(void)
426 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
428 T0
= env
->CP0_TCHalt
[other_tc
];
431 void do_mfc0_tccontext (void)
433 T0
= env
->CP0_TCContext
[env
->current_tc
];
436 void do_mftc0_tccontext(void)
438 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
440 T0
= env
->CP0_TCContext
[other_tc
];
443 void do_mfc0_tcschedule (void)
445 T0
= env
->CP0_TCSchedule
[env
->current_tc
];
448 void do_mftc0_tcschedule(void)
450 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
452 T0
= env
->CP0_TCSchedule
[other_tc
];
455 void do_mfc0_tcschefback (void)
457 T0
= env
->CP0_TCScheFBack
[env
->current_tc
];
460 void do_mftc0_tcschefback(void)
462 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
464 T0
= env
->CP0_TCScheFBack
[other_tc
];
467 void do_mfc0_count (void)
469 T0
= (int32_t)cpu_mips_get_count(env
);
472 void do_mftc0_entryhi(void)
474 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
476 T0
= (env
->CP0_EntryHi
& ~0xff) | (env
->CP0_TCStatus
[other_tc
] & 0xff);
479 void do_mftc0_status(void)
481 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
482 uint32_t tcstatus
= env
->CP0_TCStatus
[other_tc
];
484 T0
= env
->CP0_Status
& ~0xf1000018;
485 T0
|= tcstatus
& (0xf << CP0TCSt_TCU0
);
486 T0
|= (tcstatus
& (1 << CP0TCSt_TMX
)) >> (CP0TCSt_TMX
- CP0St_MX
);
487 T0
|= (tcstatus
& (0x3 << CP0TCSt_TKSU
)) >> (CP0TCSt_TKSU
- CP0St_KSU
);
490 void do_mfc0_lladdr (void)
492 T0
= (int32_t)env
->CP0_LLAddr
>> 4;
495 void do_mfc0_watchlo (uint32_t sel
)
497 T0
= (int32_t)env
->CP0_WatchLo
[sel
];
500 void do_mfc0_watchhi (uint32_t sel
)
502 T0
= env
->CP0_WatchHi
[sel
];
505 void do_mfc0_debug (void)
508 if (env
->hflags
& MIPS_HFLAG_DM
)
512 void do_mftc0_debug(void)
514 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
516 /* XXX: Might be wrong, check with EJTAG spec. */
517 T0
= (env
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
518 (env
->CP0_Debug_tcstatus
[other_tc
] &
519 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
522 #if defined(TARGET_MIPS64)
523 void do_dmfc0_tcrestart (void)
525 T0
= env
->PC
[env
->current_tc
];
528 void do_dmfc0_tchalt (void)
530 T0
= env
->CP0_TCHalt
[env
->current_tc
];
533 void do_dmfc0_tccontext (void)
535 T0
= env
->CP0_TCContext
[env
->current_tc
];
538 void do_dmfc0_tcschedule (void)
540 T0
= env
->CP0_TCSchedule
[env
->current_tc
];
543 void do_dmfc0_tcschefback (void)
545 T0
= env
->CP0_TCScheFBack
[env
->current_tc
];
548 void do_dmfc0_lladdr (void)
550 T0
= env
->CP0_LLAddr
>> 4;
553 void do_dmfc0_watchlo (uint32_t sel
)
555 T0
= env
->CP0_WatchLo
[sel
];
557 #endif /* TARGET_MIPS64 */
559 void do_mtc0_index (void)
562 unsigned int tmp
= env
->tlb
->nb_tlb
;
568 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (T0
& (num
- 1));
571 void do_mtc0_mvpcontrol (void)
576 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
577 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
579 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
580 mask
|= (1 << CP0MVPCo_STLB
);
581 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (T0
& mask
);
583 // TODO: Enable/disable shared TLB, enable/disable VPEs.
585 env
->mvp
->CP0_MVPControl
= newval
;
588 void do_mtc0_vpecontrol (void)
593 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
594 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
595 newval
= (env
->CP0_VPEControl
& ~mask
) | (T0
& mask
);
597 /* Yield scheduler intercept not implemented. */
598 /* Gating storage scheduler intercept not implemented. */
600 // TODO: Enable/disable TCs.
602 env
->CP0_VPEControl
= newval
;
605 void do_mtc0_vpeconf0 (void)
610 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
611 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
612 mask
|= (0xff << CP0VPEC0_XTC
);
613 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
615 newval
= (env
->CP0_VPEConf0
& ~mask
) | (T0
& mask
);
617 // TODO: TC exclusive handling due to ERL/EXL.
619 env
->CP0_VPEConf0
= newval
;
622 void do_mtc0_vpeconf1 (void)
627 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
628 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
629 (0xff << CP0VPEC1_NCP1
);
630 newval
= (env
->CP0_VPEConf1
& ~mask
) | (T0
& mask
);
632 /* UDI not implemented. */
633 /* CP2 not implemented. */
635 // TODO: Handle FPU (CP1) binding.
637 env
->CP0_VPEConf1
= newval
;
640 void do_mtc0_yqmask (void)
642 /* Yield qualifier inputs not implemented. */
643 env
->CP0_YQMask
= 0x00000000;
646 void do_mtc0_vpeopt (void)
648 env
->CP0_VPEOpt
= T0
& 0x0000ffff;
651 void do_mtc0_entrylo0 (void)
653 /* Large physaddr (PABITS) not implemented */
654 /* 1k pages not implemented */
655 env
->CP0_EntryLo0
= T0
& 0x3FFFFFFF;
658 void do_mtc0_tcstatus (void)
660 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
663 newval
= (env
->CP0_TCStatus
[env
->current_tc
] & ~mask
) | (T0
& mask
);
665 // TODO: Sync with CP0_Status.
667 env
->CP0_TCStatus
[env
->current_tc
] = newval
;
670 void do_mttc0_tcstatus (void)
672 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
674 // TODO: Sync with CP0_Status.
676 env
->CP0_TCStatus
[other_tc
] = T0
;
679 void do_mtc0_tcbind (void)
681 uint32_t mask
= (1 << CP0TCBd_TBE
);
684 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
685 mask
|= (1 << CP0TCBd_CurVPE
);
686 newval
= (env
->CP0_TCBind
[env
->current_tc
] & ~mask
) | (T0
& mask
);
687 env
->CP0_TCBind
[env
->current_tc
] = newval
;
690 void do_mttc0_tcbind (void)
692 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
693 uint32_t mask
= (1 << CP0TCBd_TBE
);
696 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
697 mask
|= (1 << CP0TCBd_CurVPE
);
698 newval
= (env
->CP0_TCBind
[other_tc
] & ~mask
) | (T0
& mask
);
699 env
->CP0_TCBind
[other_tc
] = newval
;
702 void do_mtc0_tcrestart (void)
704 env
->PC
[env
->current_tc
] = T0
;
705 env
->CP0_TCStatus
[env
->current_tc
] &= ~(1 << CP0TCSt_TDS
);
706 env
->CP0_LLAddr
= 0ULL;
707 /* MIPS16 not implemented. */
710 void do_mttc0_tcrestart (void)
712 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
714 env
->PC
[other_tc
] = T0
;
715 env
->CP0_TCStatus
[other_tc
] &= ~(1 << CP0TCSt_TDS
);
716 env
->CP0_LLAddr
= 0ULL;
717 /* MIPS16 not implemented. */
720 void do_mtc0_tchalt (void)
722 env
->CP0_TCHalt
[env
->current_tc
] = T0
& 0x1;
724 // TODO: Halt TC / Restart (if allocated+active) TC.
727 void do_mttc0_tchalt (void)
729 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
731 // TODO: Halt TC / Restart (if allocated+active) TC.
733 env
->CP0_TCHalt
[other_tc
] = T0
;
736 void do_mtc0_tccontext (void)
738 env
->CP0_TCContext
[env
->current_tc
] = T0
;
741 void do_mttc0_tccontext (void)
743 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
745 env
->CP0_TCContext
[other_tc
] = T0
;
748 void do_mtc0_tcschedule (void)
750 env
->CP0_TCSchedule
[env
->current_tc
] = T0
;
753 void do_mttc0_tcschedule (void)
755 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
757 env
->CP0_TCSchedule
[other_tc
] = T0
;
760 void do_mtc0_tcschefback (void)
762 env
->CP0_TCScheFBack
[env
->current_tc
] = T0
;
765 void do_mttc0_tcschefback (void)
767 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
769 env
->CP0_TCScheFBack
[other_tc
] = T0
;
772 void do_mtc0_entrylo1 (void)
774 /* Large physaddr (PABITS) not implemented */
775 /* 1k pages not implemented */
776 env
->CP0_EntryLo1
= T0
& 0x3FFFFFFF;
779 void do_mtc0_context (void)
781 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (T0
& ~0x007FFFFF);
784 void do_mtc0_pagemask (void)
786 /* 1k pages not implemented */
787 env
->CP0_PageMask
= T0
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
790 void do_mtc0_pagegrain (void)
792 /* SmartMIPS not implemented */
793 /* Large physaddr (PABITS) not implemented */
794 /* 1k pages not implemented */
795 env
->CP0_PageGrain
= 0;
798 void do_mtc0_wired (void)
800 env
->CP0_Wired
= T0
% env
->tlb
->nb_tlb
;
803 void do_mtc0_srsconf0 (void)
805 env
->CP0_SRSConf0
|= T0
& env
->CP0_SRSConf0_rw_bitmask
;
808 void do_mtc0_srsconf1 (void)
810 env
->CP0_SRSConf1
|= T0
& env
->CP0_SRSConf1_rw_bitmask
;
813 void do_mtc0_srsconf2 (void)
815 env
->CP0_SRSConf2
|= T0
& env
->CP0_SRSConf2_rw_bitmask
;
818 void do_mtc0_srsconf3 (void)
820 env
->CP0_SRSConf3
|= T0
& env
->CP0_SRSConf3_rw_bitmask
;
823 void do_mtc0_srsconf4 (void)
825 env
->CP0_SRSConf4
|= T0
& env
->CP0_SRSConf4_rw_bitmask
;
828 void do_mtc0_hwrena (void)
830 env
->CP0_HWREna
= T0
& 0x0000000F;
833 void do_mtc0_count (void)
835 cpu_mips_store_count(env
, T0
);
838 void do_mtc0_entryhi (void)
840 target_ulong old
, val
;
842 /* 1k pages not implemented */
843 val
= T0
& ((TARGET_PAGE_MASK
<< 1) | 0xFF);
844 #if defined(TARGET_MIPS64)
847 old
= env
->CP0_EntryHi
;
848 env
->CP0_EntryHi
= val
;
849 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
850 uint32_t tcst
= env
->CP0_TCStatus
[env
->current_tc
] & ~0xff;
851 env
->CP0_TCStatus
[env
->current_tc
] = tcst
| (val
& 0xff);
853 /* If the ASID changes, flush qemu's TLB. */
854 if ((old
& 0xFF) != (val
& 0xFF))
855 cpu_mips_tlb_flush(env
, 1);
858 void do_mttc0_entryhi(void)
860 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
862 env
->CP0_EntryHi
= (env
->CP0_EntryHi
& 0xff) | (T0
& ~0xff);
863 env
->CP0_TCStatus
[other_tc
] = (env
->CP0_TCStatus
[other_tc
] & ~0xff) | (T0
& 0xff);
866 void do_mtc0_compare (void)
868 cpu_mips_store_compare(env
, T0
);
871 void do_mtc0_status (void)
874 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
877 old
= env
->CP0_Status
;
878 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | val
;
880 if (loglevel
& CPU_LOG_EXEC
)
881 do_mtc0_status_debug(old
, val
);
882 cpu_mips_update_irq(env
);
885 void do_mttc0_status(void)
887 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
888 uint32_t tcstatus
= env
->CP0_TCStatus
[other_tc
];
890 env
->CP0_Status
= T0
& ~0xf1000018;
891 tcstatus
= (tcstatus
& ~(0xf << CP0TCSt_TCU0
)) | (T0
& (0xf << CP0St_CU0
));
892 tcstatus
= (tcstatus
& ~(1 << CP0TCSt_TMX
)) | ((T0
& (1 << CP0St_MX
)) << (CP0TCSt_TMX
- CP0St_MX
));
893 tcstatus
= (tcstatus
& ~(0x3 << CP0TCSt_TKSU
)) | ((T0
& (0x3 << CP0St_KSU
)) << (CP0TCSt_TKSU
- CP0St_KSU
));
894 env
->CP0_TCStatus
[other_tc
] = tcstatus
;
897 void do_mtc0_intctl (void)
899 /* vectored interrupts not implemented, no performance counters. */
900 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000002e0) | (T0
& 0x000002e0);
903 void do_mtc0_srsctl (void)
905 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
906 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (T0
& mask
);
909 void do_mtc0_cause (void)
911 uint32_t mask
= 0x00C00300;
912 uint32_t old
= env
->CP0_Cause
;
914 if (env
->insn_flags
& ISA_MIPS32R2
)
915 mask
|= 1 << CP0Ca_DC
;
917 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (T0
& mask
);
919 if ((old
^ env
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
920 if (env
->CP0_Cause
& (1 << CP0Ca_DC
))
921 cpu_mips_stop_count(env
);
923 cpu_mips_start_count(env
);
926 /* Handle the software interrupt as an hardware one, as they
928 if (T0
& CP0Ca_IP_mask
) {
929 cpu_mips_update_irq(env
);
933 void do_mtc0_ebase (void)
935 /* vectored interrupts not implemented */
936 /* Multi-CPU not implemented */
937 env
->CP0_EBase
= 0x80000000 | (T0
& 0x3FFFF000);
940 void do_mtc0_config0 (void)
942 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (T0
& 0x00000007);
945 void do_mtc0_config2 (void)
947 /* tertiary/secondary caches not implemented */
948 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
951 void do_mtc0_watchlo (uint32_t sel
)
953 /* Watch exceptions for instructions, data loads, data stores
955 env
->CP0_WatchLo
[sel
] = (T0
& ~0x7);
958 void do_mtc0_watchhi (uint32_t sel
)
960 env
->CP0_WatchHi
[sel
] = (T0
& 0x40FF0FF8);
961 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & T0
& 0x7);
964 void do_mtc0_xcontext (void)
966 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
967 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (T0
& ~mask
);
970 void do_mtc0_framemask (void)
972 env
->CP0_Framemask
= T0
; /* XXX */
975 void do_mtc0_debug (void)
977 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (T0
& 0x13300120);
978 if (T0
& (1 << CP0DB_DM
))
979 env
->hflags
|= MIPS_HFLAG_DM
;
981 env
->hflags
&= ~MIPS_HFLAG_DM
;
984 void do_mttc0_debug(void)
986 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
988 /* XXX: Might be wrong, check with EJTAG spec. */
989 env
->CP0_Debug_tcstatus
[other_tc
] = T0
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
990 env
->CP0_Debug
= (env
->CP0_Debug
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
991 (T0
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
994 void do_mtc0_performance0 (void)
996 env
->CP0_Performance0
= T0
& 0x000007ff;
999 void do_mtc0_taglo (void)
1001 env
->CP0_TagLo
= T0
& 0xFFFFFCF6;
1004 void do_mtc0_datalo (void)
1006 env
->CP0_DataLo
= T0
; /* XXX */
1009 void do_mtc0_taghi (void)
1011 env
->CP0_TagHi
= T0
; /* XXX */
1014 void do_mtc0_datahi (void)
1016 env
->CP0_DataHi
= T0
; /* XXX */
1019 void do_mtc0_status_debug(uint32_t old
, uint32_t val
)
1021 fprintf(logfile
, "Status %08x (%08x) => %08x (%08x) Cause %08x",
1022 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1023 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1025 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1026 case MIPS_HFLAG_UM
: fputs(", UM\n", logfile
); break;
1027 case MIPS_HFLAG_SM
: fputs(", SM\n", logfile
); break;
1028 case MIPS_HFLAG_KM
: fputs("\n", logfile
); break;
1029 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1033 void do_mtc0_status_irqraise_debug(void)
1035 fprintf(logfile
, "Raise pending IRQs\n");
1037 #endif /* !CONFIG_USER_ONLY */
1039 /* MIPS MT functions */
1040 void do_mftgpr(uint32_t sel
)
1042 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1044 T0
= env
->gpr
[other_tc
][sel
];
1047 void do_mftlo(uint32_t sel
)
1049 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1051 T0
= env
->LO
[other_tc
][sel
];
1054 void do_mfthi(uint32_t sel
)
1056 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1058 T0
= env
->HI
[other_tc
][sel
];
1061 void do_mftacx(uint32_t sel
)
1063 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1065 T0
= env
->ACX
[other_tc
][sel
];
1068 void do_mftdsp(void)
1070 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1072 T0
= env
->DSPControl
[other_tc
];
1075 void do_mttgpr(uint32_t sel
)
1077 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1079 T0
= env
->gpr
[other_tc
][sel
];
1082 void do_mttlo(uint32_t sel
)
1084 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1086 T0
= env
->LO
[other_tc
][sel
];
1089 void do_mtthi(uint32_t sel
)
1091 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1093 T0
= env
->HI
[other_tc
][sel
];
1096 void do_mttacx(uint32_t sel
)
1098 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1100 T0
= env
->ACX
[other_tc
][sel
];
1103 void do_mttdsp(void)
1105 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1107 T0
= env
->DSPControl
[other_tc
];
1110 /* MIPS MT functions */
1143 // TODO: store to TC register
1149 /* No scheduling policy implemented. */
1151 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1152 env
->CP0_TCStatus
[env
->current_tc
] & (1 << CP0TCSt_DT
)) {
1153 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1154 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1155 do_raise_exception(EXCP_THREAD
);
1158 } else if (T0
== 0) {
1159 if (0 /* TODO: TC underflow */) {
1160 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1161 do_raise_exception(EXCP_THREAD
);
1163 // TODO: Deallocate TC
1165 } else if (T0
> 0) {
1166 /* Yield qualifier inputs not implemented. */
1167 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1168 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1169 do_raise_exception(EXCP_THREAD
);
1171 T0
= env
->CP0_YQMask
;
1175 void fpu_handle_exception(void)
1177 #ifdef CONFIG_SOFTFLOAT
1178 int flags
= get_float_exception_flags(&env
->fpu
->fp_status
);
1179 unsigned int cpuflags
= 0, enable
, cause
= 0;
1181 enable
= GET_FP_ENABLE(env
->fpu
->fcr31
);
1183 /* determine current flags */
1184 if (flags
& float_flag_invalid
) {
1185 cpuflags
|= FP_INVALID
;
1186 cause
|= FP_INVALID
& enable
;
1188 if (flags
& float_flag_divbyzero
) {
1189 cpuflags
|= FP_DIV0
;
1190 cause
|= FP_DIV0
& enable
;
1192 if (flags
& float_flag_overflow
) {
1193 cpuflags
|= FP_OVERFLOW
;
1194 cause
|= FP_OVERFLOW
& enable
;
1196 if (flags
& float_flag_underflow
) {
1197 cpuflags
|= FP_UNDERFLOW
;
1198 cause
|= FP_UNDERFLOW
& enable
;
1200 if (flags
& float_flag_inexact
) {
1201 cpuflags
|= FP_INEXACT
;
1202 cause
|= FP_INEXACT
& enable
;
1204 SET_FP_FLAGS(env
->fpu
->fcr31
, cpuflags
);
1205 SET_FP_CAUSE(env
->fpu
->fcr31
, cause
);
1207 SET_FP_FLAGS(env
->fpu
->fcr31
, 0);
1208 SET_FP_CAUSE(env
->fpu
->fcr31
, 0);
1212 #ifndef CONFIG_USER_ONLY
1213 /* TLB management */
1214 void cpu_mips_tlb_flush (CPUState
*env
, int flush_global
)
1216 /* Flush qemu's TLB and discard all shadowed entries. */
1217 tlb_flush (env
, flush_global
);
1218 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
1221 static void r4k_mips_tlb_flush_extra (CPUState
*env
, int first
)
1223 /* Discard entries from env->tlb[first] onwards. */
1224 while (env
->tlb
->tlb_in_use
> first
) {
1225 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1229 static void r4k_fill_tlb (int idx
)
1233 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1234 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1235 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1236 #if defined(TARGET_MIPS64)
1237 tlb
->VPN
&= env
->SEGMask
;
1239 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1240 tlb
->PageMask
= env
->CP0_PageMask
;
1241 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1242 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1243 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1244 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1245 tlb
->PFN
[0] = (env
->CP0_EntryLo0
>> 6) << 12;
1246 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1247 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1248 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1249 tlb
->PFN
[1] = (env
->CP0_EntryLo1
>> 6) << 12;
1252 void r4k_do_tlbwi (void)
1254 /* Discard cached TLB entries. We could avoid doing this if the
1255 tlbwi is just upgrading access permissions on the current entry;
1256 that might be a further win. */
1257 r4k_mips_tlb_flush_extra (env
, env
->tlb
->nb_tlb
);
1259 r4k_invalidate_tlb(env
, env
->CP0_Index
% env
->tlb
->nb_tlb
, 0);
1260 r4k_fill_tlb(env
->CP0_Index
% env
->tlb
->nb_tlb
);
1263 void r4k_do_tlbwr (void)
1265 int r
= cpu_mips_get_random(env
);
1267 r4k_invalidate_tlb(env
, r
, 1);
1271 void r4k_do_tlbp (void)
1280 ASID
= env
->CP0_EntryHi
& 0xFF;
1281 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
1282 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1283 /* 1k pages are not supported. */
1284 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1285 tag
= env
->CP0_EntryHi
& ~mask
;
1286 VPN
= tlb
->VPN
& ~mask
;
1287 /* Check ASID, virtual page number & size */
1288 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1294 if (i
== env
->tlb
->nb_tlb
) {
1295 /* No match. Discard any shadow entries, if any of them match. */
1296 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
1297 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1298 /* 1k pages are not supported. */
1299 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1300 tag
= env
->CP0_EntryHi
& ~mask
;
1301 VPN
= tlb
->VPN
& ~mask
;
1302 /* Check ASID, virtual page number & size */
1303 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1304 r4k_mips_tlb_flush_extra (env
, i
);
1309 env
->CP0_Index
|= 0x80000000;
1313 void r4k_do_tlbr (void)
1318 ASID
= env
->CP0_EntryHi
& 0xFF;
1319 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[env
->CP0_Index
% env
->tlb
->nb_tlb
];
1321 /* If this will change the current ASID, flush qemu's TLB. */
1322 if (ASID
!= tlb
->ASID
)
1323 cpu_mips_tlb_flush (env
, 1);
1325 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
1327 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
1328 env
->CP0_PageMask
= tlb
->PageMask
;
1329 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
1330 (tlb
->C0
<< 3) | (tlb
->PFN
[0] >> 6);
1331 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
1332 (tlb
->C1
<< 3) | (tlb
->PFN
[1] >> 6);
1335 #endif /* !CONFIG_USER_ONLY */
1337 void dump_ldst (const unsigned char *func
)
1340 fprintf(logfile
, "%s => " TARGET_FMT_lx
" " TARGET_FMT_lx
"\n", __func__
, T0
, T1
);
1346 fprintf(logfile
, "%s " TARGET_FMT_lx
" at " TARGET_FMT_lx
" (" TARGET_FMT_lx
")\n", __func__
,
1347 T1
, T0
, env
->CP0_LLAddr
);
1351 void debug_pre_eret (void)
1353 fprintf(logfile
, "ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
1354 env
->PC
[env
->current_tc
], env
->CP0_EPC
);
1355 if (env
->CP0_Status
& (1 << CP0St_ERL
))
1356 fprintf(logfile
, " ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
1357 if (env
->hflags
& MIPS_HFLAG_DM
)
1358 fprintf(logfile
, " DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
1359 fputs("\n", logfile
);
1362 void debug_post_eret (void)
1364 fprintf(logfile
, " => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
1365 env
->PC
[env
->current_tc
], env
->CP0_EPC
);
1366 if (env
->CP0_Status
& (1 << CP0St_ERL
))
1367 fprintf(logfile
, " ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
1368 if (env
->hflags
& MIPS_HFLAG_DM
)
1369 fprintf(logfile
, " DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
1370 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1371 case MIPS_HFLAG_UM
: fputs(", UM\n", logfile
); break;
1372 case MIPS_HFLAG_SM
: fputs(", SM\n", logfile
); break;
1373 case MIPS_HFLAG_KM
: fputs("\n", logfile
); break;
1374 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1378 void do_pmon (int function
)
1382 case 2: /* TODO: char inbyte(int waitflag); */
1383 if (env
->gpr
[env
->current_tc
][4] == 0)
1384 env
->gpr
[env
->current_tc
][2] = -1;
1386 case 11: /* TODO: char inbyte (void); */
1387 env
->gpr
[env
->current_tc
][2] = -1;
1391 printf("%c", (char)(env
->gpr
[env
->current_tc
][4] & 0xFF));
1397 unsigned char *fmt
= (void *)(unsigned long)env
->gpr
[env
->current_tc
][4];
1404 #if !defined(CONFIG_USER_ONLY)
1406 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
);
1408 #define MMUSUFFIX _mmu
1409 #define ALIGNED_ONLY
1412 #include "softmmu_template.h"
1415 #include "softmmu_template.h"
1418 #include "softmmu_template.h"
1421 #include "softmmu_template.h"
1423 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
1425 env
->CP0_BadVAddr
= addr
;
1426 do_restore_state (retaddr
);
1427 do_raise_exception ((is_write
== 1) ? EXCP_AdES
: EXCP_AdEL
);
1430 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
1432 TranslationBlock
*tb
;
1433 CPUState
*saved_env
;
1437 /* XXX: hack to restore env in all cases, even if not called from
1440 env
= cpu_single_env
;
1441 ret
= cpu_mips_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
1444 /* now we have a real cpu fault */
1445 pc
= (unsigned long)retaddr
;
1446 tb
= tb_find_pc(pc
);
1448 /* the PC is inside the translated code. It means that we have
1449 a virtual CPU fault */
1450 cpu_restore_state(tb
, env
, pc
, NULL
);
1453 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1458 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
1462 do_raise_exception(EXCP_IBE
);
1464 do_raise_exception(EXCP_DBE
);
1466 #endif /* !CONFIG_USER_ONLY */
1468 /* Complex FPU operations which may need stack space. */
1470 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1471 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1472 #define FLOAT_TWO32 make_float32(1 << 30)
1473 #define FLOAT_TWO64 make_float64(1ULL << 62)
1474 #define FLOAT_QNAN32 0x7fbfffff
1475 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1476 #define FLOAT_SNAN32 0x7fffffff
1477 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1479 /* convert MIPS rounding mode in FCR31 to IEEE library */
1480 unsigned int ieee_rm
[] = {
1481 float_round_nearest_even
,
1482 float_round_to_zero
,
1487 #define RESTORE_ROUNDING_MODE \
1488 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
1490 void do_cfc1 (uint32_t reg
)
1494 T0
= (int32_t)env
->fpu
->fcr0
;
1497 T0
= ((env
->fpu
->fcr31
>> 24) & 0xfe) | ((env
->fpu
->fcr31
>> 23) & 0x1);
1500 T0
= env
->fpu
->fcr31
& 0x0003f07c;
1503 T0
= (env
->fpu
->fcr31
& 0x00000f83) | ((env
->fpu
->fcr31
>> 22) & 0x4);
1506 T0
= (int32_t)env
->fpu
->fcr31
;
1511 void do_ctc1 (uint32_t reg
)
1515 if (T0
& 0xffffff00)
1517 env
->fpu
->fcr31
= (env
->fpu
->fcr31
& 0x017fffff) | ((T0
& 0xfe) << 24) |
1521 if (T0
& 0x007c0000)
1523 env
->fpu
->fcr31
= (env
->fpu
->fcr31
& 0xfffc0f83) | (T0
& 0x0003f07c);
1526 if (T0
& 0x007c0000)
1528 env
->fpu
->fcr31
= (env
->fpu
->fcr31
& 0xfefff07c) | (T0
& 0x00000f83) |
1532 if (T0
& 0x007c0000)
1534 env
->fpu
->fcr31
= T0
;
1539 /* set rounding mode */
1540 RESTORE_ROUNDING_MODE
;
1541 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1542 if ((GET_FP_ENABLE(env
->fpu
->fcr31
) | 0x20) & GET_FP_CAUSE(env
->fpu
->fcr31
))
1543 do_raise_exception(EXCP_FPE
);
1546 static always_inline
char ieee_ex_to_mips(char xcpt
)
1548 return (xcpt
& float_flag_inexact
) >> 5 |
1549 (xcpt
& float_flag_underflow
) >> 3 |
1550 (xcpt
& float_flag_overflow
) >> 1 |
1551 (xcpt
& float_flag_divbyzero
) << 1 |
1552 (xcpt
& float_flag_invalid
) << 4;
1555 static always_inline
char mips_ex_to_ieee(char xcpt
)
1557 return (xcpt
& FP_INEXACT
) << 5 |
1558 (xcpt
& FP_UNDERFLOW
) << 3 |
1559 (xcpt
& FP_OVERFLOW
) << 1 |
1560 (xcpt
& FP_DIV0
) >> 1 |
1561 (xcpt
& FP_INVALID
) >> 4;
1564 static always_inline
void update_fcr31(void)
1566 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->fpu
->fp_status
));
1568 SET_FP_CAUSE(env
->fpu
->fcr31
, tmp
);
1569 if (GET_FP_ENABLE(env
->fpu
->fcr31
) & tmp
)
1570 do_raise_exception(EXCP_FPE
);
1572 UPDATE_FP_FLAGS(env
->fpu
->fcr31
, tmp
);
1575 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
1579 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1580 FDT2
= float32_to_float64(FST0
, &env
->fpu
->fp_status
);
1585 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1586 FDT2
= int32_to_float64(WT0
, &env
->fpu
->fp_status
);
1591 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1592 FDT2
= int64_to_float64(DT0
, &env
->fpu
->fp_status
);
1597 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1598 DT2
= float64_to_int64(FDT0
, &env
->fpu
->fp_status
);
1600 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1605 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1606 DT2
= float32_to_int64(FST0
, &env
->fpu
->fp_status
);
1608 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1614 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1615 FST2
= int32_to_float32(WT0
, &env
->fpu
->fp_status
);
1616 FSTH2
= int32_to_float32(WTH0
, &env
->fpu
->fp_status
);
1621 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1622 WT2
= float32_to_int32(FST0
, &env
->fpu
->fp_status
);
1623 WTH2
= float32_to_int32(FSTH0
, &env
->fpu
->fp_status
);
1625 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1630 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1631 FST2
= float64_to_float32(FDT0
, &env
->fpu
->fp_status
);
1636 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1637 FST2
= int32_to_float32(WT0
, &env
->fpu
->fp_status
);
1642 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1643 FST2
= int64_to_float32(DT0
, &env
->fpu
->fp_status
);
1648 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1654 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1660 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1661 WT2
= float32_to_int32(FST0
, &env
->fpu
->fp_status
);
1663 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1668 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1669 WT2
= float64_to_int32(FDT0
, &env
->fpu
->fp_status
);
1671 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1677 set_float_rounding_mode(float_round_nearest_even
, &env
->fpu
->fp_status
);
1678 DT2
= float64_to_int64(FDT0
, &env
->fpu
->fp_status
);
1679 RESTORE_ROUNDING_MODE
;
1681 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1686 set_float_rounding_mode(float_round_nearest_even
, &env
->fpu
->fp_status
);
1687 DT2
= float32_to_int64(FST0
, &env
->fpu
->fp_status
);
1688 RESTORE_ROUNDING_MODE
;
1690 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1695 set_float_rounding_mode(float_round_nearest_even
, &env
->fpu
->fp_status
);
1696 WT2
= float64_to_int32(FDT0
, &env
->fpu
->fp_status
);
1697 RESTORE_ROUNDING_MODE
;
1699 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1704 set_float_rounding_mode(float_round_nearest_even
, &env
->fpu
->fp_status
);
1705 WT2
= float32_to_int32(FST0
, &env
->fpu
->fp_status
);
1706 RESTORE_ROUNDING_MODE
;
1708 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1714 DT2
= float64_to_int64_round_to_zero(FDT0
, &env
->fpu
->fp_status
);
1716 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1721 DT2
= float32_to_int64_round_to_zero(FST0
, &env
->fpu
->fp_status
);
1723 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1728 WT2
= float64_to_int32_round_to_zero(FDT0
, &env
->fpu
->fp_status
);
1730 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1735 WT2
= float32_to_int32_round_to_zero(FST0
, &env
->fpu
->fp_status
);
1737 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1743 set_float_rounding_mode(float_round_up
, &env
->fpu
->fp_status
);
1744 DT2
= float64_to_int64(FDT0
, &env
->fpu
->fp_status
);
1745 RESTORE_ROUNDING_MODE
;
1747 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1752 set_float_rounding_mode(float_round_up
, &env
->fpu
->fp_status
);
1753 DT2
= float32_to_int64(FST0
, &env
->fpu
->fp_status
);
1754 RESTORE_ROUNDING_MODE
;
1756 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1761 set_float_rounding_mode(float_round_up
, &env
->fpu
->fp_status
);
1762 WT2
= float64_to_int32(FDT0
, &env
->fpu
->fp_status
);
1763 RESTORE_ROUNDING_MODE
;
1765 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1770 set_float_rounding_mode(float_round_up
, &env
->fpu
->fp_status
);
1771 WT2
= float32_to_int32(FST0
, &env
->fpu
->fp_status
);
1772 RESTORE_ROUNDING_MODE
;
1774 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1780 set_float_rounding_mode(float_round_down
, &env
->fpu
->fp_status
);
1781 DT2
= float64_to_int64(FDT0
, &env
->fpu
->fp_status
);
1782 RESTORE_ROUNDING_MODE
;
1784 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1789 set_float_rounding_mode(float_round_down
, &env
->fpu
->fp_status
);
1790 DT2
= float32_to_int64(FST0
, &env
->fpu
->fp_status
);
1791 RESTORE_ROUNDING_MODE
;
1793 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1798 set_float_rounding_mode(float_round_down
, &env
->fpu
->fp_status
);
1799 WT2
= float64_to_int32(FDT0
, &env
->fpu
->fp_status
);
1800 RESTORE_ROUNDING_MODE
;
1802 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1807 set_float_rounding_mode(float_round_down
, &env
->fpu
->fp_status
);
1808 WT2
= float32_to_int32(FST0
, &env
->fpu
->fp_status
);
1809 RESTORE_ROUNDING_MODE
;
1811 if (GET_FP_CAUSE(env
->fpu
->fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
1815 /* MIPS specific unary operations */
1818 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1819 FDT2
= float64_div(FLOAT_ONE64
, FDT0
, &env
->fpu
->fp_status
);
1824 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1825 FST2
= float32_div(FLOAT_ONE32
, FST0
, &env
->fpu
->fp_status
);
1831 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1832 FDT2
= float64_sqrt(FDT0
, &env
->fpu
->fp_status
);
1833 FDT2
= float64_div(FLOAT_ONE64
, FDT2
, &env
->fpu
->fp_status
);
1838 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1839 FST2
= float32_sqrt(FST0
, &env
->fpu
->fp_status
);
1840 FST2
= float32_div(FLOAT_ONE32
, FST2
, &env
->fpu
->fp_status
);
1846 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1847 FDT2
= float64_div(FLOAT_ONE64
, FDT0
, &env
->fpu
->fp_status
);
1852 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1853 FST2
= float32_div(FLOAT_ONE32
, FST0
, &env
->fpu
->fp_status
);
1856 FLOAT_OP(recip1
, ps
)
1858 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1859 FST2
= float32_div(FLOAT_ONE32
, FST0
, &env
->fpu
->fp_status
);
1860 FSTH2
= float32_div(FLOAT_ONE32
, FSTH0
, &env
->fpu
->fp_status
);
1866 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1867 FDT2
= float64_sqrt(FDT0
, &env
->fpu
->fp_status
);
1868 FDT2
= float64_div(FLOAT_ONE64
, FDT2
, &env
->fpu
->fp_status
);
1873 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1874 FST2
= float32_sqrt(FST0
, &env
->fpu
->fp_status
);
1875 FST2
= float32_div(FLOAT_ONE32
, FST2
, &env
->fpu
->fp_status
);
1878 FLOAT_OP(rsqrt1
, ps
)
1880 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1881 FST2
= float32_sqrt(FST0
, &env
->fpu
->fp_status
);
1882 FSTH2
= float32_sqrt(FSTH0
, &env
->fpu
->fp_status
);
1883 FST2
= float32_div(FLOAT_ONE32
, FST2
, &env
->fpu
->fp_status
);
1884 FSTH2
= float32_div(FLOAT_ONE32
, FSTH2
, &env
->fpu
->fp_status
);
1888 /* binary operations */
1889 #define FLOAT_BINOP(name) \
1892 set_float_exception_flags(0, &env->fpu->fp_status); \
1893 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1895 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1896 DT2 = FLOAT_QNAN64; \
1900 set_float_exception_flags(0, &env->fpu->fp_status); \
1901 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1903 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1904 WT2 = FLOAT_QNAN32; \
1906 FLOAT_OP(name, ps) \
1908 set_float_exception_flags(0, &env->fpu->fp_status); \
1909 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1910 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1912 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1913 WT2 = FLOAT_QNAN32; \
1914 WTH2 = FLOAT_QNAN32; \
1923 /* MIPS specific binary operations */
1926 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1927 FDT2
= float64_mul(FDT0
, FDT2
, &env
->fpu
->fp_status
);
1928 FDT2
= float64_chs(float64_sub(FDT2
, FLOAT_ONE64
, &env
->fpu
->fp_status
));
1933 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1934 FST2
= float32_mul(FST0
, FST2
, &env
->fpu
->fp_status
);
1935 FST2
= float32_chs(float32_sub(FST2
, FLOAT_ONE32
, &env
->fpu
->fp_status
));
1938 FLOAT_OP(recip2
, ps
)
1940 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1941 FST2
= float32_mul(FST0
, FST2
, &env
->fpu
->fp_status
);
1942 FSTH2
= float32_mul(FSTH0
, FSTH2
, &env
->fpu
->fp_status
);
1943 FST2
= float32_chs(float32_sub(FST2
, FLOAT_ONE32
, &env
->fpu
->fp_status
));
1944 FSTH2
= float32_chs(float32_sub(FSTH2
, FLOAT_ONE32
, &env
->fpu
->fp_status
));
1950 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1951 FDT2
= float64_mul(FDT0
, FDT2
, &env
->fpu
->fp_status
);
1952 FDT2
= float64_sub(FDT2
, FLOAT_ONE64
, &env
->fpu
->fp_status
);
1953 FDT2
= float64_chs(float64_div(FDT2
, FLOAT_TWO64
, &env
->fpu
->fp_status
));
1958 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1959 FST2
= float32_mul(FST0
, FST2
, &env
->fpu
->fp_status
);
1960 FST2
= float32_sub(FST2
, FLOAT_ONE32
, &env
->fpu
->fp_status
);
1961 FST2
= float32_chs(float32_div(FST2
, FLOAT_TWO32
, &env
->fpu
->fp_status
));
1964 FLOAT_OP(rsqrt2
, ps
)
1966 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1967 FST2
= float32_mul(FST0
, FST2
, &env
->fpu
->fp_status
);
1968 FSTH2
= float32_mul(FSTH0
, FSTH2
, &env
->fpu
->fp_status
);
1969 FST2
= float32_sub(FST2
, FLOAT_ONE32
, &env
->fpu
->fp_status
);
1970 FSTH2
= float32_sub(FSTH2
, FLOAT_ONE32
, &env
->fpu
->fp_status
);
1971 FST2
= float32_chs(float32_div(FST2
, FLOAT_TWO32
, &env
->fpu
->fp_status
));
1972 FSTH2
= float32_chs(float32_div(FSTH2
, FLOAT_TWO32
, &env
->fpu
->fp_status
));
1978 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1979 FST2
= float32_add (FST0
, FSTH0
, &env
->fpu
->fp_status
);
1980 FSTH2
= float32_add (FST1
, FSTH1
, &env
->fpu
->fp_status
);
1986 set_float_exception_flags(0, &env
->fpu
->fp_status
);
1987 FST2
= float32_mul (FST0
, FSTH0
, &env
->fpu
->fp_status
);
1988 FSTH2
= float32_mul (FST1
, FSTH1
, &env
->fpu
->fp_status
);
1992 /* compare operations */
1993 #define FOP_COND_D(op, cond) \
1994 void do_cmp_d_ ## op (long cc) \
1999 SET_FP_COND(cc, env->fpu); \
2001 CLEAR_FP_COND(cc, env->fpu); \
2003 void do_cmpabs_d_ ## op (long cc) \
2006 FDT0 = float64_abs(FDT0); \
2007 FDT1 = float64_abs(FDT1); \
2011 SET_FP_COND(cc, env->fpu); \
2013 CLEAR_FP_COND(cc, env->fpu); \
2016 int float64_is_unordered(int sig
, float64 a
, float64 b STATUS_PARAM
)
2018 if (float64_is_signaling_nan(a
) ||
2019 float64_is_signaling_nan(b
) ||
2020 (sig
&& (float64_is_nan(a
) || float64_is_nan(b
)))) {
2021 float_raise(float_flag_invalid
, status
);
2023 } else if (float64_is_nan(a
) || float64_is_nan(b
)) {
2030 /* NOTE: the comma operator will make "cond" to eval to false,
2031 * but float*_is_unordered() is still called. */
2032 FOP_COND_D(f
, (float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
), 0))
2033 FOP_COND_D(un
, float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
))
2034 FOP_COND_D(eq
, !float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
) && float64_eq(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2035 FOP_COND_D(ueq
, float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
) || float64_eq(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2036 FOP_COND_D(olt
, !float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
) && float64_lt(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2037 FOP_COND_D(ult
, float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
) || float64_lt(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2038 FOP_COND_D(ole
, !float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
) && float64_le(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2039 FOP_COND_D(ule
, float64_is_unordered(0, FDT1
, FDT0
, &env
->fpu
->fp_status
) || float64_le(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2040 /* NOTE: the comma operator will make "cond" to eval to false,
2041 * but float*_is_unordered() is still called. */
2042 FOP_COND_D(sf
, (float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
), 0))
2043 FOP_COND_D(ngle
,float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
))
2044 FOP_COND_D(seq
, !float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
) && float64_eq(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2045 FOP_COND_D(ngl
, float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
) || float64_eq(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2046 FOP_COND_D(lt
, !float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
) && float64_lt(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2047 FOP_COND_D(nge
, float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
) || float64_lt(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2048 FOP_COND_D(le
, !float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
) && float64_le(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2049 FOP_COND_D(ngt
, float64_is_unordered(1, FDT1
, FDT0
, &env
->fpu
->fp_status
) || float64_le(FDT0
, FDT1
, &env
->fpu
->fp_status
))
2051 #define FOP_COND_S(op, cond) \
2052 void do_cmp_s_ ## op (long cc) \
2057 SET_FP_COND(cc, env->fpu); \
2059 CLEAR_FP_COND(cc, env->fpu); \
2061 void do_cmpabs_s_ ## op (long cc) \
2064 FST0 = float32_abs(FST0); \
2065 FST1 = float32_abs(FST1); \
2069 SET_FP_COND(cc, env->fpu); \
2071 CLEAR_FP_COND(cc, env->fpu); \
2074 flag
float32_is_unordered(int sig
, float32 a
, float32 b STATUS_PARAM
)
2076 if (float32_is_signaling_nan(a
) ||
2077 float32_is_signaling_nan(b
) ||
2078 (sig
&& (float32_is_nan(a
) || float32_is_nan(b
)))) {
2079 float_raise(float_flag_invalid
, status
);
2081 } else if (float32_is_nan(a
) || float32_is_nan(b
)) {
2088 /* NOTE: the comma operator will make "cond" to eval to false,
2089 * but float*_is_unordered() is still called. */
2090 FOP_COND_S(f
, (float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
), 0))
2091 FOP_COND_S(un
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
))
2092 FOP_COND_S(eq
, !float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
))
2093 FOP_COND_S(ueq
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
))
2094 FOP_COND_S(olt
, !float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
))
2095 FOP_COND_S(ult
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
))
2096 FOP_COND_S(ole
, !float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_le(FST0
, FST1
, &env
->fpu
->fp_status
))
2097 FOP_COND_S(ule
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_le(FST0
, FST1
, &env
->fpu
->fp_status
))
2098 /* NOTE: the comma operator will make "cond" to eval to false,
2099 * but float*_is_unordered() is still called. */
2100 FOP_COND_S(sf
, (float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
), 0))
2101 FOP_COND_S(ngle
,float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
))
2102 FOP_COND_S(seq
, !float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
))
2103 FOP_COND_S(ngl
, float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
))
2104 FOP_COND_S(lt
, !float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
))
2105 FOP_COND_S(nge
, float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
))
2106 FOP_COND_S(le
, !float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_le(FST0
, FST1
, &env
->fpu
->fp_status
))
2107 FOP_COND_S(ngt
, float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_le(FST0
, FST1
, &env
->fpu
->fp_status
))
2109 #define FOP_COND_PS(op, condl, condh) \
2110 void do_cmp_ps_ ## op (long cc) \
2116 SET_FP_COND(cc, env->fpu); \
2118 CLEAR_FP_COND(cc, env->fpu); \
2120 SET_FP_COND(cc + 1, env->fpu); \
2122 CLEAR_FP_COND(cc + 1, env->fpu); \
2124 void do_cmpabs_ps_ ## op (long cc) \
2127 FST0 = float32_abs(FST0); \
2128 FSTH0 = float32_abs(FSTH0); \
2129 FST1 = float32_abs(FST1); \
2130 FSTH1 = float32_abs(FSTH1); \
2135 SET_FP_COND(cc, env->fpu); \
2137 CLEAR_FP_COND(cc, env->fpu); \
2139 SET_FP_COND(cc + 1, env->fpu); \
2141 CLEAR_FP_COND(cc + 1, env->fpu); \
2144 /* NOTE: the comma operator will make "cond" to eval to false,
2145 * but float*_is_unordered() is still called. */
2146 FOP_COND_PS(f
, (float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
), 0),
2147 (float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
), 0))
2148 FOP_COND_PS(un
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
),
2149 float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
))
2150 FOP_COND_PS(eq
, !float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
),
2151 !float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) && float32_eq(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2152 FOP_COND_PS(ueq
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
),
2153 float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) || float32_eq(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2154 FOP_COND_PS(olt
, !float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
),
2155 !float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) && float32_lt(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2156 FOP_COND_PS(ult
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
),
2157 float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) || float32_lt(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2158 FOP_COND_PS(ole
, !float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_le(FST0
, FST1
, &env
->fpu
->fp_status
),
2159 !float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) && float32_le(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2160 FOP_COND_PS(ule
, float32_is_unordered(0, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_le(FST0
, FST1
, &env
->fpu
->fp_status
),
2161 float32_is_unordered(0, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) || float32_le(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2162 /* NOTE: the comma operator will make "cond" to eval to false,
2163 * but float*_is_unordered() is still called. */
2164 FOP_COND_PS(sf
, (float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
), 0),
2165 (float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
), 0))
2166 FOP_COND_PS(ngle
,float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
),
2167 float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
))
2168 FOP_COND_PS(seq
, !float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
),
2169 !float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) && float32_eq(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2170 FOP_COND_PS(ngl
, float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_eq(FST0
, FST1
, &env
->fpu
->fp_status
),
2171 float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) || float32_eq(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2172 FOP_COND_PS(lt
, !float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
),
2173 !float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) && float32_lt(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2174 FOP_COND_PS(nge
, float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_lt(FST0
, FST1
, &env
->fpu
->fp_status
),
2175 float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) || float32_lt(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2176 FOP_COND_PS(le
, !float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) && float32_le(FST0
, FST1
, &env
->fpu
->fp_status
),
2177 !float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) && float32_le(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))
2178 FOP_COND_PS(ngt
, float32_is_unordered(1, FST1
, FST0
, &env
->fpu
->fp_status
) || float32_le(FST0
, FST1
, &env
->fpu
->fp_status
),
2179 float32_is_unordered(1, FSTH1
, FSTH0
, &env
->fpu
->fp_status
) || float32_le(FSTH0
, FSTH1
, &env
->fpu
->fp_status
))