hw/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27 #include "qemu-timer.h"
  28
  29 #define D(x)
  30
  31 #define RW_TMR0_DIV   0x00
  32 #define R_TMR0_DATA   0x04
  33 #define RW_TMR0_CTRL  0x08
  34 #define RW_TMR1_DIV   0x10
  35 #define R_TMR1_DATA   0x14
  36 #define RW_TMR1_CTRL  0x18
  37 #define R_TIME        0x38
  38 #define RW_WD_CTRL    0x40
  39 #define RW_INTR_MASK  0x48
  40 #define RW_ACK_INTR   0x4c
  41 #define R_INTR        0x50
  42 #define R_MASKED_INTR 0x54
  43
  44 struct fs_timer_t {
  45         CPUState *env;
  46         qemu_irq *irq;
  47         target_phys_addr_t base;
  48
  49         QEMUBH *bh;
  50         ptimer_state *ptimer;
  51         struct timeval last;
  52
  53         /* Control registers.  */
  54         uint32_t rw_tmr0_div;
  55         uint32_t r_tmr0_data;
  56         uint32_t rw_tmr0_ctrl;
  57
  58         uint32_t rw_tmr1_div;
  59         uint32_t r_tmr1_data;
  60         uint32_t rw_tmr1_ctrl;
  61
  62         uint32_t rw_intr_mask;
  63         uint32_t rw_ack_intr;
  64         uint32_t r_intr;
  65         uint32_t r_masked_intr;
  66 };
  67
  68 static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
  69 {
  70         struct fs_timer_t *t = opaque;
  71         CPUState *env = t->env;
  72         cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
  73                   addr, env->pc);
  74         return 0;
  75 }
  76
  77 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
  78 {
  79         struct fs_timer_t *t = opaque;
  80         D(CPUState *env = t->env);
  81         uint32_t r = 0;
  82
  83         /* Make addr relative to this instances base.  */
  84         addr -= t->base;
  85         switch (addr) {
  86         case R_TMR0_DATA:
  87                 break;
  88         case R_TMR1_DATA:
  89                 D(printf ("R_TMR1_DATA\n"));
  90                 break;
  91         case R_TIME:
  92                 r = qemu_get_clock(vm_clock) * 10;
  93                 break;
  94         case RW_INTR_MASK:
  95                 r = t->rw_intr_mask;
  96                 break;
  97         case R_MASKED_INTR:
  98                 r = t->r_intr & t->rw_intr_mask;
  99                 break;
 100         default:
 101                 D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
 102                 break;
 103         }
 104         return r;
 105 }
 106
 107 static void
 108 timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 109 {
 110         struct fs_timer_t *t = opaque;
 111         CPUState *env = t->env;
 112         cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
 113                   addr, env->pc);
 114 }
 115
 116 #define TIMER_SLOWDOWN 1
 117 static void update_ctrl(struct fs_timer_t *t)
 118 {
 119         unsigned int op;
 120         unsigned int freq;
 121         unsigned int freq_hz;
 122         unsigned int div;
 123
 124         op = t->rw_tmr0_ctrl & 3;
 125         freq = t->rw_tmr0_ctrl >> 2;
 126         freq_hz = 32000000;
 127
 128         switch (freq)
 129         {
 130         case 0:
 131         case 1:
 132                 D(printf ("extern or disabled timer clock?\n"));
 133                 break;
 134         case 4: freq_hz =  29493000; break;
 135         case 5: freq_hz =  32000000; break;
 136         case 6: freq_hz =  32768000; break;
 137         case 7: freq_hz = 100000000; break;
 138         default:
 139                 abort();
 140                 break;
 141         }
 142
 143         D(printf ("freq_hz=%d div=%d\n", freq_hz, t->rw_tmr0_div));
 144         div = t->rw_tmr0_div * TIMER_SLOWDOWN;
 145         div >>= 15;
 146         freq_hz >>= 15;
 147         ptimer_set_freq(t->ptimer, freq_hz);
 148         ptimer_set_limit(t->ptimer, div, 0);
 149
 150         switch (op)
 151         {
 152                 case 0:
 153                         /* Load.  */
 154                         ptimer_set_limit(t->ptimer, div, 1);
 155                         ptimer_run(t->ptimer, 1);
 156                         break;
 157                 case 1:
 158                         /* Hold.  */
 159                         ptimer_stop(t->ptimer);
 160                         break;
 161                 case 2:
 162                         /* Run.  */
 163                         ptimer_run(t->ptimer, 0);
 164                         break;
 165                 default:
 166                         abort();
 167                         break;
 168         }
 169 }
 170
 171 static void timer_update_irq(struct fs_timer_t *t)
 172 {
 173         t->r_intr &= ~(t->rw_ack_intr);
 174         t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 175
 176         D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 177         if (t->r_masked_intr & 1)
 178                 qemu_irq_raise(t->irq[0]);
 179         else
 180                 qemu_irq_lower(t->irq[0]);
 181 }
 182
 183 static void timer_hit(void *opaque)
 184 {
 185         struct fs_timer_t *t = opaque;
 186         t->r_intr |= 1;
 187         timer_update_irq(t);
 188 }
 189
 190 static void
 191 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 192 {
 193         struct fs_timer_t *t = opaque;
 194         CPUState *env = t->env;
 195
 196         /* Make addr relative to this instances base.  */
 197         addr -= t->base;
 198         switch (addr)
 199         {
 200                 case RW_TMR0_DIV:
 201                         t->rw_tmr0_div = value;
 202                         break;
 203                 case RW_TMR0_CTRL:
 204                         D(printf ("RW_TMR0_CTRL=%x\n", value));
 205                         t->rw_tmr0_ctrl = value;
 206                         update_ctrl(t);
 207                         break;
 208                 case RW_TMR1_DIV:
 209                         t->rw_tmr1_div = value;
 210                         break;
 211                 case RW_TMR1_CTRL:
 212                         D(printf ("RW_TMR1_CTRL=%x\n", value));
 213                         break;
 214                 case RW_INTR_MASK:
 215                         D(printf ("RW_INTR_MASK=%x\n", value));
 216                         t->rw_intr_mask = value;
 217                         timer_update_irq(t);
 218                         break;
 219                 case RW_WD_CTRL:
 220                         D(printf ("RW_WD_CTRL=%x\n", value));
 221                         break;
 222                 case RW_ACK_INTR:
 223                         t->rw_ack_intr = value;
 224                         timer_update_irq(t);
 225                         t->rw_ack_intr = 0;
 226                         break;
 227                 default:
 228                         printf ("%s %x %x pc=%x\n",
 229                                 __func__, addr, value, env->pc);
 230                         break;
 231         }
 232 }
 233
 234 static CPUReadMemoryFunc *timer_read[] = {
 235     &timer_rinvalid,
 236     &timer_rinvalid,
 237     &timer_readl,
 238 };
 239
 240 static CPUWriteMemoryFunc *timer_write[] = {
 241     &timer_winvalid,
 242     &timer_winvalid,
 243     &timer_writel,
 244 };
 245
 246 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
 247                         target_phys_addr_t base)
 248 {
 249         static struct fs_timer_t *t;
 250         int timer_regs;
 251
 252         t = qemu_mallocz(sizeof *t);
 253         if (!t)
 254                 return;
 255
 256         t->bh = qemu_bh_new(timer_hit, t);
 257         t->ptimer = ptimer_init(t->bh);
 258         t->irq = irqs;
 259         t->env = env;
 260         t->base = base;
 261
 262         timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
 263         cpu_register_physical_memory (base, 0x5c, timer_regs);
 264 }