Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 case
[qemu-kvm/fedora.git] / hw / versatilepb.c
blobbfbc0312a096712dfd1c69a2734837fc37e29926
1 /*
2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
8 */
10 #include "hw.h"
11 #include "arm-misc.h"
12 #include "primecell.h"
13 #include "devices.h"
14 #include "net.h"
15 #include "sysemu.h"
16 #include "pci.h"
17 #include "boards.h"
19 /* Primary interrupt controller. */
21 typedef struct vpb_sic_state
23 uint32_t base;
24 uint32_t level;
25 uint32_t mask;
26 uint32_t pic_enable;
27 qemu_irq *parent;
28 int irq;
29 } vpb_sic_state;
31 static void vpb_sic_update(vpb_sic_state *s)
33 uint32_t flags;
35 flags = s->level & s->mask;
36 qemu_set_irq(s->parent[s->irq], flags != 0);
39 static void vpb_sic_update_pic(vpb_sic_state *s)
41 int i;
42 uint32_t mask;
44 for (i = 21; i <= 30; i++) {
45 mask = 1u << i;
46 if (!(s->pic_enable & mask))
47 continue;
48 qemu_set_irq(s->parent[i], (s->level & mask) != 0);
52 static void vpb_sic_set_irq(void *opaque, int irq, int level)
54 vpb_sic_state *s = (vpb_sic_state *)opaque;
55 if (level)
56 s->level |= 1u << irq;
57 else
58 s->level &= ~(1u << irq);
59 if (s->pic_enable & (1u << irq))
60 qemu_set_irq(s->parent[irq], level);
61 vpb_sic_update(s);
64 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
66 vpb_sic_state *s = (vpb_sic_state *)opaque;
68 offset -= s->base;
69 switch (offset >> 2) {
70 case 0: /* STATUS */
71 return s->level & s->mask;
72 case 1: /* RAWSTAT */
73 return s->level;
74 case 2: /* ENABLE */
75 return s->mask;
76 case 4: /* SOFTINT */
77 return s->level & 1;
78 case 8: /* PICENABLE */
79 return s->pic_enable;
80 default:
81 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
82 return 0;
86 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
87 uint32_t value)
89 vpb_sic_state *s = (vpb_sic_state *)opaque;
90 offset -= s->base;
92 switch (offset >> 2) {
93 case 2: /* ENSET */
94 s->mask |= value;
95 break;
96 case 3: /* ENCLR */
97 s->mask &= ~value;
98 break;
99 case 4: /* SOFTINTSET */
100 if (value)
101 s->mask |= 1;
102 break;
103 case 5: /* SOFTINTCLR */
104 if (value)
105 s->mask &= ~1u;
106 break;
107 case 8: /* PICENSET */
108 s->pic_enable |= (value & 0x7fe00000);
109 vpb_sic_update_pic(s);
110 break;
111 case 9: /* PICENCLR */
112 s->pic_enable &= ~value;
113 vpb_sic_update_pic(s);
114 break;
115 default:
116 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
117 return;
119 vpb_sic_update(s);
122 static CPUReadMemoryFunc *vpb_sic_readfn[] = {
123 vpb_sic_read,
124 vpb_sic_read,
125 vpb_sic_read
128 static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
129 vpb_sic_write,
130 vpb_sic_write,
131 vpb_sic_write
134 static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
136 vpb_sic_state *s;
137 qemu_irq *qi;
138 int iomemtype;
140 s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
141 if (!s)
142 return NULL;
143 qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
144 s->base = base;
145 s->parent = parent;
146 s->irq = irq;
147 iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
148 vpb_sic_writefn, s);
149 cpu_register_physical_memory(base, 0x00001000, iomemtype);
150 /* ??? Save/restore. */
151 return qi;
154 /* Board init. */
156 /* The AB and PB boards both use the same core, just with different
157 peripherans and expansion busses. For now we emulate a subset of the
158 PB peripherals and just change the board ID. */
160 static struct arm_boot_info versatile_binfo;
162 static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
163 const char *boot_device, DisplayState *ds,
164 const char *kernel_filename, const char *kernel_cmdline,
165 const char *initrd_filename, const char *cpu_model,
166 int board_id)
168 CPUState *env;
169 qemu_irq *pic;
170 qemu_irq *sic;
171 void *scsi_hba;
172 PCIBus *pci_bus;
173 NICInfo *nd;
174 int n;
175 int done_smc = 0;
176 int index;
178 if (!cpu_model)
179 cpu_model = "arm926";
180 env = cpu_init(cpu_model);
181 if (!env) {
182 fprintf(stderr, "Unable to find CPU definition\n");
183 exit(1);
185 /* ??? RAM should repeat to fill physical memory space. */
186 /* SDRAM at address zero. */
187 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
189 arm_sysctl_init(0x10000000, 0x41007004);
190 pic = arm_pic_init_cpu(env);
191 pic = pl190_init(0x10140000, pic[0], pic[1]);
192 sic = vpb_sic_init(0x10003000, pic, 31);
193 pl050_init(0x10006000, sic[3], 0);
194 pl050_init(0x10007000, sic[4], 1);
196 pci_bus = pci_vpb_init(sic, 27, 0);
197 /* The Versatile PCI bridge does not provide access to PCI IO space,
198 so many of the qemu PCI devices are not useable. */
199 for(n = 0; n < nb_nics; n++) {
200 nd = &nd_table[n];
201 if (!nd->model)
202 nd->model = done_smc ? "rtl8139" : "smc91c111";
203 if (strcmp(nd->model, "smc91c111") == 0) {
204 smc91c111_init(nd, 0x10010000, sic[25]);
205 } else {
206 pci_nic_init(pci_bus, nd, -1);
209 if (usb_enabled) {
210 usb_ohci_init_pci(pci_bus, 3, -1);
212 if (drive_get_max_bus(IF_SCSI) > 0) {
213 fprintf(stderr, "qemu: too many SCSI bus\n");
214 exit(1);
216 scsi_hba = lsi_scsi_init(pci_bus, -1);
217 for (n = 0; n < LSI_MAX_DEVS; n++) {
218 index = drive_get_index(IF_SCSI, 0, n);
219 if (index == -1)
220 continue;
221 lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n);
224 pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM);
225 pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM);
226 pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM);
227 pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM);
229 pl080_init(0x10130000, pic[17], 8);
230 sp804_init(0x101e2000, pic[4]);
231 sp804_init(0x101e3000, pic[5]);
233 /* The versatile/PB actually has a modified Color LCD controller
234 that includes hardware cursor support from the PL111. */
235 pl110_init(ds, 0x10120000, pic[16], 1);
237 index = drive_get_index(IF_SD, 0, 0);
238 if (index == -1) {
239 fprintf(stderr, "qemu: missing SecureDigital card\n");
240 exit(1);
243 pl181_init(0x10005000, drives_table[index].bdrv, sic[22], sic[1]);
244 #if 0
245 /* Disabled because there's no way of specifying a block device. */
246 pl181_init(0x1000b000, NULL, sic, 23, 2);
247 #endif
249 /* Add PL031 Real Time Clock. */
250 pl031_init(0x101e8000,pic[10]);
252 /* Memory map for Versatile/PB: */
253 /* 0x10000000 System registers. */
254 /* 0x10001000 PCI controller config registers. */
255 /* 0x10002000 Serial bus interface. */
256 /* 0x10003000 Secondary interrupt controller. */
257 /* 0x10004000 AACI (audio). */
258 /* 0x10005000 MMCI0. */
259 /* 0x10006000 KMI0 (keyboard). */
260 /* 0x10007000 KMI1 (mouse). */
261 /* 0x10008000 Character LCD Interface. */
262 /* 0x10009000 UART3. */
263 /* 0x1000a000 Smart card 1. */
264 /* 0x1000b000 MMCI1. */
265 /* 0x10010000 Ethernet. */
266 /* 0x10020000 USB. */
267 /* 0x10100000 SSMC. */
268 /* 0x10110000 MPMC. */
269 /* 0x10120000 CLCD Controller. */
270 /* 0x10130000 DMA Controller. */
271 /* 0x10140000 Vectored interrupt controller. */
272 /* 0x101d0000 AHB Monitor Interface. */
273 /* 0x101e0000 System Controller. */
274 /* 0x101e1000 Watchdog Interface. */
275 /* 0x101e2000 Timer 0/1. */
276 /* 0x101e3000 Timer 2/3. */
277 /* 0x101e4000 GPIO port 0. */
278 /* 0x101e5000 GPIO port 1. */
279 /* 0x101e6000 GPIO port 2. */
280 /* 0x101e7000 GPIO port 3. */
281 /* 0x101e8000 RTC. */
282 /* 0x101f0000 Smart card 0. */
283 /* 0x101f1000 UART0. */
284 /* 0x101f2000 UART1. */
285 /* 0x101f3000 UART2. */
286 /* 0x101f4000 SSPI. */
288 versatile_binfo.ram_size = ram_size;
289 versatile_binfo.kernel_filename = kernel_filename;
290 versatile_binfo.kernel_cmdline = kernel_cmdline;
291 versatile_binfo.initrd_filename = initrd_filename;
292 versatile_binfo.board_id = board_id;
293 arm_load_kernel(env, &versatile_binfo);
296 static void vpb_init(ram_addr_t ram_size, int vga_ram_size,
297 const char *boot_device, DisplayState *ds,
298 const char *kernel_filename, const char *kernel_cmdline,
299 const char *initrd_filename, const char *cpu_model)
301 versatile_init(ram_size, vga_ram_size,
302 boot_device, ds,
303 kernel_filename, kernel_cmdline,
304 initrd_filename, cpu_model, 0x183);
307 static void vab_init(ram_addr_t ram_size, int vga_ram_size,
308 const char *boot_device, DisplayState *ds,
309 const char *kernel_filename, const char *kernel_cmdline,
310 const char *initrd_filename, const char *cpu_model)
312 versatile_init(ram_size, vga_ram_size,
313 boot_device, ds,
314 kernel_filename, kernel_cmdline,
315 initrd_filename, cpu_model, 0x25e);
318 QEMUMachine versatilepb_machine = {
319 "versatilepb",
320 "ARM Versatile/PB (ARM926EJ-S)",
321 vpb_init,
324 QEMUMachine versatileab_machine = {
325 "versatileab",
326 "ARM Versatile/AB (ARM926EJ-S)",
327 vab_init,