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PPC TCG Fixes
[qemu-kvm/fedora.git] / target-cris / translate.c
blob3affd1cec656e13dc443c4f07060362cfd187985
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in need of attention.
25 */
26
27 #include <stdarg.h>
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <string.h>
31 #include <inttypes.h>
32 #include <assert.h>
33
34 #include "cpu.h"
35 #include "exec-all.h"
36 #include "disas.h"
37 #include "tcg-op.h"
38 #include "helper.h"
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
41
42 #define DISAS_CRIS 0
43 #if DISAS_CRIS
44 #define DIS(x) x
45 #else
46 #define DIS(x)
47 #endif
48
49 #define D(x)
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
52
53 #define DISAS_SWI 5
54
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
58
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
63
64 TCGv cpu_env;
65 TCGv cpu_T[2];
66 TCGv cpu_R[16];
67 TCGv cpu_PR[16];
68 TCGv cc_x;
69 TCGv cc_src;
70 TCGv cc_dest;
71 TCGv cc_result;
72 TCGv cc_op;
73 TCGv cc_size;
74 TCGv cc_mask;
75
76 TCGv env_btaken;
77 TCGv env_btarget;
78 TCGv env_pc;
79
80 /* This is the state at translation time. */
81 typedef struct DisasContext {
82 CPUState *env;
83 target_ulong pc, ppc;
84
85 /* Decoder. */
86 uint32_t ir;
87 uint32_t opcode;
88 unsigned int op1;
89 unsigned int op2;
90 unsigned int zsize, zzsize;
91 unsigned int mode;
92 unsigned int postinc;
93
94 int update_cc;
95 int cc_op;
96 int cc_size;
97 uint32_t cc_mask;
98
99 int cc_size_uptodate; /* -1 invalid or last written value. */
100
101 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
102 int flags_uptodate; /* Wether or not $ccs is uptodate. */
103 int flagx_known; /* Wether or not flags_x has the x flag known at
104 translation time. */
105 int flags_x;
106
107 int clear_x; /* Clear x after this insn? */
108 int cpustate_changed;
109 unsigned int tb_flags; /* tb dependent flags. */
110 int is_jmp;
111
112 #define JMP_NOJMP 0
113 #define JMP_DIRECT 1
114 #define JMP_INDIRECT 2
115 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
116 uint32_t jmp_pc;
117
118 int delayed_branch;
119
120 struct TranslationBlock *tb;
121 int singlestep_enabled;
122 } DisasContext;
123
124 static void gen_BUG(DisasContext *dc, char *file, int line)
125 {
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_abort(dc->env, "%s:%d\n", file, line);
129 }
130
131 const char *regnames[] =
132 {
133 "$r0", "$r1", "$r2", "$r3",
134 "$r4", "$r5", "$r6", "$r7",
135 "$r8", "$r9", "$r10", "$r11",
136 "$r12", "$r13", "$sp", "$acr",
137 };
138 const char *pregnames[] =
139 {
140 "$bz", "$vr", "$pid", "$srs",
141 "$wz", "$exs", "$eda", "$mof",
142 "$dz", "$ebp", "$erp", "$srp",
143 "$nrp", "$ccs", "$usp", "$spc",
144 };
145
146 /* We need this table to handle preg-moves with implicit width. */
147 int preg_sizes[] = {
148 1, /* bz. */
149 1, /* vr. */
150 4, /* pid. */
151 1, /* srs. */
152 2, /* wz. */
153 4, 4, 4,
154 4, 4, 4, 4,
155 4, 4, 4, 4,
156 };
157
158 #define t_gen_mov_TN_env(tn, member) \
159 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
160 #define t_gen_mov_env_TN(member, tn) \
161 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
162
163 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
164 {
165 if (r < 0 || r > 15)
166 fprintf(stderr, "wrong register read $r%d\n", r);
167 tcg_gen_mov_tl(tn, cpu_R[r]);
168 }
169 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
170 {
171 if (r < 0 || r > 15)
172 fprintf(stderr, "wrong register write $r%d\n", r);
173 tcg_gen_mov_tl(cpu_R[r], tn);
174 }
175
176 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
177 {
178 if (offset > sizeof (CPUState))
179 fprintf(stderr, "wrong load from env from off=%d\n", offset);
180 tcg_gen_ld_tl(tn, cpu_env, offset);
181 }
182 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
183 {
184 if (offset > sizeof (CPUState))
185 fprintf(stderr, "wrong store to env at off=%d\n", offset);
186 tcg_gen_st_tl(tn, cpu_env, offset);
187 }
188
189 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
190 {
191 if (r < 0 || r > 15)
192 fprintf(stderr, "wrong register read $p%d\n", r);
193 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
194 tcg_gen_mov_tl(tn, tcg_const_tl(0));
195 else if (r == PR_VR)
196 tcg_gen_mov_tl(tn, tcg_const_tl(32));
197 else if (r == PR_EXS) {
198 printf("read from EXS!\n");
199 tcg_gen_mov_tl(tn, cpu_PR[r]);
200 }
201 else if (r == PR_EDA) {
202 printf("read from EDA!\n");
203 tcg_gen_mov_tl(tn, cpu_PR[r]);
204 }
205 else
206 tcg_gen_mov_tl(tn, cpu_PR[r]);
207 }
208 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
209 {
210 if (r < 0 || r > 15)
211 fprintf(stderr, "wrong register write $p%d\n", r);
212 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
213 return;
214 else if (r == PR_SRS)
215 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
216 else {
217 tcg_gen_mov_tl(cpu_PR[r], tn);
218 if (r == PR_PID)
219 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
220 else if (r == PR_CCS)
221 dc->cpustate_changed = 1;
222 }
223 }
224
225 static inline void t_gen_raise_exception(uint32_t index)
226 {
227 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
228 }
229
230 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
231 {
232 int l1;
233
234 l1 = gen_new_label();
235 /* Speculative shift. */
236 tcg_gen_shl_tl(d, a, b);
237 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
238 /* Clear dst if shift operands were to large. */
239 tcg_gen_movi_tl(d, 0);
240 gen_set_label(l1);
241 }
242
243 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
244 {
245 int l1;
246
247 l1 = gen_new_label();
248 /* Speculative shift. */
249 tcg_gen_shr_tl(d, a, b);
250 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
251 /* Clear dst if shift operands were to large. */
252 tcg_gen_movi_tl(d, 0);
253 gen_set_label(l1);
254 }
255
256 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
257 {
258 int l1;
259
260 l1 = gen_new_label();
261 /* Speculative shift. */
262 tcg_gen_sar_tl(d, a, b);
263 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
264 /* Clear dst if shift operands were to large. */
265 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
266 gen_set_label(l1);
267 }
268
269 /* 64-bit signed mul, lower result in d and upper in d2. */
270 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
271 {
272 TCGv t0, t1;
273
274 t0 = tcg_temp_new(TCG_TYPE_I64);
275 t1 = tcg_temp_new(TCG_TYPE_I64);
276
277 tcg_gen_ext32s_i64(t0, a);
278 tcg_gen_ext32s_i64(t1, b);
279 tcg_gen_mul_i64(t0, t0, t1);
280
281 tcg_gen_trunc_i64_i32(d, t0);
282 tcg_gen_shri_i64(t0, t0, 32);
283 tcg_gen_trunc_i64_i32(d2, t0);
284
285 tcg_temp_free(t0);
286 tcg_temp_free(t1);
287 }
288
289 /* 64-bit unsigned muls, lower result in d and upper in d2. */
290 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
291 {
292 TCGv t0, t1;
293
294 t0 = tcg_temp_new(TCG_TYPE_I64);
295 t1 = tcg_temp_new(TCG_TYPE_I64);
296
297 tcg_gen_extu_i32_i64(t0, a);
298 tcg_gen_extu_i32_i64(t1, b);
299 tcg_gen_mul_i64(t0, t0, t1);
300
301 tcg_gen_trunc_i64_i32(d, t0);
302 tcg_gen_shri_i64(t0, t0, 32);
303 tcg_gen_trunc_i64_i32(d2, t0);
304
305 tcg_temp_free(t0);
306 tcg_temp_free(t1);
307 }
308
309 /* 32bit branch-free binary search for counting leading zeros. */
310 static void t_gen_lz_i32(TCGv d, TCGv x)
311 {
312 TCGv y, m, n;
313
314 y = tcg_temp_new(TCG_TYPE_I32);
315 m = tcg_temp_new(TCG_TYPE_I32);
316 n = tcg_temp_new(TCG_TYPE_I32);
317
318 /* y = -(x >> 16) */
319 tcg_gen_shri_i32(y, x, 16);
320 tcg_gen_neg_i32(y, y);
321
322 /* m = (y >> 16) & 16 */
323 tcg_gen_sari_i32(m, y, 16);
324 tcg_gen_andi_i32(m, m, 16);
325
326 /* n = 16 - m */
327 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
328 /* x = x >> m */
329 tcg_gen_shr_i32(x, x, m);
330
331 /* y = x - 0x100 */
332 tcg_gen_subi_i32(y, x, 0x100);
333 /* m = (y >> 16) & 8 */
334 tcg_gen_sari_i32(m, y, 16);
335 tcg_gen_andi_i32(m, m, 8);
336 /* n = n + m */
337 tcg_gen_add_i32(n, n, m);
338 /* x = x << m */
339 tcg_gen_shl_i32(x, x, m);
340
341 /* y = x - 0x1000 */
342 tcg_gen_subi_i32(y, x, 0x1000);
343 /* m = (y >> 16) & 4 */
344 tcg_gen_sari_i32(m, y, 16);
345 tcg_gen_andi_i32(m, m, 4);
346 /* n = n + m */
347 tcg_gen_add_i32(n, n, m);
348 /* x = x << m */
349 tcg_gen_shl_i32(x, x, m);
350
351 /* y = x - 0x4000 */
352 tcg_gen_subi_i32(y, x, 0x4000);
353 /* m = (y >> 16) & 2 */
354 tcg_gen_sari_i32(m, y, 16);
355 tcg_gen_andi_i32(m, m, 2);
356 /* n = n + m */
357 tcg_gen_add_i32(n, n, m);
358 /* x = x << m */
359 tcg_gen_shl_i32(x, x, m);
360
361 /* y = x >> 14 */
362 tcg_gen_shri_i32(y, x, 14);
363 /* m = y & ~(y >> 1) */
364 tcg_gen_sari_i32(m, y, 1);
365 tcg_gen_not_i32(m, m);
366 tcg_gen_and_i32(m, m, y);
367
368 /* d = n + 2 - m */
369 tcg_gen_addi_i32(d, n, 2);
370 tcg_gen_sub_i32(d, d, m);
371
372 tcg_temp_free(y);
373 tcg_temp_free(m);
374 tcg_temp_free(n);
375 }
376
377 static void t_gen_btst(TCGv d, TCGv a, TCGv b)
378 {
379 TCGv sbit;
380 TCGv bset;
381 TCGv t0;
382 int l1;
383
384 /* des ref:
385 The N flag is set according to the selected bit in the dest reg.
386 The Z flag is set if the selected bit and all bits to the right are
387 zero.
388 The X flag is cleared.
389 Other flags are left untouched.
390 The destination reg is not affected.
391
392 unsigned int fz, sbit, bset, mask, masked_t0;
393
394 sbit = T1 & 31;
395 bset = !!(T0 & (1 << sbit));
396 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
397 masked_t0 = T0 & mask;
398 fz = !(masked_t0 | bset);
399
400 // Clear the X, N and Z flags.
401 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
402 // Set the N and Z flags accordingly.
403 T0 |= (bset << 3) | (fz << 2);
404 */
405
406 l1 = gen_new_label();
407 sbit = tcg_temp_new(TCG_TYPE_TL);
408 bset = tcg_temp_new(TCG_TYPE_TL);
409 t0 = tcg_temp_new(TCG_TYPE_TL);
410
411 /* Compute bset and sbit. */
412 tcg_gen_andi_tl(sbit, b, 31);
413 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
414 tcg_gen_and_tl(bset, a, t0);
415 tcg_gen_shr_tl(bset, bset, sbit);
416 /* Displace to N_FLAG. */
417 tcg_gen_shli_tl(bset, bset, 3);
418
419 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
420 tcg_gen_subi_tl(sbit, sbit, 1);
421 tcg_gen_and_tl(sbit, a, sbit);
422
423 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
424 /* or in the N_FLAG. */
425 tcg_gen_or_tl(d, d, bset);
426 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
427 /* or in the Z_FLAG. */
428 tcg_gen_ori_tl(d, d, Z_FLAG);
429 gen_set_label(l1);
430
431 tcg_temp_free(sbit);
432 tcg_temp_free(bset);
433 }
434
435 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
436 {
437 int l1;
438
439 l1 = gen_new_label();
440
441 /*
442 * d <<= 1
443 * if (d >= s)
444 * d -= s;
445 */
446 tcg_gen_shli_tl(d, a, 1);
447 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
448 tcg_gen_sub_tl(d, d, b);
449 gen_set_label(l1);
450 }
451
452 /* Extended arithmetics on CRIS. */
453 static inline void t_gen_add_flag(TCGv d, int flag)
454 {
455 TCGv c;
456
457 c = tcg_temp_new(TCG_TYPE_TL);
458 t_gen_mov_TN_preg(c, PR_CCS);
459 /* Propagate carry into d. */
460 tcg_gen_andi_tl(c, c, 1 << flag);
461 if (flag)
462 tcg_gen_shri_tl(c, c, flag);
463 tcg_gen_add_tl(d, d, c);
464 tcg_temp_free(c);
465 }
466
467 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
468 {
469 if (dc->flagx_known) {
470 if (dc->flags_x) {
471 TCGv c;
472
473 c = tcg_temp_new(TCG_TYPE_TL);
474 t_gen_mov_TN_preg(c, PR_CCS);
475 /* C flag is already at bit 0. */
476 tcg_gen_andi_tl(c, c, C_FLAG);
477 tcg_gen_add_tl(d, d, c);
478 tcg_temp_free(c);
479 }
480 } else {
481 TCGv x, c;
482
483 x = tcg_temp_new(TCG_TYPE_TL);
484 c = tcg_temp_new(TCG_TYPE_TL);
485 t_gen_mov_TN_preg(x, PR_CCS);
486 tcg_gen_mov_tl(c, x);
487
488 /* Propagate carry into d if X is set. Branch free. */
489 tcg_gen_andi_tl(c, c, C_FLAG);
490 tcg_gen_andi_tl(x, x, X_FLAG);
491 tcg_gen_shri_tl(x, x, 4);
492
493 tcg_gen_and_tl(x, x, c);
494 tcg_gen_add_tl(d, d, x);
495 tcg_temp_free(x);
496 tcg_temp_free(c);
497 }
498 }
499
500 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
501 {
502 if (dc->flagx_known) {
503 if (dc->flags_x) {
504 TCGv c;
505
506 c = tcg_temp_new(TCG_TYPE_TL);
507 t_gen_mov_TN_preg(c, PR_CCS);
508 /* C flag is already at bit 0. */
509 tcg_gen_andi_tl(c, c, C_FLAG);
510 tcg_gen_sub_tl(d, d, c);
511 tcg_temp_free(c);
512 }
513 } else {
514 TCGv x, c;
515
516 x = tcg_temp_new(TCG_TYPE_TL);
517 c = tcg_temp_new(TCG_TYPE_TL);
518 t_gen_mov_TN_preg(x, PR_CCS);
519 tcg_gen_mov_tl(c, x);
520
521 /* Propagate carry into d if X is set. Branch free. */
522 tcg_gen_andi_tl(c, c, C_FLAG);
523 tcg_gen_andi_tl(x, x, X_FLAG);
524 tcg_gen_shri_tl(x, x, 4);
525
526 tcg_gen_and_tl(x, x, c);
527 tcg_gen_sub_tl(d, d, x);
528 tcg_temp_free(x);
529 tcg_temp_free(c);
530 }
531 }
532
533 /* Swap the two bytes within each half word of the s operand.
534 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
535 static inline void t_gen_swapb(TCGv d, TCGv s)
536 {
537 TCGv t, org_s;
538
539 t = tcg_temp_new(TCG_TYPE_TL);
540 org_s = tcg_temp_new(TCG_TYPE_TL);
541
542 /* d and s may refer to the same object. */
543 tcg_gen_mov_tl(org_s, s);
544 tcg_gen_shli_tl(t, org_s, 8);
545 tcg_gen_andi_tl(d, t, 0xff00ff00);
546 tcg_gen_shri_tl(t, org_s, 8);
547 tcg_gen_andi_tl(t, t, 0x00ff00ff);
548 tcg_gen_or_tl(d, d, t);
549 tcg_temp_free(t);
550 tcg_temp_free(org_s);
551 }
552
553 /* Swap the halfwords of the s operand. */
554 static inline void t_gen_swapw(TCGv d, TCGv s)
555 {
556 TCGv t;
557 /* d and s refer the same object. */
558 t = tcg_temp_new(TCG_TYPE_TL);
559 tcg_gen_mov_tl(t, s);
560 tcg_gen_shli_tl(d, t, 16);
561 tcg_gen_shri_tl(t, t, 16);
562 tcg_gen_or_tl(d, d, t);
563 tcg_temp_free(t);
564 }
565
566 /* Reverse the within each byte.
567 T0 = (((T0 << 7) & 0x80808080) |
568 ((T0 << 5) & 0x40404040) |
569 ((T0 << 3) & 0x20202020) |
570 ((T0 << 1) & 0x10101010) |
571 ((T0 >> 1) & 0x08080808) |
572 ((T0 >> 3) & 0x04040404) |
573 ((T0 >> 5) & 0x02020202) |
574 ((T0 >> 7) & 0x01010101));
575 */
576 static inline void t_gen_swapr(TCGv d, TCGv s)
577 {
578 struct {
579 int shift; /* LSL when positive, LSR when negative. */
580 uint32_t mask;
581 } bitrev [] = {
582 {7, 0x80808080},
583 {5, 0x40404040},
584 {3, 0x20202020},
585 {1, 0x10101010},
586 {-1, 0x08080808},
587 {-3, 0x04040404},
588 {-5, 0x02020202},
589 {-7, 0x01010101}
590 };
591 int i;
592 TCGv t, org_s;
593
594 /* d and s refer the same object. */
595 t = tcg_temp_new(TCG_TYPE_TL);
596 org_s = tcg_temp_new(TCG_TYPE_TL);
597 tcg_gen_mov_tl(org_s, s);
598
599 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
600 tcg_gen_andi_tl(d, t, bitrev[0].mask);
601 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
602 if (bitrev[i].shift >= 0) {
603 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
604 } else {
605 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
606 }
607 tcg_gen_andi_tl(t, t, bitrev[i].mask);
608 tcg_gen_or_tl(d, d, t);
609 }
610 tcg_temp_free(t);
611 tcg_temp_free(org_s);
612 }
613
614 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
615 {
616 TCGv btaken;
617 int l1;
618
619 l1 = gen_new_label();
620 btaken = tcg_temp_new(TCG_TYPE_TL);
621
622 /* Conditional jmp. */
623 tcg_gen_mov_tl(btaken, env_btaken);
624 tcg_gen_mov_tl(env_pc, pc_false);
625 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
626 tcg_gen_mov_tl(env_pc, pc_true);
627 gen_set_label(l1);
628
629 tcg_temp_free(btaken);
630 }
631
632 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
633 {
634 TranslationBlock *tb;
635 tb = dc->tb;
636 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
637 tcg_gen_goto_tb(n);
638 tcg_gen_movi_tl(env_pc, dest);
639 tcg_gen_exit_tb((long)tb + n);
640 } else {
641 tcg_gen_movi_tl(env_pc, dest);
642 tcg_gen_exit_tb(0);
643 }
644 }
645
646 /* Sign extend at translation time. */
647 static int sign_extend(unsigned int val, unsigned int width)
648 {
649 int sval;
650
651 /* LSL. */
652 val <<= 31 - width;
653 sval = val;
654 /* ASR. */
655 sval >>= 31 - width;
656 return sval;
657 }
658
659 static inline void cris_clear_x_flag(DisasContext *dc)
660 {
661 if (dc->flagx_known && dc->flags_x)
662 dc->flags_uptodate = 0;
663
664 dc->flagx_known = 1;
665 dc->flags_x = 0;
666 }
667
668 static void cris_flush_cc_state(DisasContext *dc)
669 {
670 if (dc->cc_size_uptodate != dc->cc_size) {
671 tcg_gen_movi_tl(cc_size, dc->cc_size);
672 dc->cc_size_uptodate = dc->cc_size;
673 }
674 tcg_gen_movi_tl(cc_op, dc->cc_op);
675 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
676 }
677
678 static void cris_evaluate_flags(DisasContext *dc)
679 {
680 if (!dc->flags_uptodate) {
681 cris_flush_cc_state(dc);
682
683 switch (dc->cc_op)
684 {
685 case CC_OP_MCP:
686 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
687 break;
688 case CC_OP_MULS:
689 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
690 break;
691 case CC_OP_MULU:
692 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
693 break;
694 case CC_OP_MOVE:
695 case CC_OP_AND:
696 case CC_OP_OR:
697 case CC_OP_XOR:
698 case CC_OP_ASR:
699 case CC_OP_LSR:
700 case CC_OP_LSL:
701 switch (dc->cc_size)
702 {
703 case 4:
704 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
705 break;
706 case 2:
707 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
708 break;
709 default:
710 tcg_gen_helper_0_0(helper_evaluate_flags);
711 break;
712 }
713 break;
714 case CC_OP_FLAGS:
715 /* live. */
716 break;
717 default:
718 {
719 switch (dc->cc_size)
720 {
721 case 4:
722 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
723 break;
724 default:
725 tcg_gen_helper_0_0(helper_evaluate_flags);
726 break;
727 }
728 }
729 break;
730 }
731 if (dc->flagx_known) {
732 if (dc->flags_x)
733 tcg_gen_ori_tl(cpu_PR[PR_CCS],
734 cpu_PR[PR_CCS], X_FLAG);
735 else
736 tcg_gen_andi_tl(cpu_PR[PR_CCS],
737 cpu_PR[PR_CCS], ~X_FLAG);
738 }
739
740 dc->flags_uptodate = 1;
741 }
742 }
743
744 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
745 {
746 uint32_t ovl;
747
748 if (!mask) {
749 dc->update_cc = 0;
750 return;
751 }
752
753 /* Check if we need to evaluate the condition codes due to
754 CC overlaying. */
755 ovl = (dc->cc_mask ^ mask) & ~mask;
756 if (ovl) {
757 /* TODO: optimize this case. It trigs all the time. */
758 cris_evaluate_flags (dc);
759 }
760 dc->cc_mask = mask;
761 dc->update_cc = 1;
762 }
763
764 static void cris_update_cc_op(DisasContext *dc, int op, int size)
765 {
766 dc->cc_op = op;
767 dc->cc_size = size;
768 dc->flags_uptodate = 0;
769 }
770
771 static inline void cris_update_cc_x(DisasContext *dc)
772 {
773 /* Save the x flag state at the time of the cc snapshot. */
774 if (dc->flagx_known) {
775 if (dc->cc_x_uptodate == (2 | dc->flags_x))
776 return;
777 tcg_gen_movi_tl(cc_x, dc->flags_x);
778 dc->cc_x_uptodate = 2 | dc->flags_x;
779 }
780 else {
781 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
782 dc->cc_x_uptodate = 1;
783 }
784 }
785
786 /* Update cc prior to executing ALU op. Needs source operands untouched. */
787 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
788 TCGv dst, TCGv src, int size)
789 {
790 if (dc->update_cc) {
791 cris_update_cc_op(dc, op, size);
792 tcg_gen_mov_tl(cc_src, src);
793
794 if (op != CC_OP_MOVE
795 && op != CC_OP_AND
796 && op != CC_OP_OR
797 && op != CC_OP_XOR
798 && op != CC_OP_ASR
799 && op != CC_OP_LSR
800 && op != CC_OP_LSL)
801 tcg_gen_mov_tl(cc_dest, dst);
802
803 cris_update_cc_x(dc);
804 }
805 }
806
807 /* Update cc after executing ALU op. needs the result. */
808 static inline void cris_update_result(DisasContext *dc, TCGv res)
809 {
810 if (dc->update_cc) {
811 if (dc->cc_size == 4 &&
812 (dc->cc_op == CC_OP_SUB
813 || dc->cc_op == CC_OP_ADD))
814 return;
815 tcg_gen_mov_tl(cc_result, res);
816 }
817 }
818
819 /* Returns one if the write back stage should execute. */
820 static void cris_alu_op_exec(DisasContext *dc, int op,
821 TCGv dst, TCGv a, TCGv b, int size)
822 {
823 /* Emit the ALU insns. */
824 switch (op)
825 {
826 case CC_OP_ADD:
827 tcg_gen_add_tl(dst, a, b);
828 /* Extended arithmetics. */
829 t_gen_addx_carry(dc, dst);
830 break;
831 case CC_OP_ADDC:
832 tcg_gen_add_tl(dst, a, b);
833 t_gen_add_flag(dst, 0); /* C_FLAG. */
834 break;
835 case CC_OP_MCP:
836 tcg_gen_add_tl(dst, a, b);
837 t_gen_add_flag(dst, 8); /* R_FLAG. */
838 break;
839 case CC_OP_SUB:
840 tcg_gen_sub_tl(dst, a, b);
841 /* Extended arithmetics. */
842 t_gen_subx_carry(dc, dst);
843 break;
844 case CC_OP_MOVE:
845 tcg_gen_mov_tl(dst, b);
846 break;
847 case CC_OP_OR:
848 tcg_gen_or_tl(dst, a, b);
849 break;
850 case CC_OP_AND:
851 tcg_gen_and_tl(dst, a, b);
852 break;
853 case CC_OP_XOR:
854 tcg_gen_xor_tl(dst, a, b);
855 break;
856 case CC_OP_LSL:
857 t_gen_lsl(dst, a, b);
858 break;
859 case CC_OP_LSR:
860 t_gen_lsr(dst, a, b);
861 break;
862 case CC_OP_ASR:
863 t_gen_asr(dst, a, b);
864 break;
865 case CC_OP_NEG:
866 tcg_gen_neg_tl(dst, b);
867 /* Extended arithmetics. */
868 t_gen_subx_carry(dc, dst);
869 break;
870 case CC_OP_LZ:
871 t_gen_lz_i32(dst, b);
872 break;
873 case CC_OP_BTST:
874 t_gen_btst(dst, a, b);
875 break;
876 case CC_OP_MULS:
877 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
878 break;
879 case CC_OP_MULU:
880 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
881 break;
882 case CC_OP_DSTEP:
883 t_gen_cris_dstep(dst, a, b);
884 break;
885 case CC_OP_BOUND:
886 {
887 int l1;
888 l1 = gen_new_label();
889 tcg_gen_mov_tl(dst, a);
890 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
891 tcg_gen_mov_tl(dst, b);
892 gen_set_label(l1);
893 }
894 break;
895 case CC_OP_CMP:
896 tcg_gen_sub_tl(dst, a, b);
897 /* Extended arithmetics. */
898 t_gen_subx_carry(dc, dst);
899 break;
900 default:
901 fprintf (logfile, "illegal ALU op.\n");
902 BUG();
903 break;
904 }
905
906 if (size == 1)
907 tcg_gen_andi_tl(dst, dst, 0xff);
908 else if (size == 2)
909 tcg_gen_andi_tl(dst, dst, 0xffff);
910 }
911
912 static void cris_alu(DisasContext *dc, int op,
913 TCGv d, TCGv op_a, TCGv op_b, int size)
914 {
915 TCGv tmp;
916 int writeback;
917
918 writeback = 1;
919 tmp = cpu_T[0];
920 if (op == CC_OP_CMP)
921 writeback = 0;
922 else if (size == 4) {
923 tmp = d;
924 writeback = 0;
925 }
926
927 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
928 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
929 cris_update_result(dc, tmp);
930
931 /* Writeback. */
932 if (writeback) {
933 if (size == 1)
934 tcg_gen_andi_tl(d, d, ~0xff);
935 else
936 tcg_gen_andi_tl(d, d, ~0xffff);
937 tcg_gen_or_tl(d, d, tmp);
938 }
939 }
940
941 static int arith_cc(DisasContext *dc)
942 {
943 if (dc->update_cc) {
944 switch (dc->cc_op) {
945 case CC_OP_ADDC: return 1;
946 case CC_OP_ADD: return 1;
947 case CC_OP_SUB: return 1;
948 case CC_OP_DSTEP: return 1;
949 case CC_OP_LSL: return 1;
950 case CC_OP_LSR: return 1;
951 case CC_OP_ASR: return 1;
952 case CC_OP_CMP: return 1;
953 case CC_OP_NEG: return 1;
954 case CC_OP_OR: return 1;
955 case CC_OP_XOR: return 1;
956 case CC_OP_MULU: return 1;
957 case CC_OP_MULS: return 1;
958 default:
959 return 0;
960 }
961 }
962 return 0;
963 }
964
965 static void gen_tst_cc (DisasContext *dc, int cond)
966 {
967 int arith_opt, move_opt;
968
969 /* TODO: optimize more condition codes. */
970
971 /*
972 * If the flags are live, we've gotta look into the bits of CCS.
973 * Otherwise, if we just did an arithmetic operation we try to
974 * evaluate the condition code faster.
975 *
976 * When this function is done, T0 should be non-zero if the condition
977 * code is true.
978 */
979 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
980 move_opt = (dc->cc_op == CC_OP_MOVE) && !dc->flags_uptodate;
981 switch (cond) {
982 case CC_EQ:
983 if (arith_opt || move_opt) {
984 /* If cc_result is zero, T0 should be
985 non-zero otherwise T0 should be zero. */
986 int l1;
987 l1 = gen_new_label();
988 tcg_gen_movi_tl(cpu_T[0], 0);
989 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
990 0, l1);
991 tcg_gen_movi_tl(cpu_T[0], 1);
992 gen_set_label(l1);
993 }
994 else {
995 cris_evaluate_flags(dc);
996 tcg_gen_andi_tl(cpu_T[0],
997 cpu_PR[PR_CCS], Z_FLAG);
998 }
999 break;
1000 case CC_NE:
1001 if (arith_opt || move_opt)
1002 tcg_gen_mov_tl(cpu_T[0], cc_result);
1003 else {
1004 cris_evaluate_flags(dc);
1005 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1006 Z_FLAG);
1007 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1008 }
1009 break;
1010 case CC_CS:
1011 cris_evaluate_flags(dc);
1012 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
1013 break;
1014 case CC_CC:
1015 cris_evaluate_flags(dc);
1016 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
1017 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
1018 break;
1019 case CC_VS:
1020 cris_evaluate_flags(dc);
1021 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
1022 break;
1023 case CC_VC:
1024 cris_evaluate_flags(dc);
1025 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1026 V_FLAG);
1027 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
1028 break;
1029 case CC_PL:
1030 if (arith_opt || move_opt) {
1031 int bits = 31;
1032
1033 if (dc->cc_size == 1)
1034 bits = 7;
1035 else if (dc->cc_size == 2)
1036 bits = 15;
1037
1038 tcg_gen_shri_tl(cpu_T[0], cc_result, bits);
1039 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
1040 } else {
1041 cris_evaluate_flags(dc);
1042 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1043 N_FLAG);
1044 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1045 }
1046 break;
1047 case CC_MI:
1048 if (arith_opt || move_opt) {
1049 int bits = 31;
1050
1051 if (dc->cc_size == 1)
1052 bits = 7;
1053 else if (dc->cc_size == 2)
1054 bits = 15;
1055
1056 tcg_gen_shri_tl(cpu_T[0], cc_result, 31);
1057 }
1058 else {
1059 cris_evaluate_flags(dc);
1060 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1061 N_FLAG);
1062 }
1063 break;
1064 case CC_LS:
1065 cris_evaluate_flags(dc);
1066 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1067 C_FLAG | Z_FLAG);
1068 break;
1069 case CC_HI:
1070 cris_evaluate_flags(dc);
1071 {
1072 TCGv tmp;
1073
1074 tmp = tcg_temp_new(TCG_TYPE_TL);
1075 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1076 C_FLAG | Z_FLAG);
1077 /* Overlay the C flag on top of the Z. */
1078 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
1079 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
1080 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1081
1082 tcg_temp_free(tmp);
1083 }
1084 break;
1085 case CC_GE:
1086 cris_evaluate_flags(dc);
1087 /* Overlay the V flag on top of the N. */
1088 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1089 tcg_gen_xor_tl(cpu_T[0],
1090 cpu_PR[PR_CCS], cpu_T[0]);
1091 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1092 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
1093 break;
1094 case CC_LT:
1095 cris_evaluate_flags(dc);
1096 /* Overlay the V flag on top of the N. */
1097 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1098 tcg_gen_xor_tl(cpu_T[0],
1099 cpu_PR[PR_CCS], cpu_T[0]);
1100 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1101 break;
1102 case CC_GT:
1103 cris_evaluate_flags(dc);
1104 {
1105 TCGv n, z;
1106
1107 n = tcg_temp_new(TCG_TYPE_TL);
1108 z = tcg_temp_new(TCG_TYPE_TL);
1109
1110 /* To avoid a shift we overlay everything on
1111 the V flag. */
1112 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1113 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1114 /* invert Z. */
1115 tcg_gen_xori_tl(z, z, 2);
1116
1117 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1118 tcg_gen_xori_tl(n, n, 2);
1119 tcg_gen_and_tl(cpu_T[0], z, n);
1120 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1121
1122 tcg_temp_free(n);
1123 tcg_temp_free(z);
1124 }
1125 break;
1126 case CC_LE:
1127 cris_evaluate_flags(dc);
1128 {
1129 TCGv n, z;
1130
1131 n = tcg_temp_new(TCG_TYPE_TL);
1132 z = tcg_temp_new(TCG_TYPE_TL);
1133
1134 /* To avoid a shift we overlay everything on
1135 the V flag. */
1136 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1137 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1138
1139 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1140 tcg_gen_or_tl(cpu_T[0], z, n);
1141 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1142
1143 tcg_temp_free(n);
1144 tcg_temp_free(z);
1145 }
1146 break;
1147 case CC_P:
1148 cris_evaluate_flags(dc);
1149 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
1150 break;
1151 case CC_A:
1152 tcg_gen_movi_tl(cpu_T[0], 1);
1153 break;
1154 default:
1155 BUG();
1156 break;
1157 };
1158 }
1159
1160 static void cris_store_direct_jmp(DisasContext *dc)
1161 {
1162 /* Store the direct jmp state into the cpu-state. */
1163 if (dc->jmp == JMP_DIRECT) {
1164 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1165 tcg_gen_movi_tl(env_btaken, 1);
1166 }
1167 }
1168
1169 static void cris_prepare_cc_branch (DisasContext *dc,
1170 int offset, int cond)
1171 {
1172 /* This helps us re-schedule the micro-code to insns in delay-slots
1173 before the actual jump. */
1174 dc->delayed_branch = 2;
1175 dc->jmp_pc = dc->pc + offset;
1176
1177 if (cond != CC_A)
1178 {
1179 dc->jmp = JMP_INDIRECT;
1180 gen_tst_cc (dc, cond);
1181 tcg_gen_mov_tl(env_btaken, cpu_T[0]);
1182 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1183 } else {
1184 /* Allow chaining. */
1185 dc->jmp = JMP_DIRECT;
1186 }
1187 }
1188
1189
1190 /* jumps, when the dest is in a live reg for example. Direct should be set
1191 when the dest addr is constant to allow tb chaining. */
1192 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1193 {
1194 /* This helps us re-schedule the micro-code to insns in delay-slots
1195 before the actual jump. */
1196 dc->delayed_branch = 2;
1197 dc->jmp = type;
1198 if (type == JMP_INDIRECT)
1199 tcg_gen_movi_tl(env_btaken, 1);
1200 }
1201
1202 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1203 unsigned int size, int sign)
1204 {
1205 int mem_index = cpu_mmu_index(dc->env);
1206
1207 /* If we get a fault on a delayslot we must keep the jmp state in
1208 the cpu-state to be able to re-execute the jmp. */
1209 if (dc->delayed_branch == 1)
1210 cris_store_direct_jmp(dc);
1211
1212 if (size == 1) {
1213 if (sign)
1214 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1215 else
1216 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1217 }
1218 else if (size == 2) {
1219 if (sign)
1220 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1221 else
1222 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1223 }
1224 else {
1225 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1226 }
1227 }
1228
1229 void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1230 unsigned int size)
1231 {
1232 int mem_index = cpu_mmu_index(dc->env);
1233
1234 /* If we get a fault on a delayslot we must keep the jmp state in
1235 the cpu-state to be able to re-execute the jmp. */
1236 if (dc->delayed_branch == 1)
1237 cris_store_direct_jmp(dc);
1238
1239
1240 /* Conditional writes. We only support the kind were X and P are known
1241 at translation time. */
1242 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1243 dc->postinc = 0;
1244 cris_evaluate_flags(dc);
1245 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1246 return;
1247 }
1248
1249 /* Remember, operands are flipped. CRIS has reversed order. */
1250 if (size == 1)
1251 tcg_gen_qemu_st8(val, addr, mem_index);
1252 else if (size == 2)
1253 tcg_gen_qemu_st16(val, addr, mem_index);
1254 else
1255 tcg_gen_qemu_st32(val, addr, mem_index);
1256
1257 if (dc->flagx_known && dc->flags_x) {
1258 cris_evaluate_flags(dc);
1259 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1260 }
1261 }
1262
1263 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1264 {
1265 if (size == 1)
1266 tcg_gen_ext8s_i32(d, s);
1267 else if (size == 2)
1268 tcg_gen_ext16s_i32(d, s);
1269 else if(d != s)
1270 tcg_gen_mov_tl(d, s);
1271 }
1272
1273 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1274 {
1275 if (size == 1)
1276 tcg_gen_ext8u_i32(d, s);
1277 else if (size == 2)
1278 tcg_gen_ext16u_i32(d, s);
1279 else if (d != s)
1280 tcg_gen_mov_tl(d, s);
1281 }
1282
1283 #if DISAS_CRIS
1284 static char memsize_char(int size)
1285 {
1286 switch (size)
1287 {
1288 case 1: return 'b'; break;
1289 case 2: return 'w'; break;
1290 case 4: return 'd'; break;
1291 default:
1292 return 'x';
1293 break;
1294 }
1295 }
1296 #endif
1297
1298 static inline unsigned int memsize_z(DisasContext *dc)
1299 {
1300 return dc->zsize + 1;
1301 }
1302
1303 static inline unsigned int memsize_zz(DisasContext *dc)
1304 {
1305 switch (dc->zzsize)
1306 {
1307 case 0: return 1;
1308 case 1: return 2;
1309 default:
1310 return 4;
1311 }
1312 }
1313
1314 static inline void do_postinc (DisasContext *dc, int size)
1315 {
1316 if (dc->postinc)
1317 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1318 }
1319
1320 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1321 int size, int s_ext, TCGv dst)
1322 {
1323 if (s_ext)
1324 t_gen_sext(dst, cpu_R[rs], size);
1325 else
1326 t_gen_zext(dst, cpu_R[rs], size);
1327 }
1328
1329 /* Prepare T0 and T1 for a register alu operation.
1330 s_ext decides if the operand1 should be sign-extended or zero-extended when
1331 needed. */
1332 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1333 int size, int s_ext)
1334 {
1335 dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);
1336
1337 if (s_ext)
1338 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1339 else
1340 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1341 }
1342
1343 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1344 TCGv dst)
1345 {
1346 unsigned int rs, rd;
1347 uint32_t imm;
1348 int is_imm;
1349 int insn_len = 2;
1350
1351 rs = dc->op1;
1352 rd = dc->op2;
1353 is_imm = rs == 15 && dc->postinc;
1354
1355 /* Load [$rs] onto T1. */
1356 if (is_imm) {
1357 insn_len = 2 + memsize;
1358 if (memsize == 1)
1359 insn_len++;
1360
1361 if (memsize != 4) {
1362 if (s_ext) {
1363 if (memsize == 1)
1364 imm = ldsb_code(dc->pc + 2);
1365 else
1366 imm = ldsw_code(dc->pc + 2);
1367 } else {
1368 if (memsize == 1)
1369 imm = ldub_code(dc->pc + 2);
1370 else
1371 imm = lduw_code(dc->pc + 2);
1372 }
1373 } else
1374 imm = ldl_code(dc->pc + 2);
1375
1376 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1377 imm, rd, s_ext, memsize));
1378 tcg_gen_movi_tl(dst, imm);
1379 dc->postinc = 0;
1380 } else {
1381 cris_flush_cc_state(dc);
1382 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1383 if (s_ext)
1384 t_gen_sext(dst, dst, memsize);
1385 else
1386 t_gen_zext(dst, dst, memsize);
1387 }
1388 return insn_len;
1389 }
1390
1391 /* Prepare T0 and T1 for a memory + alu operation.
1392 s_ext decides if the operand1 should be sign-extended or zero-extended when
1393 needed. */
1394 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1395 {
1396 int insn_len;
1397
1398 insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
1399
1400 /* put dest in T0. */
1401 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
1402 return insn_len;
1403 }
1404
1405 #if DISAS_CRIS
1406 static const char *cc_name(int cc)
1407 {
1408 static char *cc_names[16] = {
1409 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1410 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1411 };
1412 assert(cc < 16);
1413 return cc_names[cc];
1414 }
1415 #endif
1416
1417 /* Start of insn decoders. */
1418
1419 static unsigned int dec_bccq(DisasContext *dc)
1420 {
1421 int32_t offset;
1422 int sign;
1423 uint32_t cond = dc->op2;
1424 int tmp;
1425
1426 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1427 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1428
1429 offset *= 2;
1430 offset |= sign << 8;
1431 tmp = offset;
1432 offset = sign_extend(offset, 8);
1433
1434 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1435
1436 /* op2 holds the condition-code. */
1437 cris_cc_mask(dc, 0);
1438 cris_prepare_cc_branch (dc, offset, cond);
1439 return 2;
1440 }
1441 static unsigned int dec_addoq(DisasContext *dc)
1442 {
1443 int32_t imm;
1444
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1446 imm = sign_extend(dc->op1, 7);
1447
1448 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1449 cris_cc_mask(dc, 0);
1450 /* Fetch register operand, */
1451 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1452 return 2;
1453 }
1454 static unsigned int dec_addq(DisasContext *dc)
1455 {
1456 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1457
1458 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1459
1460 cris_cc_mask(dc, CC_MASK_NZVC);
1461
1462 cris_alu(dc, CC_OP_ADD,
1463 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1464 return 2;
1465 }
1466 static unsigned int dec_moveq(DisasContext *dc)
1467 {
1468 uint32_t imm;
1469
1470 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1471 imm = sign_extend(dc->op1, 5);
1472 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1473
1474 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1475 return 2;
1476 }
1477 static unsigned int dec_subq(DisasContext *dc)
1478 {
1479 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1480
1481 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1482
1483 cris_cc_mask(dc, CC_MASK_NZVC);
1484 cris_alu(dc, CC_OP_SUB,
1485 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1486 return 2;
1487 }
1488 static unsigned int dec_cmpq(DisasContext *dc)
1489 {
1490 uint32_t imm;
1491 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1492 imm = sign_extend(dc->op1, 5);
1493
1494 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1495 cris_cc_mask(dc, CC_MASK_NZVC);
1496
1497 cris_alu(dc, CC_OP_CMP,
1498 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1499 return 2;
1500 }
1501 static unsigned int dec_andq(DisasContext *dc)
1502 {
1503 uint32_t imm;
1504 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1505 imm = sign_extend(dc->op1, 5);
1506
1507 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1508 cris_cc_mask(dc, CC_MASK_NZ);
1509
1510 cris_alu(dc, CC_OP_AND,
1511 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1512 return 2;
1513 }
1514 static unsigned int dec_orq(DisasContext *dc)
1515 {
1516 uint32_t imm;
1517 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1518 imm = sign_extend(dc->op1, 5);
1519 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1520 cris_cc_mask(dc, CC_MASK_NZ);
1521
1522 cris_alu(dc, CC_OP_OR,
1523 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1524 return 2;
1525 }
1526 static unsigned int dec_btstq(DisasContext *dc)
1527 {
1528 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1529 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1530
1531 cris_cc_mask(dc, CC_MASK_NZ);
1532
1533 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1534 cris_alu(dc, CC_OP_BTST,
1535 cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1536 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1537 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1538 dc->flags_uptodate = 1;
1539 return 2;
1540 }
1541 static unsigned int dec_asrq(DisasContext *dc)
1542 {
1543 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1544 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1545 cris_cc_mask(dc, CC_MASK_NZ);
1546
1547 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1548 cris_alu(dc, CC_OP_MOVE,
1549 cpu_R[dc->op2],
1550 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1551 return 2;
1552 }
1553 static unsigned int dec_lslq(DisasContext *dc)
1554 {
1555 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1556 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1557
1558 cris_cc_mask(dc, CC_MASK_NZ);
1559
1560 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1561
1562 cris_alu(dc, CC_OP_MOVE,
1563 cpu_R[dc->op2],
1564 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1565 return 2;
1566 }
1567 static unsigned int dec_lsrq(DisasContext *dc)
1568 {
1569 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1570 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1571
1572 cris_cc_mask(dc, CC_MASK_NZ);
1573
1574 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1575 cris_alu(dc, CC_OP_MOVE,
1576 cpu_R[dc->op2],
1577 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1578 return 2;
1579 }
1580
1581 static unsigned int dec_move_r(DisasContext *dc)
1582 {
1583 int size = memsize_zz(dc);
1584
1585 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1586 memsize_char(size), dc->op1, dc->op2));
1587
1588 cris_cc_mask(dc, CC_MASK_NZ);
1589 if (size == 4) {
1590 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1591 cris_cc_mask(dc, CC_MASK_NZ);
1592 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1593 cris_update_cc_x(dc);
1594 cris_update_result(dc, cpu_R[dc->op2]);
1595 }
1596 else {
1597 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1598 cris_alu(dc, CC_OP_MOVE,
1599 cpu_R[dc->op2],
1600 cpu_R[dc->op2], cpu_T[1], size);
1601 }
1602 return 2;
1603 }
1604
1605 static unsigned int dec_scc_r(DisasContext *dc)
1606 {
1607 int cond = dc->op2;
1608
1609 DIS(fprintf (logfile, "s%s $r%u\n",
1610 cc_name(cond), dc->op1));
1611
1612 if (cond != CC_A)
1613 {
1614 int l1;
1615
1616 gen_tst_cc (dc, cond);
1617
1618 l1 = gen_new_label();
1619 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1620 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
1621 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1622 gen_set_label(l1);
1623 }
1624 else
1625 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1626
1627 cris_cc_mask(dc, 0);
1628 return 2;
1629 }
1630
1631 static unsigned int dec_and_r(DisasContext *dc)
1632 {
1633 int size = memsize_zz(dc);
1634
1635 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1636 memsize_char(size), dc->op1, dc->op2));
1637 cris_cc_mask(dc, CC_MASK_NZ);
1638 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1639
1640 cris_alu(dc, CC_OP_AND,
1641 cpu_R[dc->op2],
1642 cpu_R[dc->op2], cpu_T[1], size);
1643 return 2;
1644 }
1645
1646 static unsigned int dec_lz_r(DisasContext *dc)
1647 {
1648 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1649 dc->op1, dc->op2));
1650 cris_cc_mask(dc, CC_MASK_NZ);
1651 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1652 cris_alu(dc, CC_OP_LZ,
1653 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1654 return 2;
1655 }
1656
1657 static unsigned int dec_lsl_r(DisasContext *dc)
1658 {
1659 int size = memsize_zz(dc);
1660
1661 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1662 memsize_char(size), dc->op1, dc->op2));
1663 cris_cc_mask(dc, CC_MASK_NZ);
1664 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1665 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1666
1667 cris_alu(dc, CC_OP_LSL,
1668 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1669 return 2;
1670 }
1671
1672 static unsigned int dec_lsr_r(DisasContext *dc)
1673 {
1674 int size = memsize_zz(dc);
1675
1676 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1677 memsize_char(size), dc->op1, dc->op2));
1678 cris_cc_mask(dc, CC_MASK_NZ);
1679 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1680 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1681
1682 cris_alu(dc, CC_OP_LSR,
1683 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1684 return 2;
1685 }
1686
1687 static unsigned int dec_asr_r(DisasContext *dc)
1688 {
1689 int size = memsize_zz(dc);
1690
1691 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1692 memsize_char(size), dc->op1, dc->op2));
1693 cris_cc_mask(dc, CC_MASK_NZ);
1694 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1695 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1696
1697 cris_alu(dc, CC_OP_ASR,
1698 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1699 return 2;
1700 }
1701
1702 static unsigned int dec_muls_r(DisasContext *dc)
1703 {
1704 int size = memsize_zz(dc);
1705
1706 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1707 memsize_char(size), dc->op1, dc->op2));
1708 cris_cc_mask(dc, CC_MASK_NZV);
1709 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1710
1711 cris_alu(dc, CC_OP_MULS,
1712 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1713 return 2;
1714 }
1715
1716 static unsigned int dec_mulu_r(DisasContext *dc)
1717 {
1718 int size = memsize_zz(dc);
1719
1720 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1721 memsize_char(size), dc->op1, dc->op2));
1722 cris_cc_mask(dc, CC_MASK_NZV);
1723 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1724
1725 cris_alu(dc, CC_OP_MULU,
1726 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1727 return 2;
1728 }
1729
1730
1731 static unsigned int dec_dstep_r(DisasContext *dc)
1732 {
1733 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1734 cris_cc_mask(dc, CC_MASK_NZ);
1735 cris_alu(dc, CC_OP_DSTEP,
1736 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1737 return 2;
1738 }
1739
1740 static unsigned int dec_xor_r(DisasContext *dc)
1741 {
1742 int size = memsize_zz(dc);
1743 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1744 memsize_char(size), dc->op1, dc->op2));
1745 BUG_ON(size != 4); /* xor is dword. */
1746 cris_cc_mask(dc, CC_MASK_NZ);
1747 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1748
1749 cris_alu(dc, CC_OP_XOR,
1750 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1751 return 2;
1752 }
1753
1754 static unsigned int dec_bound_r(DisasContext *dc)
1755 {
1756 int size = memsize_zz(dc);
1757 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1758 memsize_char(size), dc->op1, dc->op2));
1759 cris_cc_mask(dc, CC_MASK_NZ);
1760 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1761 cris_alu(dc, CC_OP_BOUND,
1762 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1763 return 2;
1764 }
1765
1766 static unsigned int dec_cmp_r(DisasContext *dc)
1767 {
1768 int size = memsize_zz(dc);
1769 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1770 memsize_char(size), dc->op1, dc->op2));
1771 cris_cc_mask(dc, CC_MASK_NZVC);
1772 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1773
1774 cris_alu(dc, CC_OP_CMP,
1775 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1776 return 2;
1777 }
1778
1779 static unsigned int dec_abs_r(DisasContext *dc)
1780 {
1781 int l1;
1782
1783 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1784 dc->op1, dc->op2));
1785 cris_cc_mask(dc, CC_MASK_NZ);
1786 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[1]);
1787
1788 /* TODO: consider a branch free approach. */
1789 l1 = gen_new_label();
1790 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
1791 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
1792 gen_set_label(l1);
1793 cris_alu(dc, CC_OP_MOVE,
1794 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1795 return 2;
1796 }
1797
1798 static unsigned int dec_add_r(DisasContext *dc)
1799 {
1800 int size = memsize_zz(dc);
1801 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1802 memsize_char(size), dc->op1, dc->op2));
1803 cris_cc_mask(dc, CC_MASK_NZVC);
1804 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1805
1806 cris_alu(dc, CC_OP_ADD,
1807 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1808 return 2;
1809 }
1810
1811 static unsigned int dec_addc_r(DisasContext *dc)
1812 {
1813 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1814 dc->op1, dc->op2));
1815 cris_evaluate_flags(dc);
1816 cris_cc_mask(dc, CC_MASK_NZVC);
1817 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1818 cris_alu(dc, CC_OP_ADDC,
1819 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1820 return 2;
1821 }
1822
1823 static unsigned int dec_mcp_r(DisasContext *dc)
1824 {
1825 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1826 dc->op2, dc->op1));
1827 cris_evaluate_flags(dc);
1828 cris_cc_mask(dc, CC_MASK_RNZV);
1829 cris_alu(dc, CC_OP_MCP,
1830 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1831 return 2;
1832 }
1833
1834 #if DISAS_CRIS
1835 static char * swapmode_name(int mode, char *modename) {
1836 int i = 0;
1837 if (mode & 8)
1838 modename[i++] = 'n';
1839 if (mode & 4)
1840 modename[i++] = 'w';
1841 if (mode & 2)
1842 modename[i++] = 'b';
1843 if (mode & 1)
1844 modename[i++] = 'r';
1845 modename[i++] = 0;
1846 return modename;
1847 }
1848 #endif
1849
1850 static unsigned int dec_swap_r(DisasContext *dc)
1851 {
1852 #if DISAS_CRIS
1853 char modename[4];
1854 #endif
1855 DIS(fprintf (logfile, "swap%s $r%u\n",
1856 swapmode_name(dc->op2, modename), dc->op1));
1857
1858 cris_cc_mask(dc, CC_MASK_NZ);
1859 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1860 if (dc->op2 & 8)
1861 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
1862 if (dc->op2 & 4)
1863 t_gen_swapw(cpu_T[0], cpu_T[0]);
1864 if (dc->op2 & 2)
1865 t_gen_swapb(cpu_T[0], cpu_T[0]);
1866 if (dc->op2 & 1)
1867 t_gen_swapr(cpu_T[0], cpu_T[0]);
1868 cris_alu(dc, CC_OP_MOVE,
1869 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0], 4);
1870
1871 return 2;
1872 }
1873
1874 static unsigned int dec_or_r(DisasContext *dc)
1875 {
1876 int size = memsize_zz(dc);
1877 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1878 memsize_char(size), dc->op1, dc->op2));
1879 cris_cc_mask(dc, CC_MASK_NZ);
1880 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1881
1882 cris_alu(dc, CC_OP_OR,
1883 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1884 return 2;
1885 }
1886
1887 static unsigned int dec_addi_r(DisasContext *dc)
1888 {
1889 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1890 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1891 cris_cc_mask(dc, 0);
1892 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1893 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0]);
1894 return 2;
1895 }
1896
1897 static unsigned int dec_addi_acr(DisasContext *dc)
1898 {
1899 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1900 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1901 cris_cc_mask(dc, 0);
1902 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1903 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], cpu_T[0]);
1904 return 2;
1905 }
1906
1907 static unsigned int dec_neg_r(DisasContext *dc)
1908 {
1909 int size = memsize_zz(dc);
1910 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1911 memsize_char(size), dc->op1, dc->op2));
1912 cris_cc_mask(dc, CC_MASK_NZVC);
1913 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1914
1915 cris_alu(dc, CC_OP_NEG,
1916 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1917 return 2;
1918 }
1919
1920 static unsigned int dec_btst_r(DisasContext *dc)
1921 {
1922 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1923 dc->op1, dc->op2));
1924 cris_cc_mask(dc, CC_MASK_NZ);
1925 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1926
1927 cris_alu(dc, CC_OP_BTST,
1928 cpu_T[0], cpu_T[0], cpu_T[1], 4);
1929 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1930 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1931 dc->flags_uptodate = 1;
1932 return 2;
1933 }
1934
1935 static unsigned int dec_sub_r(DisasContext *dc)
1936 {
1937 int size = memsize_zz(dc);
1938 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1939 memsize_char(size), dc->op1, dc->op2));
1940 cris_cc_mask(dc, CC_MASK_NZVC);
1941 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1942 cris_alu(dc, CC_OP_SUB,
1943 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1944 return 2;
1945 }
1946
1947 /* Zero extension. From size to dword. */
1948 static unsigned int dec_movu_r(DisasContext *dc)
1949 {
1950 int size = memsize_z(dc);
1951 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1952 memsize_char(size),
1953 dc->op1, dc->op2));
1954
1955 cris_cc_mask(dc, CC_MASK_NZ);
1956 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1957 cris_alu(dc, CC_OP_MOVE,
1958 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1959 return 2;
1960 }
1961
1962 /* Sign extension. From size to dword. */
1963 static unsigned int dec_movs_r(DisasContext *dc)
1964 {
1965 int size = memsize_z(dc);
1966 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1967 memsize_char(size),
1968 dc->op1, dc->op2));
1969
1970 cris_cc_mask(dc, CC_MASK_NZ);
1971 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1972 /* Size can only be qi or hi. */
1973 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
1974 cris_alu(dc, CC_OP_MOVE,
1975 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1976 return 2;
1977 }
1978
1979 /* zero extension. From size to dword. */
1980 static unsigned int dec_addu_r(DisasContext *dc)
1981 {
1982 int size = memsize_z(dc);
1983 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1984 memsize_char(size),
1985 dc->op1, dc->op2));
1986
1987 cris_cc_mask(dc, CC_MASK_NZVC);
1988 /* Size can only be qi or hi. */
1989 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
1990 cris_alu(dc, CC_OP_ADD,
1991 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1992 return 2;
1993 }
1994
1995 /* Sign extension. From size to dword. */
1996 static unsigned int dec_adds_r(DisasContext *dc)
1997 {
1998 int size = memsize_z(dc);
1999 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2000 memsize_char(size),
2001 dc->op1, dc->op2));
2002
2003 cris_cc_mask(dc, CC_MASK_NZVC);
2004 /* Size can only be qi or hi. */
2005 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2006 cris_alu(dc, CC_OP_ADD,
2007 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2008 return 2;
2009 }
2010
2011 /* Zero extension. From size to dword. */
2012 static unsigned int dec_subu_r(DisasContext *dc)
2013 {
2014 int size = memsize_z(dc);
2015 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2016 memsize_char(size),
2017 dc->op1, dc->op2));
2018
2019 cris_cc_mask(dc, CC_MASK_NZVC);
2020 /* Size can only be qi or hi. */
2021 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
2022 cris_alu(dc, CC_OP_SUB,
2023 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2024 return 2;
2025 }
2026
2027 /* Sign extension. From size to dword. */
2028 static unsigned int dec_subs_r(DisasContext *dc)
2029 {
2030 int size = memsize_z(dc);
2031 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2032 memsize_char(size),
2033 dc->op1, dc->op2));
2034
2035 cris_cc_mask(dc, CC_MASK_NZVC);
2036 /* Size can only be qi or hi. */
2037 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2038 cris_alu(dc, CC_OP_SUB,
2039 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2040 return 2;
2041 }
2042
2043 static unsigned int dec_setclrf(DisasContext *dc)
2044 {
2045 uint32_t flags;
2046 int set = (~dc->opcode >> 2) & 1;
2047
2048 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2049 | EXTRACT_FIELD(dc->ir, 0, 3);
2050 if (set && flags == 0) {
2051 DIS(fprintf (logfile, "nop\n"));
2052 return 2;
2053 } else if (!set && (flags & 0x20)) {
2054 DIS(fprintf (logfile, "di\n"));
2055 }
2056 else {
2057 DIS(fprintf (logfile, "%sf %x\n",
2058 set ? "set" : "clr",
2059 flags));
2060 }
2061
2062 /* User space is not allowed to touch these. Silently ignore. */
2063 if (dc->tb_flags & U_FLAG) {
2064 flags &= ~(I_FLAG | U_FLAG);
2065 }
2066
2067 if (flags & X_FLAG) {
2068 dc->flagx_known = 1;
2069 if (set)
2070 dc->flags_x = X_FLAG;
2071 else
2072 dc->flags_x = 0;
2073 }
2074
2075 /* Break the TB if the P flag changes. */
2076 if (flags & P_FLAG) {
2077 if ((set && !(dc->tb_flags & P_FLAG))
2078 || (!set && (dc->tb_flags & P_FLAG))) {
2079 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2080 dc->is_jmp = DISAS_UPDATE;
2081 dc->cpustate_changed = 1;
2082 }
2083 }
2084
2085
2086 /* Simply decode the flags. */
2087 cris_evaluate_flags (dc);
2088 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2089 cris_update_cc_x(dc);
2090 tcg_gen_movi_tl(cc_op, dc->cc_op);
2091
2092 if (set) {
2093 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2094 /* Enter user mode. */
2095 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2096 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2097 dc->cpustate_changed = 1;
2098 }
2099 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2100 }
2101 else
2102 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2103
2104 dc->flags_uptodate = 1;
2105 dc->clear_x = 0;
2106 return 2;
2107 }
2108
2109 static unsigned int dec_move_rs(DisasContext *dc)
2110 {
2111 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2112 cris_cc_mask(dc, 0);
2113 tcg_gen_helper_0_2(helper_movl_sreg_reg,
2114 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2115 return 2;
2116 }
2117 static unsigned int dec_move_sr(DisasContext *dc)
2118 {
2119 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2120 cris_cc_mask(dc, 0);
2121 tcg_gen_helper_0_2(helper_movl_reg_sreg,
2122 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2123 return 2;
2124 }
2125
2126 static unsigned int dec_move_rp(DisasContext *dc)
2127 {
2128 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2129 cris_cc_mask(dc, 0);
2130
2131 if (dc->op2 == PR_CCS) {
2132 cris_evaluate_flags(dc);
2133 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2134 if (dc->tb_flags & U_FLAG) {
2135 /* User space is not allowed to touch all flags. */
2136 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
2137 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
2138 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
2139 }
2140 }
2141 else
2142 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2143
2144 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
2145 if (dc->op2 == PR_CCS) {
2146 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2147 dc->flags_uptodate = 1;
2148 }
2149 return 2;
2150 }
2151 static unsigned int dec_move_pr(DisasContext *dc)
2152 {
2153 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2154 cris_cc_mask(dc, 0);
2155
2156 if (dc->op2 == PR_CCS)
2157 cris_evaluate_flags(dc);
2158
2159 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2160 cris_alu(dc, CC_OP_MOVE,
2161 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
2162 preg_sizes[dc->op2]);
2163 return 2;
2164 }
2165
2166 static unsigned int dec_move_mr(DisasContext *dc)
2167 {
2168 int memsize = memsize_zz(dc);
2169 int insn_len;
2170 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2171 memsize_char(memsize),
2172 dc->op1, dc->postinc ? "+]" : "]",
2173 dc->op2));
2174
2175 if (memsize == 4) {
2176 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2177 cris_cc_mask(dc, CC_MASK_NZ);
2178 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2179 cris_update_cc_x(dc);
2180 cris_update_result(dc, cpu_R[dc->op2]);
2181 }
2182 else {
2183 insn_len = dec_prep_move_m(dc, 0, memsize, cpu_T[1]);
2184 cris_cc_mask(dc, CC_MASK_NZ);
2185 cris_alu(dc, CC_OP_MOVE,
2186 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], memsize);
2187 }
2188 do_postinc(dc, memsize);
2189 return insn_len;
2190 }
2191
2192 static unsigned int dec_movs_m(DisasContext *dc)
2193 {
2194 int memsize = memsize_z(dc);
2195 int insn_len;
2196 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2197 memsize_char(memsize),
2198 dc->op1, dc->postinc ? "+]" : "]",
2199 dc->op2));
2200
2201 /* sign extend. */
2202 insn_len = dec_prep_alu_m(dc, 1, memsize);
2203 cris_cc_mask(dc, CC_MASK_NZ);
2204 cris_alu(dc, CC_OP_MOVE,
2205 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2206 do_postinc(dc, memsize);
2207 return insn_len;
2208 }
2209
2210 static unsigned int dec_addu_m(DisasContext *dc)
2211 {
2212 int memsize = memsize_z(dc);
2213 int insn_len;
2214 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2215 memsize_char(memsize),
2216 dc->op1, dc->postinc ? "+]" : "]",
2217 dc->op2));
2218
2219 /* sign extend. */
2220 insn_len = dec_prep_alu_m(dc, 0, memsize);
2221 cris_cc_mask(dc, CC_MASK_NZVC);
2222 cris_alu(dc, CC_OP_ADD,
2223 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2224 do_postinc(dc, memsize);
2225 return insn_len;
2226 }
2227
2228 static unsigned int dec_adds_m(DisasContext *dc)
2229 {
2230 int memsize = memsize_z(dc);
2231 int insn_len;
2232 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2233 memsize_char(memsize),
2234 dc->op1, dc->postinc ? "+]" : "]",
2235 dc->op2));
2236
2237 /* sign extend. */
2238 insn_len = dec_prep_alu_m(dc, 1, memsize);
2239 cris_cc_mask(dc, CC_MASK_NZVC);
2240 cris_alu(dc, CC_OP_ADD,
2241 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2242 do_postinc(dc, memsize);
2243 return insn_len;
2244 }
2245
2246 static unsigned int dec_subu_m(DisasContext *dc)
2247 {
2248 int memsize = memsize_z(dc);
2249 int insn_len;
2250 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2251 memsize_char(memsize),
2252 dc->op1, dc->postinc ? "+]" : "]",
2253 dc->op2));
2254
2255 /* sign extend. */
2256 insn_len = dec_prep_alu_m(dc, 0, memsize);
2257 cris_cc_mask(dc, CC_MASK_NZVC);
2258 cris_alu(dc, CC_OP_SUB,
2259 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2260 do_postinc(dc, memsize);
2261 return insn_len;
2262 }
2263
2264 static unsigned int dec_subs_m(DisasContext *dc)
2265 {
2266 int memsize = memsize_z(dc);
2267 int insn_len;
2268 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2269 memsize_char(memsize),
2270 dc->op1, dc->postinc ? "+]" : "]",
2271 dc->op2));
2272
2273 /* sign extend. */
2274 insn_len = dec_prep_alu_m(dc, 1, memsize);
2275 cris_cc_mask(dc, CC_MASK_NZVC);
2276 cris_alu(dc, CC_OP_SUB,
2277 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2278 do_postinc(dc, memsize);
2279 return insn_len;
2280 }
2281
2282 static unsigned int dec_movu_m(DisasContext *dc)
2283 {
2284 int memsize = memsize_z(dc);
2285 int insn_len;
2286
2287 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2288 memsize_char(memsize),
2289 dc->op1, dc->postinc ? "+]" : "]",
2290 dc->op2));
2291
2292 insn_len = dec_prep_alu_m(dc, 0, memsize);
2293 cris_cc_mask(dc, CC_MASK_NZ);
2294 cris_alu(dc, CC_OP_MOVE,
2295 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2296 do_postinc(dc, memsize);
2297 return insn_len;
2298 }
2299
2300 static unsigned int dec_cmpu_m(DisasContext *dc)
2301 {
2302 int memsize = memsize_z(dc);
2303 int insn_len;
2304 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2305 memsize_char(memsize),
2306 dc->op1, dc->postinc ? "+]" : "]",
2307 dc->op2));
2308
2309 insn_len = dec_prep_alu_m(dc, 0, memsize);
2310 cris_cc_mask(dc, CC_MASK_NZVC);
2311 cris_alu(dc, CC_OP_CMP,
2312 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2313 do_postinc(dc, memsize);
2314 return insn_len;
2315 }
2316
2317 static unsigned int dec_cmps_m(DisasContext *dc)
2318 {
2319 int memsize = memsize_z(dc);
2320 int insn_len;
2321 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2322 memsize_char(memsize),
2323 dc->op1, dc->postinc ? "+]" : "]",
2324 dc->op2));
2325
2326 insn_len = dec_prep_alu_m(dc, 1, memsize);
2327 cris_cc_mask(dc, CC_MASK_NZVC);
2328 cris_alu(dc, CC_OP_CMP,
2329 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2330 memsize_zz(dc));
2331 do_postinc(dc, memsize);
2332 return insn_len;
2333 }
2334
2335 static unsigned int dec_cmp_m(DisasContext *dc)
2336 {
2337 int memsize = memsize_zz(dc);
2338 int insn_len;
2339 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2340 memsize_char(memsize),
2341 dc->op1, dc->postinc ? "+]" : "]",
2342 dc->op2));
2343
2344 insn_len = dec_prep_alu_m(dc, 0, memsize);
2345 cris_cc_mask(dc, CC_MASK_NZVC);
2346 cris_alu(dc, CC_OP_CMP,
2347 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2348 memsize_zz(dc));
2349 do_postinc(dc, memsize);
2350 return insn_len;
2351 }
2352
2353 static unsigned int dec_test_m(DisasContext *dc)
2354 {
2355 int memsize = memsize_zz(dc);
2356 int insn_len;
2357 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2358 memsize_char(memsize),
2359 dc->op1, dc->postinc ? "+]" : "]",
2360 dc->op2));
2361
2362 cris_evaluate_flags(dc);
2363
2364 insn_len = dec_prep_alu_m(dc, 0, memsize);
2365 cris_cc_mask(dc, CC_MASK_NZ);
2366 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2367
2368 cris_alu(dc, CC_OP_CMP,
2369 cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
2370 memsize_zz(dc));
2371 do_postinc(dc, memsize);
2372 return insn_len;
2373 }
2374
2375 static unsigned int dec_and_m(DisasContext *dc)
2376 {
2377 int memsize = memsize_zz(dc);
2378 int insn_len;
2379 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2380 memsize_char(memsize),
2381 dc->op1, dc->postinc ? "+]" : "]",
2382 dc->op2));
2383
2384 insn_len = dec_prep_alu_m(dc, 0, memsize);
2385 cris_cc_mask(dc, CC_MASK_NZ);
2386 cris_alu(dc, CC_OP_AND,
2387 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2388 memsize_zz(dc));
2389 do_postinc(dc, memsize);
2390 return insn_len;
2391 }
2392
2393 static unsigned int dec_add_m(DisasContext *dc)
2394 {
2395 int memsize = memsize_zz(dc);
2396 int insn_len;
2397 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2398 memsize_char(memsize),
2399 dc->op1, dc->postinc ? "+]" : "]",
2400 dc->op2));
2401
2402 insn_len = dec_prep_alu_m(dc, 0, memsize);
2403 cris_cc_mask(dc, CC_MASK_NZVC);
2404 cris_alu(dc, CC_OP_ADD,
2405 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2406 memsize_zz(dc));
2407 do_postinc(dc, memsize);
2408 return insn_len;
2409 }
2410
2411 static unsigned int dec_addo_m(DisasContext *dc)
2412 {
2413 int memsize = memsize_zz(dc);
2414 int insn_len;
2415 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2416 memsize_char(memsize),
2417 dc->op1, dc->postinc ? "+]" : "]",
2418 dc->op2));
2419
2420 insn_len = dec_prep_alu_m(dc, 1, memsize);
2421 cris_cc_mask(dc, 0);
2422 cris_alu(dc, CC_OP_ADD,
2423 cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
2424 do_postinc(dc, memsize);
2425 return insn_len;
2426 }
2427
2428 static unsigned int dec_bound_m(DisasContext *dc)
2429 {
2430 int memsize = memsize_zz(dc);
2431 int insn_len;
2432 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2433 memsize_char(memsize),
2434 dc->op1, dc->postinc ? "+]" : "]",
2435 dc->op2));
2436
2437 insn_len = dec_prep_alu_m(dc, 0, memsize);
2438 cris_cc_mask(dc, CC_MASK_NZ);
2439 cris_alu(dc, CC_OP_BOUND,
2440 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2441 do_postinc(dc, memsize);
2442 return insn_len;
2443 }
2444
2445 static unsigned int dec_addc_mr(DisasContext *dc)
2446 {
2447 int insn_len = 2;
2448 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2449 dc->op1, dc->postinc ? "+]" : "]",
2450 dc->op2));
2451
2452 cris_evaluate_flags(dc);
2453 insn_len = dec_prep_alu_m(dc, 0, 4);
2454 cris_cc_mask(dc, CC_MASK_NZVC);
2455 cris_alu(dc, CC_OP_ADDC,
2456 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2457 do_postinc(dc, 4);
2458 return insn_len;
2459 }
2460
2461 static unsigned int dec_sub_m(DisasContext *dc)
2462 {
2463 int memsize = memsize_zz(dc);
2464 int insn_len;
2465 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2466 memsize_char(memsize),
2467 dc->op1, dc->postinc ? "+]" : "]",
2468 dc->op2, dc->ir, dc->zzsize));
2469
2470 insn_len = dec_prep_alu_m(dc, 0, memsize);
2471 cris_cc_mask(dc, CC_MASK_NZVC);
2472 cris_alu(dc, CC_OP_SUB,
2473 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
2474 do_postinc(dc, memsize);
2475 return insn_len;
2476 }
2477
2478 static unsigned int dec_or_m(DisasContext *dc)
2479 {
2480 int memsize = memsize_zz(dc);
2481 int insn_len;
2482 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2483 memsize_char(memsize),
2484 dc->op1, dc->postinc ? "+]" : "]",
2485 dc->op2, dc->pc));
2486
2487 insn_len = dec_prep_alu_m(dc, 0, memsize);
2488 cris_cc_mask(dc, CC_MASK_NZ);
2489 cris_alu(dc, CC_OP_OR,
2490 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
2491 do_postinc(dc, memsize);
2492 return insn_len;
2493 }
2494
2495 static unsigned int dec_move_mp(DisasContext *dc)
2496 {
2497 int memsize = memsize_zz(dc);
2498 int insn_len = 2;
2499
2500 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2501 memsize_char(memsize),
2502 dc->op1,
2503 dc->postinc ? "+]" : "]",
2504 dc->op2));
2505
2506 insn_len = dec_prep_alu_m(dc, 0, memsize);
2507 cris_cc_mask(dc, 0);
2508 if (dc->op2 == PR_CCS) {
2509 cris_evaluate_flags(dc);
2510 if (dc->tb_flags & U_FLAG) {
2511 /* User space is not allowed to touch all flags. */
2512 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2513 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2514 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2515 }
2516 }
2517
2518 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
2519
2520 do_postinc(dc, memsize);
2521 return insn_len;
2522 }
2523
2524 static unsigned int dec_move_pm(DisasContext *dc)
2525 {
2526 int memsize;
2527
2528 memsize = preg_sizes[dc->op2];
2529
2530 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2531 memsize_char(memsize),
2532 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2533
2534 /* prepare store. Address in T0, value in T1. */
2535 if (dc->op2 == PR_CCS)
2536 cris_evaluate_flags(dc);
2537 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2538 cris_flush_cc_state(dc);
2539 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2540
2541 cris_cc_mask(dc, 0);
2542 if (dc->postinc)
2543 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2544 return 2;
2545 }
2546
2547 static unsigned int dec_movem_mr(DisasContext *dc)
2548 {
2549 TCGv tmp[16];
2550 int i;
2551
2552 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2553 dc->postinc ? "+]" : "]", dc->op2));
2554
2555 /* fetch the address into T0 and T1. */
2556 cris_flush_cc_state(dc);
2557 for (i = 0; i <= dc->op2; i++) {
2558 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
2559 /* Perform the load onto regnum i. Always dword wide. */
2560 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2561 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2562 }
2563
2564 for (i = 0; i <= dc->op2; i++) {
2565 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2566 tcg_temp_free(tmp[i]);
2567 }
2568
2569 /* writeback the updated pointer value. */
2570 if (dc->postinc)
2571 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2572
2573 /* gen_load might want to evaluate the previous insns flags. */
2574 cris_cc_mask(dc, 0);
2575 return 2;
2576 }
2577
2578 static unsigned int dec_movem_rm(DisasContext *dc)
2579 {
2580 TCGv tmp;
2581 int i;
2582
2583 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2584 dc->postinc ? "+]" : "]"));
2585
2586 cris_flush_cc_state(dc);
2587
2588 tmp = tcg_temp_new(TCG_TYPE_TL);
2589 tcg_gen_movi_tl(tmp, 4);
2590 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
2591 for (i = 0; i <= dc->op2; i++) {
2592 /* Displace addr. */
2593 /* Perform the store. */
2594 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2595 tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
2596 }
2597 if (dc->postinc)
2598 tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
2599 cris_cc_mask(dc, 0);
2600 tcg_temp_free(tmp);
2601 return 2;
2602 }
2603
2604 static unsigned int dec_move_rm(DisasContext *dc)
2605 {
2606 int memsize;
2607
2608 memsize = memsize_zz(dc);
2609
2610 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2611 memsize, dc->op2, dc->op1));
2612
2613 /* prepare store. */
2614 cris_flush_cc_state(dc);
2615 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2616
2617 if (dc->postinc)
2618 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2619 cris_cc_mask(dc, 0);
2620 return 2;
2621 }
2622
2623 static unsigned int dec_lapcq(DisasContext *dc)
2624 {
2625 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2626 dc->pc + dc->op1*2, dc->op2));
2627 cris_cc_mask(dc, 0);
2628 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2629 return 2;
2630 }
2631
2632 static unsigned int dec_lapc_im(DisasContext *dc)
2633 {
2634 unsigned int rd;
2635 int32_t imm;
2636 int32_t pc;
2637
2638 rd = dc->op2;
2639
2640 cris_cc_mask(dc, 0);
2641 imm = ldl_code(dc->pc + 2);
2642 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2643
2644 pc = dc->pc;
2645 pc += imm;
2646 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2647 return 6;
2648 }
2649
2650 /* Jump to special reg. */
2651 static unsigned int dec_jump_p(DisasContext *dc)
2652 {
2653 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2654
2655 if (dc->op2 == PR_CCS)
2656 cris_evaluate_flags(dc);
2657 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2658 /* rete will often have low bit set to indicate delayslot. */
2659 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2660 cris_cc_mask(dc, 0);
2661 cris_prepare_jmp(dc, JMP_INDIRECT);
2662 return 2;
2663 }
2664
2665 /* Jump and save. */
2666 static unsigned int dec_jas_r(DisasContext *dc)
2667 {
2668 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2669 cris_cc_mask(dc, 0);
2670 /* Store the return address in Pd. */
2671 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2672 if (dc->op2 > 15)
2673 abort();
2674 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2675
2676 cris_prepare_jmp(dc, JMP_INDIRECT);
2677 return 2;
2678 }
2679
2680 static unsigned int dec_jas_im(DisasContext *dc)
2681 {
2682 uint32_t imm;
2683
2684 imm = ldl_code(dc->pc + 2);
2685
2686 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2687 cris_cc_mask(dc, 0);
2688 /* Store the return address in Pd. */
2689 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2690
2691 dc->jmp_pc = imm;
2692 cris_prepare_jmp(dc, JMP_DIRECT);
2693 return 6;
2694 }
2695
2696 static unsigned int dec_jasc_im(DisasContext *dc)
2697 {
2698 uint32_t imm;
2699
2700 imm = ldl_code(dc->pc + 2);
2701
2702 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2703 cris_cc_mask(dc, 0);
2704 /* Store the return address in Pd. */
2705 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2706
2707 dc->jmp_pc = imm;
2708 cris_prepare_jmp(dc, JMP_DIRECT);
2709 return 6;
2710 }
2711
2712 static unsigned int dec_jasc_r(DisasContext *dc)
2713 {
2714 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2715 cris_cc_mask(dc, 0);
2716 /* Store the return address in Pd. */
2717 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2718 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2719 cris_prepare_jmp(dc, JMP_INDIRECT);
2720 return 2;
2721 }
2722
2723 static unsigned int dec_bcc_im(DisasContext *dc)
2724 {
2725 int32_t offset;
2726 uint32_t cond = dc->op2;
2727
2728 offset = ldsw_code(dc->pc + 2);
2729
2730 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2731 cc_name(cond), offset,
2732 dc->pc, dc->pc + offset));
2733
2734 cris_cc_mask(dc, 0);
2735 /* op2 holds the condition-code. */
2736 cris_prepare_cc_branch (dc, offset, cond);
2737 return 4;
2738 }
2739
2740 static unsigned int dec_bas_im(DisasContext *dc)
2741 {
2742 int32_t simm;
2743
2744
2745 simm = ldl_code(dc->pc + 2);
2746
2747 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2748 cris_cc_mask(dc, 0);
2749 /* Store the return address in Pd. */
2750 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2751
2752 dc->jmp_pc = dc->pc + simm;
2753 cris_prepare_jmp(dc, JMP_DIRECT);
2754 return 6;
2755 }
2756
2757 static unsigned int dec_basc_im(DisasContext *dc)
2758 {
2759 int32_t simm;
2760 simm = ldl_code(dc->pc + 2);
2761
2762 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2763 cris_cc_mask(dc, 0);
2764 /* Store the return address in Pd. */
2765 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2766
2767 dc->jmp_pc = dc->pc + simm;
2768 cris_prepare_jmp(dc, JMP_DIRECT);
2769 return 6;
2770 }
2771
2772 static unsigned int dec_rfe_etc(DisasContext *dc)
2773 {
2774 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2775 dc->opcode, dc->pc, dc->op1, dc->op2));
2776
2777 cris_cc_mask(dc, 0);
2778
2779 if (dc->op2 == 15) /* ignore halt. */
2780 return 2;
2781
2782 switch (dc->op2 & 7) {
2783 case 2:
2784 /* rfe. */
2785 cris_evaluate_flags(dc);
2786 tcg_gen_helper_0_0(helper_rfe);
2787 dc->is_jmp = DISAS_UPDATE;
2788 break;
2789 case 5:
2790 /* rfn. */
2791 BUG();
2792 break;
2793 case 6:
2794 /* break. */
2795 tcg_gen_movi_tl(env_pc, dc->pc);
2796 /* Breaks start at 16 in the exception vector. */
2797 t_gen_mov_env_TN(trap_vector,
2798 tcg_const_tl(dc->op1 + 16));
2799 t_gen_raise_exception(EXCP_BREAK);
2800 dc->is_jmp = DISAS_UPDATE;
2801 break;
2802 default:
2803 printf ("op2=%x\n", dc->op2);
2804 BUG();
2805 break;
2806
2807 }
2808 return 2;
2809 }
2810
2811 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2812 {
2813 /* Ignore D-cache flushes. */
2814 return 2;
2815 }
2816
2817 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2818 {
2819 /* Ignore I-cache flushes. */
2820 return 2;
2821 }
2822
2823 static unsigned int dec_null(DisasContext *dc)
2824 {
2825 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2826 dc->pc, dc->opcode, dc->op1, dc->op2);
2827 fflush(NULL);
2828 BUG();
2829 return 2;
2830 }
2831
2832 struct decoder_info {
2833 struct {
2834 uint32_t bits;
2835 uint32_t mask;
2836 };
2837 unsigned int (*dec)(DisasContext *dc);
2838 } decinfo[] = {
2839 /* Order matters here. */
2840 {DEC_MOVEQ, dec_moveq},
2841 {DEC_BTSTQ, dec_btstq},
2842 {DEC_CMPQ, dec_cmpq},
2843 {DEC_ADDOQ, dec_addoq},
2844 {DEC_ADDQ, dec_addq},
2845 {DEC_SUBQ, dec_subq},
2846 {DEC_ANDQ, dec_andq},
2847 {DEC_ORQ, dec_orq},
2848 {DEC_ASRQ, dec_asrq},
2849 {DEC_LSLQ, dec_lslq},
2850 {DEC_LSRQ, dec_lsrq},
2851 {DEC_BCCQ, dec_bccq},
2852
2853 {DEC_BCC_IM, dec_bcc_im},
2854 {DEC_JAS_IM, dec_jas_im},
2855 {DEC_JAS_R, dec_jas_r},
2856 {DEC_JASC_IM, dec_jasc_im},
2857 {DEC_JASC_R, dec_jasc_r},
2858 {DEC_BAS_IM, dec_bas_im},
2859 {DEC_BASC_IM, dec_basc_im},
2860 {DEC_JUMP_P, dec_jump_p},
2861 {DEC_LAPC_IM, dec_lapc_im},
2862 {DEC_LAPCQ, dec_lapcq},
2863
2864 {DEC_RFE_ETC, dec_rfe_etc},
2865 {DEC_ADDC_MR, dec_addc_mr},
2866
2867 {DEC_MOVE_MP, dec_move_mp},
2868 {DEC_MOVE_PM, dec_move_pm},
2869 {DEC_MOVEM_MR, dec_movem_mr},
2870 {DEC_MOVEM_RM, dec_movem_rm},
2871 {DEC_MOVE_PR, dec_move_pr},
2872 {DEC_SCC_R, dec_scc_r},
2873 {DEC_SETF, dec_setclrf},
2874 {DEC_CLEARF, dec_setclrf},
2875
2876 {DEC_MOVE_SR, dec_move_sr},
2877 {DEC_MOVE_RP, dec_move_rp},
2878 {DEC_SWAP_R, dec_swap_r},
2879 {DEC_ABS_R, dec_abs_r},
2880 {DEC_LZ_R, dec_lz_r},
2881 {DEC_MOVE_RS, dec_move_rs},
2882 {DEC_BTST_R, dec_btst_r},
2883 {DEC_ADDC_R, dec_addc_r},
2884
2885 {DEC_DSTEP_R, dec_dstep_r},
2886 {DEC_XOR_R, dec_xor_r},
2887 {DEC_MCP_R, dec_mcp_r},
2888 {DEC_CMP_R, dec_cmp_r},
2889
2890 {DEC_ADDI_R, dec_addi_r},
2891 {DEC_ADDI_ACR, dec_addi_acr},
2892
2893 {DEC_ADD_R, dec_add_r},
2894 {DEC_SUB_R, dec_sub_r},
2895
2896 {DEC_ADDU_R, dec_addu_r},
2897 {DEC_ADDS_R, dec_adds_r},
2898 {DEC_SUBU_R, dec_subu_r},
2899 {DEC_SUBS_R, dec_subs_r},
2900 {DEC_LSL_R, dec_lsl_r},
2901
2902 {DEC_AND_R, dec_and_r},
2903 {DEC_OR_R, dec_or_r},
2904 {DEC_BOUND_R, dec_bound_r},
2905 {DEC_ASR_R, dec_asr_r},
2906 {DEC_LSR_R, dec_lsr_r},
2907
2908 {DEC_MOVU_R, dec_movu_r},
2909 {DEC_MOVS_R, dec_movs_r},
2910 {DEC_NEG_R, dec_neg_r},
2911 {DEC_MOVE_R, dec_move_r},
2912
2913 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2914 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2915
2916 {DEC_MULS_R, dec_muls_r},
2917 {DEC_MULU_R, dec_mulu_r},
2918
2919 {DEC_ADDU_M, dec_addu_m},
2920 {DEC_ADDS_M, dec_adds_m},
2921 {DEC_SUBU_M, dec_subu_m},
2922 {DEC_SUBS_M, dec_subs_m},
2923
2924 {DEC_CMPU_M, dec_cmpu_m},
2925 {DEC_CMPS_M, dec_cmps_m},
2926 {DEC_MOVU_M, dec_movu_m},
2927 {DEC_MOVS_M, dec_movs_m},
2928
2929 {DEC_CMP_M, dec_cmp_m},
2930 {DEC_ADDO_M, dec_addo_m},
2931 {DEC_BOUND_M, dec_bound_m},
2932 {DEC_ADD_M, dec_add_m},
2933 {DEC_SUB_M, dec_sub_m},
2934 {DEC_AND_M, dec_and_m},
2935 {DEC_OR_M, dec_or_m},
2936 {DEC_MOVE_RM, dec_move_rm},
2937 {DEC_TEST_M, dec_test_m},
2938 {DEC_MOVE_MR, dec_move_mr},
2939
2940 {{0, 0}, dec_null}
2941 };
2942
2943 static inline unsigned int
2944 cris_decoder(DisasContext *dc)
2945 {
2946 unsigned int insn_len = 2;
2947 int i;
2948
2949 /* Load a halfword onto the instruction register. */
2950 dc->ir = lduw_code(dc->pc);
2951
2952 /* Now decode it. */
2953 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2954 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2955 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2956 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2957 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2958 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2959
2960 /* Large switch for all insns. */
2961 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2962 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2963 {
2964 insn_len = decinfo[i].dec(dc);
2965 break;
2966 }
2967 }
2968
2969 return insn_len;
2970 }
2971
2972 static void check_breakpoint(CPUState *env, DisasContext *dc)
2973 {
2974 int j;
2975 if (env->nb_breakpoints > 0) {
2976 for(j = 0; j < env->nb_breakpoints; j++) {
2977 if (env->breakpoints[j] == dc->pc) {
2978 cris_evaluate_flags (dc);
2979 tcg_gen_movi_tl(env_pc, dc->pc);
2980 t_gen_raise_exception(EXCP_DEBUG);
2981 dc->is_jmp = DISAS_UPDATE;
2982 }
2983 }
2984 }
2985 }
2986
2987
2988 /*
2989 * Delay slots on QEMU/CRIS.
2990 *
2991 * If an exception hits on a delayslot, the core will let ERP (the Exception
2992 * Return Pointer) point to the branch (the previous) insn and set the lsb to
2993 * to give SW a hint that the exception actually hit on the dslot.
2994 *
2995 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
2996 * the core and any jmp to an odd addresses will mask off that lsb. It is
2997 * simply there to let sw know there was an exception on a dslot.
2998 *
2999 * When the software returns from an exception, the branch will re-execute.
3000 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3001 * and the branch and delayslot dont share pages.
3002 *
3003 * The TB contaning the branch insn will set up env->btarget and evaluate
3004 * env->btaken. When the translation loop exits we will note that the branch
3005 * sequence is broken and let env->dslot be the size of the branch insn (those
3006 * vary in length).
3007 *
3008 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3009 * set). It will also expect to have env->dslot setup with the size of the
3010 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3011 * will execute the dslot and take the branch, either to btarget or just one
3012 * insn ahead.
3013 *
3014 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3015 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3016 * branch and set lsb). Then env->dslot gets cleared so that the exception
3017 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3018 * masked off and we will reexecute the branch insn.
3019 *
3020 */
3021
3022 /* generate intermediate code for basic block 'tb'. */
3023 static int
3024 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3025 int search_pc)
3026 {
3027 uint16_t *gen_opc_end;
3028 uint32_t pc_start;
3029 unsigned int insn_len;
3030 int j, lj;
3031 struct DisasContext ctx;
3032 struct DisasContext *dc = &ctx;
3033 uint32_t next_page_start;
3034 target_ulong npc;
3035
3036 if (!logfile)
3037 logfile = stderr;
3038
3039 /* Odd PC indicates that branch is rexecuting due to exception in the
3040 * delayslot, like in real hw.
3041 */
3042 pc_start = tb->pc & ~1;
3043 dc->env = env;
3044 dc->tb = tb;
3045
3046 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3047
3048 dc->is_jmp = DISAS_NEXT;
3049 dc->ppc = pc_start;
3050 dc->pc = pc_start;
3051 dc->singlestep_enabled = env->singlestep_enabled;
3052 dc->flags_uptodate = 1;
3053 dc->flagx_known = 1;
3054 dc->flags_x = tb->flags & X_FLAG;
3055 dc->cc_x_uptodate = 0;
3056 dc->cc_mask = 0;
3057 dc->update_cc = 0;
3058
3059 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3060 dc->cc_size_uptodate = -1;
3061
3062 /* Decode TB flags. */
3063 dc->tb_flags = tb->flags & (P_FLAG | U_FLAG | X_FLAG);
3064 dc->delayed_branch = !!(tb->flags & 7);
3065 if (dc->delayed_branch)
3066 dc->jmp = JMP_INDIRECT;
3067 else
3068 dc->jmp = JMP_NOJMP;
3069
3070 dc->cpustate_changed = 0;
3071
3072 if (loglevel & CPU_LOG_TB_IN_ASM) {
3073 fprintf(logfile,
3074 "srch=%d pc=%x %x flg=%llx bt=%x ds=%lld ccs=%x\n"
3075 "pid=%x usp=%x\n"
3076 "%x.%x.%x.%x\n"
3077 "%x.%x.%x.%x\n"
3078 "%x.%x.%x.%x\n"
3079 "%x.%x.%x.%x\n",
3080 search_pc, dc->pc, dc->ppc, tb->flags,
3081 env->btarget, tb->flags & 7,
3082 env->pregs[PR_CCS],
3083 env->pregs[PR_PID], env->pregs[PR_USP],
3084 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3085 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3086 env->regs[8], env->regs[9],
3087 env->regs[10], env->regs[11],
3088 env->regs[12], env->regs[13],
3089 env->regs[14], env->regs[15]);
3090
3091 }
3092
3093 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3094 lj = -1;
3095 do
3096 {
3097 check_breakpoint(env, dc);
3098
3099 if (search_pc) {
3100 j = gen_opc_ptr - gen_opc_buf;
3101 if (lj < j) {
3102 lj++;
3103 while (lj < j)
3104 gen_opc_instr_start[lj++] = 0;
3105 }
3106 if (dc->delayed_branch == 1)
3107 gen_opc_pc[lj] = dc->ppc | 1;
3108 else
3109 gen_opc_pc[lj] = dc->pc;
3110 gen_opc_instr_start[lj] = 1;
3111 }
3112
3113 /* Pretty disas. */
3114 DIS(fprintf(logfile, "%x ", dc->pc));
3115 if (search_pc) {
3116 DIS(fprintf(logfile, "%x ", dc->pc));
3117 }
3118
3119 dc->clear_x = 1;
3120 if (unlikely(loglevel & CPU_LOG_TB_OP))
3121 tcg_gen_debug_insn_start(dc->pc);
3122 insn_len = cris_decoder(dc);
3123 dc->ppc = dc->pc;
3124 dc->pc += insn_len;
3125 if (dc->clear_x)
3126 cris_clear_x_flag(dc);
3127
3128 /* Check for delayed branches here. If we do it before
3129 actually genereating any host code, the simulator will just
3130 loop doing nothing for on this program location. */
3131 if (dc->delayed_branch) {
3132 dc->delayed_branch--;
3133 if (dc->delayed_branch == 0)
3134 {
3135 if (tb->flags & 7)
3136 t_gen_mov_env_TN(dslot,
3137 tcg_const_tl(0));
3138 if (dc->jmp == JMP_DIRECT) {
3139 dc->is_jmp = DISAS_NEXT;
3140 } else {
3141 t_gen_cc_jmp(env_btarget,
3142 tcg_const_tl(dc->pc));
3143 dc->is_jmp = DISAS_JUMP;
3144 }
3145 break;
3146 }
3147 }
3148
3149 /* If we are rexecuting a branch due to exceptions on
3150 delay slots dont break. */
3151 if (!(tb->pc & 1) && env->singlestep_enabled)
3152 break;
3153 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
3154 && (dc->pc < next_page_start));
3155
3156 npc = dc->pc;
3157 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3158 npc = dc->jmp_pc;
3159
3160 /* Force an update if the per-tb cpu state has changed. */
3161 if (dc->is_jmp == DISAS_NEXT
3162 && (dc->cpustate_changed || !dc->flagx_known
3163 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3164 dc->is_jmp = DISAS_UPDATE;
3165 tcg_gen_movi_tl(env_pc, npc);
3166 }
3167 /* Broken branch+delayslot sequence. */
3168 if (dc->delayed_branch == 1) {
3169 /* Set env->dslot to the size of the branch insn. */
3170 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3171 cris_store_direct_jmp(dc);
3172 }
3173
3174 cris_evaluate_flags (dc);
3175
3176 if (__builtin_expect(env->singlestep_enabled, 0)) {
3177 tcg_gen_movi_tl(env_pc, npc);
3178 t_gen_raise_exception(EXCP_DEBUG);
3179 } else {
3180 switch(dc->is_jmp) {
3181 case DISAS_NEXT:
3182 gen_goto_tb(dc, 1, npc);
3183 break;
3184 default:
3185 case DISAS_JUMP:
3186 case DISAS_UPDATE:
3187 /* indicate that the hash table must be used
3188 to find the next TB */
3189 tcg_gen_exit_tb(0);
3190 break;
3191 case DISAS_SWI:
3192 case DISAS_TB_JUMP:
3193 /* nothing more to generate */
3194 break;
3195 }
3196 }
3197 *gen_opc_ptr = INDEX_op_end;
3198 if (search_pc) {
3199 j = gen_opc_ptr - gen_opc_buf;
3200 lj++;
3201 while (lj <= j)
3202 gen_opc_instr_start[lj++] = 0;
3203 } else {
3204 tb->size = dc->pc - pc_start;
3205 }
3206
3207 #ifdef DEBUG_DISAS
3208 if (loglevel & CPU_LOG_TB_IN_ASM) {
3209 fprintf(logfile, "--------------\n");
3210 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3211 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3212 fprintf(logfile, "\nisize=%d osize=%d\n",
3213 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3214 }
3215 #endif
3216 return 0;
3217 }
3218
3219 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3220 {
3221 return gen_intermediate_code_internal(env, tb, 0);
3222 }
3223
3224 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3225 {
3226 return gen_intermediate_code_internal(env, tb, 1);
3227 }
3228
3229 void cpu_dump_state (CPUState *env, FILE *f,
3230 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3231 int flags)
3232 {
3233 int i;
3234 uint32_t srs;
3235
3236 if (!env || !f)
3237 return;
3238
3239 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3240 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3241 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3242 env->cc_op,
3243 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3244
3245
3246 for (i = 0; i < 16; i++) {
3247 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3248 if ((i + 1) % 4 == 0)
3249 cpu_fprintf(f, "\n");
3250 }
3251 cpu_fprintf(f, "\nspecial regs:\n");
3252 for (i = 0; i < 16; i++) {
3253 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3254 if ((i + 1) % 4 == 0)
3255 cpu_fprintf(f, "\n");
3256 }
3257 srs = env->pregs[PR_SRS];
3258 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3259 if (srs < 256) {
3260 for (i = 0; i < 16; i++) {
3261 cpu_fprintf(f, "s%2.2d=%8.8x ",
3262 i, env->sregs[srs][i]);
3263 if ((i + 1) % 4 == 0)
3264 cpu_fprintf(f, "\n");
3265 }
3266 }
3267 cpu_fprintf(f, "\n\n");
3268
3269 }
3270
3271 CPUCRISState *cpu_cris_init (const char *cpu_model)
3272 {
3273 CPUCRISState *env;
3274 int i;
3275
3276 env = qemu_mallocz(sizeof(CPUCRISState));
3277 if (!env)
3278 return NULL;
3279 cpu_exec_init(env);
3280
3281 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3282 #if TARGET_LONG_BITS > HOST_LONG_BITS
3283 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3284 TCG_AREG0, offsetof(CPUState, t0), "T0");
3285 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3286 TCG_AREG0, offsetof(CPUState, t1), "T1");
3287 #else
3288 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3289 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3290 #endif
3291
3292 cc_x = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3293 offsetof(CPUState, cc_x), "cc_x");
3294 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3295 offsetof(CPUState, cc_src), "cc_src");
3296 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3297 offsetof(CPUState, cc_dest),
3298 "cc_dest");
3299 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3300 offsetof(CPUState, cc_result),
3301 "cc_result");
3302 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3303 offsetof(CPUState, cc_op), "cc_op");
3304 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3305 offsetof(CPUState, cc_size),
3306 "cc_size");
3307 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3308 offsetof(CPUState, cc_mask),
3309 "cc_mask");
3310
3311 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3312 offsetof(CPUState, pc),
3313 "pc");
3314 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3315 offsetof(CPUState, btarget),
3316 "btarget");
3317 env_btaken = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3318 offsetof(CPUState, btaken),
3319 "btaken");
3320 for (i = 0; i < 16; i++) {
3321 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3322 offsetof(CPUState, regs[i]),
3323 regnames[i]);
3324 }
3325 for (i = 0; i < 16; i++) {
3326 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3327 offsetof(CPUState, pregs[i]),
3328 pregnames[i]);
3329 }
3330
3331 TCG_HELPER(helper_raise_exception);
3332 TCG_HELPER(helper_store);
3333 TCG_HELPER(helper_dump);
3334 TCG_HELPER(helper_dummy);
3335
3336 TCG_HELPER(helper_tlb_flush_pid);
3337 TCG_HELPER(helper_movl_sreg_reg);
3338 TCG_HELPER(helper_movl_reg_sreg);
3339 TCG_HELPER(helper_rfe);
3340
3341 TCG_HELPER(helper_evaluate_flags_muls);
3342 TCG_HELPER(helper_evaluate_flags_mulu);
3343 TCG_HELPER(helper_evaluate_flags_mcp);
3344 TCG_HELPER(helper_evaluate_flags_alu_4);
3345 TCG_HELPER(helper_evaluate_flags_move_4);
3346 TCG_HELPER(helper_evaluate_flags_move_2);
3347 TCG_HELPER(helper_evaluate_flags);
3348 TCG_HELPER(helper_top_evaluate_flags);
3349
3350 cpu_reset(env);
3351 return env;
3352 }
3353
3354 void cpu_reset (CPUCRISState *env)
3355 {
3356 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3357 tlb_flush(env, 1);
3358
3359 #if defined(CONFIG_USER_ONLY)
3360 /* start in user mode with interrupts enabled. */
3361 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3362 #else
3363 env->pregs[PR_CCS] = 0;
3364 #endif
3365 }
3366
3367 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3368 unsigned long searched_pc, int pc_pos, void *puc)
3369 {
3370 env->pc = gen_opc_pc[pc_pos];
3371 }
Patches shipped by Fedora