hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "nvram.h"
  29 #include "pc.h"
  30 #include "sysemu.h"
  31 #include "net.h"
  32 #include "isa.h"
  33 #include "pci.h"
  34 #include "boards.h"
  35
  36 #define MAX_IDE_BUS 2
  37
  38 /* temporary frame buffer OSI calls for the video.x driver. The right
  39    solution is to modify the driver to use VGA PCI I/Os */
  40 /* XXX: to be removed. This is no way related to emulation */
  41 static int vga_osi_call (CPUState *env)
  42 {
  43     static int vga_vbl_enabled;
  44     int linesize;
  45
  46     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  47
  48     /* same handler as PearPC, coming from the original MOL video
  49        driver. */
  50     switch(env->gpr[5]) {
  51     case 4:
  52         break;
  53     case 28: /* set_vmode */
  54         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  55             env->gpr[3] = 1;
  56         else
  57             env->gpr[3] = 0;
  58         break;
  59     case 29: /* get_vmode_info */
  60         if (env->gpr[6] != 0) {
  61             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  62                 env->gpr[3] = 1;
  63                 break;
  64             }
  65         }
  66         env->gpr[3] = 0;
  67         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  68         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  69         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  70         env->gpr[7] = 85 << 16; /* refresh rate */
  71         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  72         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  73         linesize = (linesize + 3) & ~3;
  74         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  75         break;
  76     case 31: /* set_video power */
  77         env->gpr[3] = 0;
  78         break;
  79     case 39: /* video_ctrl */
  80         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  81             vga_vbl_enabled = env->gpr[6];
  82         env->gpr[3] = 0;
  83         break;
  84     case 47:
  85         break;
  86     case 59: /* set_color */
  87         /* R6 = index, R7 = RGB */
  88         env->gpr[3] = 0;
  89         break;
  90     case 64: /* get color */
  91         /* R6 = index */
  92         env->gpr[3] = 0;
  93         break;
  94     case 116: /* set hwcursor */
  95         /* R6 = x, R7 = y, R8 = visible, R9 = data */
  96         break;
  97     default:
  98         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
  99                 ppc_dump_gpr(env, 5));
 100         break;
 101     }
 102
 103     return 1; /* osi_call handled */
 104 }
 105
 106 static void ppc_heathrow_init (int ram_size, int vga_ram_size,
 107                                const char *boot_device, DisplayState *ds,
 108                                const char *kernel_filename,
 109                                const char *kernel_cmdline,
 110                                const char *initrd_filename,
 111                                const char *cpu_model)
 112 {
 113     CPUState *env = NULL, *envs[MAX_CPUS];
 114     char buf[1024];
 115     qemu_irq *pic, **heathrow_irqs;
 116     nvram_t nvram;
 117     m48t59_t *m48t59;
 118     int linux_boot, i;
 119     unsigned long bios_offset, vga_bios_offset;
 120     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 121     PCIBus *pci_bus;
 122     MacIONVRAMState *nvr;
 123     int vga_bios_size, bios_size;
 124     qemu_irq *dummy_irq;
 125     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 126     int ide_mem_index[2];
 127     int ppc_boot_device;
 128     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 129     int index;
 130
 131     linux_boot = (kernel_filename != NULL);
 132
 133     /* init CPUs */
 134     if (cpu_model == NULL)
 135         cpu_model = "default";
 136     for (i = 0; i < smp_cpus; i++) {
 137         env = cpu_init(cpu_model);
 138         if (!env) {
 139             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 140             exit(1);
 141         }
 142         /* Set time-base frequency to 100 Mhz */
 143         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 144         env->osi_call = vga_osi_call;
 145         qemu_register_reset(&cpu_ppc_reset, env);
 146         register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 147         envs[i] = env;
 148     }
 149     if (env->nip < 0xFFF80000) {
 150         /* Special test for PowerPC 601:
 151          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 152          * But the NVRAM is located at 0xFFF04000...
 153          */
 154         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 155     }
 156
 157     /* allocate RAM */
 158     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 159
 160     /* allocate and load BIOS */
 161     bios_offset = ram_size + vga_ram_size;
 162     if (bios_name == NULL)
 163         bios_name = BIOS_FILENAME;
 164     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 165     bios_size = load_image(buf, phys_ram_base + bios_offset);
 166     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 167         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 168         exit(1);
 169     }
 170     bios_size = (bios_size + 0xfff) & ~0xfff;
 171     if (bios_size > 0x00080000) {
 172         /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
 173         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 174     }
 175     cpu_register_physical_memory((uint32_t)(-bios_size),
 176                                  bios_size, bios_offset | IO_MEM_ROM);
 177
 178     /* allocate and load VGA BIOS */
 179     vga_bios_offset = bios_offset + bios_size;
 180     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 181     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 182     if (vga_bios_size < 0) {
 183         /* if no bios is present, we can still work */
 184         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 185         vga_bios_size = 0;
 186     } else {
 187         /* set a specific header (XXX: find real Apple format for NDRV
 188            drivers) */
 189         phys_ram_base[vga_bios_offset] = 'N';
 190         phys_ram_base[vga_bios_offset + 1] = 'D';
 191         phys_ram_base[vga_bios_offset + 2] = 'R';
 192         phys_ram_base[vga_bios_offset + 3] = 'V';
 193         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 194                      vga_bios_size);
 195         vga_bios_size += 8;
 196     }
 197     vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
 198
 199     if (linux_boot) {
 200         kernel_base = KERNEL_LOAD_ADDR;
 201         /* now we can load the kernel */
 202         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 203         if (kernel_size < 0) {
 204             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 205                       kernel_filename);
 206             exit(1);
 207         }
 208         /* load initrd */
 209         if (initrd_filename) {
 210             initrd_base = INITRD_LOAD_ADDR;
 211             initrd_size = load_image(initrd_filename,
 212                                      phys_ram_base + initrd_base);
 213             if (initrd_size < 0) {
 214                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 215                           initrd_filename);
 216                 exit(1);
 217             }
 218         } else {
 219             initrd_base = 0;
 220             initrd_size = 0;
 221         }
 222         ppc_boot_device = 'm';
 223     } else {
 224         kernel_base = 0;
 225         kernel_size = 0;
 226         initrd_base = 0;
 227         initrd_size = 0;
 228         ppc_boot_device = '\0';
 229         for (i = 0; boot_device[i] != '\0'; i++) {
 230             /* TOFIX: for now, the second IDE channel is not properly
 231              *        used by OHW. The Mac floppy disk are not emulated.
 232              *        For now, OHW cannot boot from the network.
 233              */
 234 #if 0
 235             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 236                 ppc_boot_device = boot_device[i];
 237                 break;
 238             }
 239 #else
 240             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 241                 ppc_boot_device = boot_device[i];
 242                 break;
 243             }
 244 #endif
 245         }
 246         if (ppc_boot_device == '\0') {
 247             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 248             exit(1);
 249         }
 250     }
 251
 252     isa_mem_base = 0x80000000;
 253
 254     /* Register 2 MB of ISA IO space */
 255     isa_mmio_init(0xfe000000, 0x00200000);
 256
 257     /* XXX: we register only 1 output pin for heathrow PIC */
 258     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 259     heathrow_irqs[0] =
 260         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 261     /* Connect the heathrow PIC outputs to the 6xx bus */
 262     for (i = 0; i < smp_cpus; i++) {
 263         switch (PPC_INPUT(env)) {
 264         case PPC_FLAGS_INPUT_6xx:
 265             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 266             heathrow_irqs[i][0] =
 267                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 268             break;
 269         default:
 270             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 271             exit(1);
 272         }
 273     }
 274
 275     /* init basic PC hardware */
 276     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 277         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 278         exit(1);
 279     }
 280     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 281     pci_bus = pci_grackle_init(0xfec00000, pic);
 282     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
 283                  ram_size, vga_ram_size,
 284                  vga_bios_offset, vga_bios_size);
 285
 286     /* XXX: suppress that */
 287     dummy_irq = i8259_init(NULL);
 288
 289     /* XXX: use Mac Serial port */
 290     serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
 291
 292     for(i = 0; i < nb_nics; i++) {
 293         if (!nd_table[i].model)
 294             nd_table[i].model = "ne2k_pci";
 295         pci_nic_init(pci_bus, &nd_table[i], -1);
 296     }
 297
 298     /* First IDE channel is a CMD646 on the PCI bus */
 299
 300     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 301         fprintf(stderr, "qemu: too many IDE bus\n");
 302         exit(1);
 303     }
 304     index = drive_get_index(IF_IDE, 0, 0);
 305     if (index == -1)
 306         hd[0] = NULL;
 307     else
 308         hd[0] =  drives_table[index].bdrv;
 309     index = drive_get_index(IF_IDE, 0, 1);
 310     if (index == -1)
 311         hd[1] = NULL;
 312     else
 313         hd[1] =  drives_table[index].bdrv;
 314     hd[3] = hd[2] = NULL;
 315     pci_cmd646_ide_init(pci_bus, hd, 0);
 316
 317     /* Second IDE channel is a MAC IDE on the MacIO bus */
 318     index = drive_get_index(IF_IDE, 1, 0);
 319     if (index == -1)
 320         hd[0] = NULL;
 321     else
 322         hd[0] =  drives_table[index].bdrv;
 323     index = drive_get_index(IF_IDE, 1, 1);
 324     if (index == -1)
 325         hd[1] = NULL;
 326     else
 327         hd[1] =  drives_table[index].bdrv;
 328     ide_mem_index[0] = -1;
 329     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
 330
 331     /* cuda also initialize ADB */
 332     cuda_init(&cuda_mem_index, pic[0x12]);
 333
 334     adb_kbd_init(&adb_bus);
 335     adb_mouse_init(&adb_bus);
 336
 337     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 338     pmac_format_nvram_partition(nvr, 0x2000);
 339
 340     dbdma_init(&dbdma_mem_index);
 341
 342     macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
 343                cuda_mem_index, nvr, 2, ide_mem_index);
 344
 345     if (usb_enabled) {
 346         usb_ohci_init_pci(pci_bus, 3, -1);
 347     }
 348
 349     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 350         graphic_depth = 15;
 351
 352     m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 353     nvram.opaque = m48t59;
 354     nvram.read_fn = &m48t59_read;
 355     nvram.write_fn = &m48t59_write;
 356     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 357                          ppc_boot_device, kernel_base, kernel_size,
 358                          kernel_cmdline,
 359                          initrd_base, initrd_size,
 360                          /* XXX: need an option to load a NVRAM image */
 361                          0,
 362                          graphic_width, graphic_height, graphic_depth);
 363     /* No PCI init: the BIOS will do it */
 364
 365     /* Special port to get debug messages from Open-Firmware */
 366     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 367 }
 368
 369 QEMUMachine heathrow_machine = {
 370     "g3bw",
 371     "Heathrow based PowerMAC",
 372     ppc_heathrow_init,
 373 };