hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 /* PCI includes legacy ISA access.  */
   5 #include "isa.h"
   6 #include <linux/pci.h>
   7
   8 /* PCI bus */
   9
  10 extern target_phys_addr_t pci_mem_base;
  11
  12 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  13                                 uint32_t address, uint32_t data, int len);
  14 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  15                                    uint32_t address, int len);
  16 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  17                                 uint32_t addr, uint32_t size, int type);
  18
  19 #define PCI_ADDRESS_SPACE_MEM           0x00
  20 #define PCI_ADDRESS_SPACE_IO            0x01
  21 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  22
  23 typedef struct PCIIORegion {
  24     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  25     uint32_t size;
  26     uint8_t type;
  27     PCIMapIORegionFunc *map_func;
  28 } PCIIORegion;
  29
  30 #define PCI_ROM_SLOT 6
  31 #define PCI_NUM_REGIONS 7
  32
  33 #define PCI_DEVICES_MAX 64
  34
  35 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  36 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  37 #define PCI_COMMAND             0x04    /* 16 bits */
  38 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  39 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  40 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  41 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
  42 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
  43 #define PCI_MIN_GNT             0x3e    /* 8 bits */
  44 #define PCI_MAX_LAT             0x3f    /* 8 bits */
  45
  46 struct PCIDevice {
  47     /* PCI config space */
  48     uint8_t config[256];
  49
  50     /* the following fields are read only */
  51     PCIBus *bus;
  52     int devfn;
  53     char name[64];
  54     PCIIORegion io_regions[PCI_NUM_REGIONS];
  55
  56     /* do not access the following fields */
  57     PCIConfigReadFunc *config_read;
  58     PCIConfigWriteFunc *config_write;
  59     /* ??? This is a PC-specific hack, and should be removed.  */
  60     int irq_index;
  61
  62     /* IRQ objects for the INTA-INTD pins.  */
  63     qemu_irq *irq;
  64
  65     /* Current IRQ levels.  Used internally by the generic PCI code.  */
  66     int irq_state[4];
  67 };
  68
  69 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
  70                                int instance_size, int devfn,
  71                                PCIConfigReadFunc *config_read,
  72                                PCIConfigWriteFunc *config_write);
  73
  74 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
  75                             uint32_t size, int type,
  76                             PCIMapIORegionFunc *map_func);
  77
  78 uint32_t pci_default_read_config(PCIDevice *d,
  79                                  uint32_t address, int len);
  80 void pci_default_write_config(PCIDevice *d,
  81                               uint32_t address, uint32_t val, int len);
  82 void pci_device_save(PCIDevice *s, QEMUFile *f);
  83 int pci_device_load(PCIDevice *s, QEMUFile *f);
  84
  85 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
  86 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
  87 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  88                          qemu_irq *pic, int devfn_min, int nirq);
  89
  90 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
  91 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
  92 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
  93 int pci_bus_num(PCIBus *s);
  94 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
  95 PCIBus *pci_find_bus(int bus_num);
  96 PCIDevice *pci_find_device(int bus_num, int slot);
  97
  98 void pci_info(void);
  99 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 100                         pci_map_irq_fn map_irq, const char *name);
 101
 102 /* lsi53c895a.c */
 103 #define LSI_MAX_DEVS 7
 104 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 105 void *lsi_scsi_init(PCIBus *bus, int devfn);
 106
 107 /* vmware_vga.c */
 108 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 109                      unsigned long vga_ram_offset, int vga_ram_size);
 110
 111 /* usb-uhci.c */
 112 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 113 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 114
 115 /* usb-ohci.c */
 116 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 117
 118 /* eepro100.c */
 119
 120 PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 121 PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 122 PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 123
 124 /* ne2000.c */
 125
 126 PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 127
 128 /* rtl8139.c */
 129
 130 PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 131
 132 /* e1000.c */
 133 PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 134
 135 /* pcnet.c */
 136 PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 137
 138 /* prep_pci.c */
 139 PCIBus *pci_prep_init(qemu_irq *pic);
 140
 141 /* apb_pci.c */
 142 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
 143                      qemu_irq *pic);
 144
 145 #endif