hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "console.h"
  27 #include "net.h"
  28 #include "pc.h"
  29
  30 //#define DEBUG_PCI
  31
  32 struct PCIBus {
  33     int bus_num;
  34     int devfn_min;
  35     pci_set_irq_fn set_irq;
  36     pci_map_irq_fn map_irq;
  37     uint32_t config_reg; /* XXX: suppress */
  38     /* low level pic */
  39     SetIRQFunc *low_set_irq;
  40     qemu_irq *irq_opaque;
  41     PCIDevice *devices[256];
  42     PCIDevice *parent_dev;
  43     PCIBus *next;
  44     /* The bus IRQ state is the logical OR of the connected devices.
  45        Keep a count of the number of devices with raised IRQs.  */
  46     int nirq;
  47     int irq_count[];
  48 };
  49
  50 static void pci_update_mappings(PCIDevice *d);
  51 static void pci_set_irq(void *opaque, int irq_num, int level);
  52
  53 target_phys_addr_t pci_mem_base;
  54 static int pci_irq_index;
  55 static PCIBus *first_bus;
  56
  57 static void pcibus_save(QEMUFile *f, void *opaque)
  58 {
  59     PCIBus *bus = (PCIBus *)opaque;
  60     int i;
  61
  62     qemu_put_be32(f, bus->nirq);
  63     for (i = 0; i < bus->nirq; i++)
  64         qemu_put_be32(f, bus->irq_count[i]);
  65 }
  66
  67 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  68 {
  69     PCIBus *bus = (PCIBus *)opaque;
  70     int i, nirq;
  71
  72     if (version_id != 1)
  73         return -EINVAL;
  74
  75     nirq = qemu_get_be32(f);
  76     if (bus->nirq != nirq) {
  77         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  78                 nirq, bus->nirq);
  79         return -EINVAL;
  80     }
  81
  82     for (i = 0; i < nirq; i++)
  83         bus->irq_count[i] = qemu_get_be32(f);
  84
  85     return 0;
  86 }
  87
  88 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  89                          qemu_irq *pic, int devfn_min, int nirq)
  90 {
  91     PCIBus *bus;
  92     static int nbus = 0;
  93
  94     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  95     bus->set_irq = set_irq;
  96     bus->map_irq = map_irq;
  97     bus->irq_opaque = pic;
  98     bus->devfn_min = devfn_min;
  99     bus->nirq = nirq;
 100     first_bus = bus;
 101     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 102     return bus;
 103 }
 104
 105 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 106 {
 107     PCIBus *bus;
 108     bus = qemu_mallocz(sizeof(PCIBus));
 109     bus->map_irq = map_irq;
 110     bus->parent_dev = dev;
 111     bus->next = dev->bus->next;
 112     dev->bus->next = bus;
 113     return bus;
 114 }
 115
 116 int pci_bus_num(PCIBus *s)
 117 {
 118     return s->bus_num;
 119 }
 120
 121 void pci_device_save(PCIDevice *s, QEMUFile *f)
 122 {
 123     int i;
 124
 125     qemu_put_be32(f, 2); /* PCI device version */
 126     qemu_put_buffer(f, s->config, 256);
 127     for (i = 0; i < 4; i++)
 128         qemu_put_be32(f, s->irq_state[i]);
 129 }
 130
 131 int pci_device_load(PCIDevice *s, QEMUFile *f)
 132 {
 133     uint32_t version_id;
 134     int i;
 135
 136     version_id = qemu_get_be32(f);
 137     if (version_id > 2)
 138         return -EINVAL;
 139     qemu_get_buffer(f, s->config, 256);
 140     pci_update_mappings(s);
 141
 142     if (version_id >= 2)
 143         for (i = 0; i < 4; i ++)
 144             s->irq_state[i] = qemu_get_be32(f);
 145
 146     return 0;
 147 }
 148
 149 /* -1 for devfn means auto assign */
 150 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 151                                int instance_size, int devfn,
 152                                PCIConfigReadFunc *config_read,
 153                                PCIConfigWriteFunc *config_write)
 154 {
 155     PCIDevice *pci_dev;
 156
 157     if (pci_irq_index >= PCI_DEVICES_MAX)
 158         return NULL;
 159
 160     if (devfn < 0) {
 161         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 162             if (!bus->devices[devfn])
 163                 goto found;
 164         }
 165         return NULL;
 166     found: ;
 167     }
 168     pci_dev = qemu_mallocz(instance_size);
 169     if (!pci_dev)
 170         return NULL;
 171     pci_dev->bus = bus;
 172     pci_dev->devfn = devfn;
 173     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 174     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 175
 176     if (!config_read)
 177         config_read = pci_default_read_config;
 178     if (!config_write)
 179         config_write = pci_default_write_config;
 180     pci_dev->config_read = config_read;
 181     pci_dev->config_write = config_write;
 182     pci_dev->irq_index = pci_irq_index++;
 183     bus->devices[devfn] = pci_dev;
 184     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 185     return pci_dev;
 186 }
 187
 188 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 189                             uint32_t size, int type,
 190                             PCIMapIORegionFunc *map_func)
 191 {
 192     PCIIORegion *r;
 193     uint32_t addr;
 194
 195     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 196         return;
 197     r = &pci_dev->io_regions[region_num];
 198     r->addr = -1;
 199     r->size = size;
 200     r->type = type;
 201     r->map_func = map_func;
 202     if (region_num == PCI_ROM_SLOT) {
 203         addr = 0x30;
 204     } else {
 205         addr = 0x10 + region_num * 4;
 206     }
 207     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 208 }
 209
 210 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 211 {
 212     return addr + pci_mem_base;
 213 }
 214
 215 static void pci_update_mappings(PCIDevice *d)
 216 {
 217     PCIIORegion *r;
 218     int cmd, i;
 219     uint32_t last_addr, new_addr, config_ofs;
 220
 221     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 222     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 223         r = &d->io_regions[i];
 224         if (i == PCI_ROM_SLOT) {
 225             config_ofs = 0x30;
 226         } else {
 227             config_ofs = 0x10 + i * 4;
 228         }
 229         if (r->size != 0) {
 230             if (r->type & PCI_ADDRESS_SPACE_IO) {
 231                 if (cmd & PCI_COMMAND_IO) {
 232                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 233                                                          config_ofs));
 234                     new_addr = new_addr & ~(r->size - 1);
 235                     last_addr = new_addr + r->size - 1;
 236                     /* NOTE: we have only 64K ioports on PC */
 237                     if (last_addr <= new_addr || new_addr == 0 ||
 238                         last_addr >= 0x10000) {
 239                         new_addr = -1;
 240                     }
 241                 } else {
 242                     new_addr = -1;
 243                 }
 244             } else {
 245                 if (cmd & PCI_COMMAND_MEMORY) {
 246                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 247                                                          config_ofs));
 248                     /* the ROM slot has a specific enable bit */
 249                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 250                         goto no_mem_map;
 251                     new_addr = new_addr & ~(r->size - 1);
 252                     last_addr = new_addr + r->size - 1;
 253                     /* NOTE: we do not support wrapping */
 254                     /* XXX: as we cannot support really dynamic
 255                        mappings, we handle specific values as invalid
 256                        mappings. */
 257                     if (last_addr <= new_addr || new_addr == 0 ||
 258                         last_addr == -1) {
 259                         new_addr = -1;
 260                     }
 261                 } else {
 262                 no_mem_map:
 263                     new_addr = -1;
 264                 }
 265             }
 266             /* now do the real mapping */
 267             if (new_addr != r->addr) {
 268                 if (r->addr != -1) {
 269                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 270                         int class;
 271                         /* NOTE: specific hack for IDE in PC case:
 272                            only one byte must be mapped. */
 273                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 274                         if (class == 0x0101 && r->size == 4) {
 275                             isa_unassign_ioport(r->addr + 2, 1);
 276                         } else {
 277                             isa_unassign_ioport(r->addr, r->size);
 278                         }
 279                     } else {
 280                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 281                                                      r->size,
 282                                                      IO_MEM_UNASSIGNED);
 283                     }
 284                 }
 285                 r->addr = new_addr;
 286                 if (r->addr != -1) {
 287                     r->map_func(d, i, r->addr, r->size, r->type);
 288                 }
 289             }
 290         }
 291     }
 292 }
 293
 294 uint32_t pci_default_read_config(PCIDevice *d,
 295                                  uint32_t address, int len)
 296 {
 297     uint32_t val;
 298
 299     switch(len) {
 300     default:
 301     case 4:
 302         if (address <= 0xfc) {
 303             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 304             break;
 305         }
 306         /* fall through */
 307     case 2:
 308         if (address <= 0xfe) {
 309             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 310             break;
 311         }
 312         /* fall through */
 313     case 1:
 314         val = d->config[address];
 315         break;
 316     }
 317     return val;
 318 }
 319
 320 void pci_default_write_config(PCIDevice *d,
 321                               uint32_t address, uint32_t val, int len)
 322 {
 323     int can_write, i;
 324     uint32_t end, addr;
 325
 326     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 327                      (address >= 0x30 && address < 0x34))) {
 328         PCIIORegion *r;
 329         int reg;
 330
 331         if ( address >= 0x30 ) {
 332             reg = PCI_ROM_SLOT;
 333         }else{
 334             reg = (address - 0x10) >> 2;
 335         }
 336         r = &d->io_regions[reg];
 337         if (r->size == 0)
 338             goto default_config;
 339         /* compute the stored value */
 340         if (reg == PCI_ROM_SLOT) {
 341             /* keep ROM enable bit */
 342             val &= (~(r->size - 1)) | 1;
 343         } else {
 344             val &= ~(r->size - 1);
 345             val |= r->type;
 346         }
 347         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 348         pci_update_mappings(d);
 349         return;
 350     }
 351  default_config:
 352     /* not efficient, but simple */
 353     addr = address;
 354     for(i = 0; i < len; i++) {
 355         /* default read/write accesses */
 356         switch(d->config[0x0e]) {
 357         case 0x00:
 358         case 0x80:
 359             switch(addr) {
 360             case 0x00:
 361             case 0x01:
 362             case 0x02:
 363             case 0x03:
 364             case 0x08:
 365             case 0x09:
 366             case 0x0a:
 367             case 0x0b:
 368             case 0x0e:
 369             case 0x10 ... 0x27: /* base */
 370             case 0x30 ... 0x33: /* rom */
 371             case 0x3d:
 372                 can_write = 0;
 373                 break;
 374             default:
 375                 can_write = 1;
 376                 break;
 377             }
 378             break;
 379         default:
 380         case 0x01:
 381             switch(addr) {
 382             case 0x00:
 383             case 0x01:
 384             case 0x02:
 385             case 0x03:
 386             case 0x08:
 387             case 0x09:
 388             case 0x0a:
 389             case 0x0b:
 390             case 0x0e:
 391             case 0x38 ... 0x3b: /* rom */
 392             case 0x3d:
 393                 can_write = 0;
 394                 break;
 395             default:
 396                 can_write = 1;
 397                 break;
 398             }
 399             break;
 400         }
 401         if (can_write) {
 402             d->config[addr] = val;
 403         }
 404         if (++addr > 0xff)
 405                 break;
 406         val >>= 8;
 407     }
 408
 409     end = address + len;
 410     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 411         /* if the command register is modified, we must modify the mappings */
 412         pci_update_mappings(d);
 413     }
 414 }
 415
 416 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 417 {
 418     PCIBus *s = opaque;
 419     PCIDevice *pci_dev;
 420     int config_addr, bus_num;
 421
 422 #if defined(DEBUG_PCI) && 0
 423     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 424            addr, val, len);
 425 #endif
 426     bus_num = (addr >> 16) & 0xff;
 427     while (s && s->bus_num != bus_num)
 428         s = s->next;
 429     if (!s)
 430         return;
 431     pci_dev = s->devices[(addr >> 8) & 0xff];
 432     if (!pci_dev)
 433         return;
 434     config_addr = addr & 0xff;
 435 #if defined(DEBUG_PCI)
 436     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 437            pci_dev->name, config_addr, val, len);
 438 #endif
 439     pci_dev->config_write(pci_dev, config_addr, val, len);
 440 }
 441
 442 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 443 {
 444     PCIBus *s = opaque;
 445     PCIDevice *pci_dev;
 446     int config_addr, bus_num;
 447     uint32_t val;
 448
 449     bus_num = (addr >> 16) & 0xff;
 450     while (s && s->bus_num != bus_num)
 451         s= s->next;
 452     if (!s)
 453         goto fail;
 454     pci_dev = s->devices[(addr >> 8) & 0xff];
 455     if (!pci_dev) {
 456     fail:
 457         switch(len) {
 458         case 1:
 459             val = 0xff;
 460             break;
 461         case 2:
 462             val = 0xffff;
 463             break;
 464         default:
 465         case 4:
 466             val = 0xffffffff;
 467             break;
 468         }
 469         goto the_end;
 470     }
 471     config_addr = addr & 0xff;
 472     val = pci_dev->config_read(pci_dev, config_addr, len);
 473 #if defined(DEBUG_PCI)
 474     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 475            pci_dev->name, config_addr, val, len);
 476 #endif
 477  the_end:
 478 #if defined(DEBUG_PCI) && 0
 479     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 480            addr, val, len);
 481 #endif
 482     return val;
 483 }
 484
 485 /***********************************************************/
 486 /* generic PCI irq support */
 487
 488 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 489 static void pci_set_irq(void *opaque, int irq_num, int level)
 490 {
 491     PCIDevice *pci_dev = (PCIDevice *)opaque;
 492     PCIBus *bus;
 493     int change;
 494
 495     change = level - pci_dev->irq_state[irq_num];
 496     if (!change)
 497         return;
 498
 499     pci_dev->irq_state[irq_num] = level;
 500     for (;;) {
 501         bus = pci_dev->bus;
 502         irq_num = bus->map_irq(pci_dev, irq_num);
 503         if (bus->set_irq)
 504             break;
 505         pci_dev = bus->parent_dev;
 506     }
 507     bus->irq_count[irq_num] += change;
 508     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 509 }
 510
 511 /***********************************************************/
 512 /* monitor info on PCI */
 513
 514 typedef struct {
 515     uint16_t class;
 516     const char *desc;
 517 } pci_class_desc;
 518
 519 static pci_class_desc pci_class_descriptions[] =
 520 {
 521     { 0x0100, "SCSI controller"},
 522     { 0x0101, "IDE controller"},
 523     { 0x0102, "Floppy controller"},
 524     { 0x0103, "IPI controller"},
 525     { 0x0104, "RAID controller"},
 526     { 0x0106, "SATA controller"},
 527     { 0x0107, "SAS controller"},
 528     { 0x0180, "Storage controller"},
 529     { 0x0200, "Ethernet controller"},
 530     { 0x0201, "Token Ring controller"},
 531     { 0x0202, "FDDI controller"},
 532     { 0x0203, "ATM controller"},
 533     { 0x0280, "Network controller"},
 534     { 0x0300, "VGA controller"},
 535     { 0x0301, "XGA controller"},
 536     { 0x0302, "3D controller"},
 537     { 0x0380, "Display controller"},
 538     { 0x0400, "Video controller"},
 539     { 0x0401, "Audio controller"},
 540     { 0x0402, "Phone"},
 541     { 0x0480, "Multimedia controller"},
 542     { 0x0500, "RAM controller"},
 543     { 0x0501, "Flash controller"},
 544     { 0x0580, "Memory controller"},
 545     { 0x0600, "Host bridge"},
 546     { 0x0601, "ISA bridge"},
 547     { 0x0602, "EISA bridge"},
 548     { 0x0603, "MC bridge"},
 549     { 0x0604, "PCI bridge"},
 550     { 0x0605, "PCMCIA bridge"},
 551     { 0x0606, "NUBUS bridge"},
 552     { 0x0607, "CARDBUS bridge"},
 553     { 0x0608, "RACEWAY bridge"},
 554     { 0x0680, "Bridge"},
 555     { 0x0c03, "USB controller"},
 556     { 0, NULL}
 557 };
 558
 559 static void pci_info_device(PCIDevice *d)
 560 {
 561     int i, class;
 562     PCIIORegion *r;
 563     pci_class_desc *desc;
 564
 565     term_printf("  Bus %2d, device %3d, function %d:\n",
 566            d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 567     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 568     term_printf("    ");
 569     desc = pci_class_descriptions;
 570     while (desc->desc && class != desc->class)
 571         desc++;
 572     if (desc->desc) {
 573         term_printf("%s", desc->desc);
 574     } else {
 575         term_printf("Class %04x", class);
 576     }
 577     term_printf(": PCI device %04x:%04x\n",
 578            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 579            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 580
 581     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 582         term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 583     }
 584     if (class == 0x0604) {
 585         term_printf("      BUS %d.\n", d->config[0x19]);
 586     }
 587     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 588         r = &d->io_regions[i];
 589         if (r->size != 0) {
 590             term_printf("      BAR%d: ", i);
 591             if (r->type & PCI_ADDRESS_SPACE_IO) {
 592                 term_printf("I/O at 0x%04x [0x%04x].\n",
 593                        r->addr, r->addr + r->size - 1);
 594             } else {
 595                 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
 596                        r->addr, r->addr + r->size - 1);
 597             }
 598         }
 599     }
 600     if (class == 0x0604 && d->config[0x19] != 0) {
 601         pci_for_each_device(d->config[0x19], pci_info_device);
 602     }
 603 }
 604
 605 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 606 {
 607     PCIBus *bus = first_bus;
 608     PCIDevice *d;
 609     int devfn;
 610
 611     while (bus && bus->bus_num != bus_num)
 612         bus = bus->next;
 613     if (bus) {
 614         for(devfn = 0; devfn < 256; devfn++) {
 615             d = bus->devices[devfn];
 616             if (d)
 617                 fn(d);
 618         }
 619     }
 620 }
 621
 622 void pci_info(void)
 623 {
 624     pci_for_each_device(0, pci_info_device);
 625 }
 626
 627 /* Initialize a PCI NIC.  */
 628 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
 629 {
 630     PCIDevice *pci_dev;
 631
 632     if (strcmp(nd->model, "ne2k_pci") == 0) {
 633         pci_dev = pci_ne2000_init(bus, nd, devfn);
 634     } else if (strcmp(nd->model, "i82551") == 0) {
 635         pci_dev = pci_i82551_init(bus, nd, devfn);
 636     } else if (strcmp(nd->model, "i82557b") == 0) {
 637         pci_dev = pci_i82557b_init(bus, nd, devfn);
 638     } else if (strcmp(nd->model, "i82559er") == 0) {
 639         pci_dev = pci_i82559er_init(bus, nd, devfn);
 640     } else if (strcmp(nd->model, "rtl8139") == 0) {
 641         pci_dev = pci_rtl8139_init(bus, nd, devfn);
 642     } else if (strcmp(nd->model, "e1000") == 0) {
 643         pci_dev = pci_e1000_init(bus, nd, devfn);
 644     } else if (strcmp(nd->model, "pcnet") == 0) {
 645         pci_dev = pci_pcnet_init(bus, nd, devfn);
 646     } else if (strcmp(nd->model, "virtio") == 0) {
 647         pci_dev = virtio_net_init(bus, nd, devfn);
 648     } else if (strcmp(nd->model, "?") == 0) {
 649         fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
 650                         " ne2k_pci pcnet rtl8139 e1000 virtio\n");
 651         exit (1);
 652     } else {
 653         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 654         exit (1);
 655     }
 656     nd->devfn = pci_dev->devfn;
 657     return pci_dev;
 658 }
 659
 660 typedef struct {
 661     PCIDevice dev;
 662     PCIBus *bus;
 663 } PCIBridge;
 664
 665 static void pci_bridge_write_config(PCIDevice *d,
 666                              uint32_t address, uint32_t val, int len)
 667 {
 668     PCIBridge *s = (PCIBridge *)d;
 669
 670     if (address == 0x19 || (address == 0x18 && len > 1)) {
 671         if (address == 0x19)
 672             s->bus->bus_num = val & 0xff;
 673         else
 674             s->bus->bus_num = (val >> 8) & 0xff;
 675 #if defined(DEBUG_PCI)
 676         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 677 #endif
 678     }
 679     pci_default_write_config(d, address, val, len);
 680 }
 681
 682 PCIBus *pci_find_bus(int bus_num)
 683 {
 684     PCIBus *bus = first_bus;
 685
 686     while (bus && bus->bus_num != bus_num)
 687         bus = bus->next;
 688
 689     return bus;
 690 }
 691
 692 PCIDevice *pci_find_device(int bus_num, int slot)
 693 {
 694     int devfn;
 695     PCIDevice *d;
 696     PCIBus *bus = pci_find_bus(bus_num);
 697
 698     if (!bus)
 699         return NULL;
 700
 701     for(devfn = 0; devfn < 256; devfn++) {
 702         d = bus->devices[devfn];
 703             if (d && PCI_SLOT(devfn) == slot)
 704                 return d;
 705     }
 706     return NULL;
 707 }
 708
 709 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 710                         pci_map_irq_fn map_irq, const char *name)
 711 {
 712     PCIBridge *s;
 713     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 714                                          devfn, NULL, pci_bridge_write_config);
 715     s->dev.config[0x00] = id >> 16;
 716     s->dev.config[0x01] = id >> 24;
 717     s->dev.config[0x02] = id; // device_id
 718     s->dev.config[0x03] = id >> 8;
 719     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 720     s->dev.config[0x05] = 0x00;
 721     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 722     s->dev.config[0x07] = 0x00; // status = fast devsel
 723     s->dev.config[0x08] = 0x00; // revision
 724     s->dev.config[0x09] = 0x00; // programming i/f
 725     s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
 726     s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
 727     s->dev.config[0x0D] = 0x10; // latency_timer
 728     s->dev.config[0x0E] = 0x81; // header_type
 729     s->dev.config[0x1E] = 0xa0; // secondary status
 730
 731     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 732     return s->bus;
 733 }