dyngen.h

   1 /*
   2  * dyngen helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 int __op_param1, __op_param2, __op_param3;
  22 #ifdef __sparc__
  23   void __op_gen_label1(){}
  24   void __op_gen_label2(){}
  25   void __op_gen_label3(){}
  26 #else
  27   int __op_gen_label1, __op_gen_label2, __op_gen_label3;
  28 #endif
  29 int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
  30
  31 #ifdef __i386__
  32 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  33 {
  34 }
  35 #endif
  36
  37 #ifdef __x86_64__
  38 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  39 {
  40 }
  41 #endif
  42
  43 #ifdef __s390__
  44 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  45 {
  46 }
  47 #endif
  48
  49 #ifdef __ia64__
  50 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  51 {
  52     while (start < stop) {
  53         asm volatile ("fc %0" :: "r"(start));
  54         start += 32;
  55     }
  56     asm volatile (";;sync.i;;srlz.i;;");
  57 }
  58 #endif
  59
  60 #ifdef __powerpc__
  61
  62 #define MIN_CACHE_LINE_SIZE 8 /* conservative value */
  63
  64 static void inline flush_icache_range(unsigned long start, unsigned long stop)
  65 {
  66     unsigned long p;
  67
  68     start &= ~(MIN_CACHE_LINE_SIZE - 1);
  69     stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
  70
  71     for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
  72         asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
  73     }
  74     asm volatile ("sync" : : : "memory");
  75     for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
  76         asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
  77     }
  78     asm volatile ("sync" : : : "memory");
  79     asm volatile ("isync" : : : "memory");
  80 }
  81 #endif
  82
  83 #ifdef __alpha__
  84 static inline void flush_icache_range(unsigned long start, unsigned long stop)
  85 {
  86     asm ("imb");
  87 }
  88 #endif
  89
  90 #ifdef __sparc__
  91
  92 static void inline flush_icache_range(unsigned long start, unsigned long stop)
  93 {
  94         unsigned long p;
  95
  96         p = start & ~(8UL - 1UL);
  97         stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
  98
  99         for (; p < stop; p += 8)
 100                 __asm__ __volatile__("flush\t%0" : : "r" (p));
 101 }
 102
 103 #endif
 104
 105 #ifdef __arm__
 106 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 107 {
 108     register unsigned long _beg __asm ("a1") = start;
 109     register unsigned long _end __asm ("a2") = stop;
 110     register unsigned long _flg __asm ("a3") = 0;
 111     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 112 }
 113 #endif
 114
 115 #ifdef __mc68000
 116 #include <asm/cachectl.h>
 117 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 118 {
 119     cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
 120 }
 121 #endif
 122
 123 #ifdef __alpha__
 124
 125 register int gp asm("$29");
 126
 127 static inline void immediate_ldah(void *p, int val) {
 128     uint32_t *dest = p;
 129     long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff;
 130
 131     *dest &= ~0xffff;
 132     *dest |= high;
 133     *dest |= 31 << 16;
 134 }
 135 static inline void immediate_lda(void *dest, int val) {
 136     *(uint16_t *) dest = val;
 137 }
 138 void fix_bsr(void *p, int offset) {
 139     uint32_t *dest = p;
 140     *dest &= ~((1 << 21) - 1);
 141     *dest |= (offset >> 2) & ((1 << 21) - 1);
 142 }
 143
 144 #endif /* __alpha__ */
 145
 146 #ifdef __arm__
 147
 148 #define MAX_OP_SIZE    (128 * 4) /* in bytes */
 149 /* max size of the code that can be generated without calling arm_flush_ldr */
 150 #define MAX_FRAG_SIZE  (1024 * 4)
 151 //#define MAX_FRAG_SIZE  (135 * 4) /* for testing */
 152
 153 typedef struct LDREntry {
 154     uint8_t *ptr;
 155     uint32_t *data_ptr;
 156 } LDREntry;
 157
 158 static LDREntry arm_ldr_table[1024];
 159 static uint32_t arm_data_table[1024];
 160
 161 extern char exec_loop;
 162
 163 static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val)
 164 {
 165     *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff);
 166 }
 167
 168 static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
 169                               LDREntry *ldr_start, LDREntry *ldr_end,
 170                               uint32_t *data_start, uint32_t *data_end,
 171                               int gen_jmp)
 172 {
 173     LDREntry *le;
 174     uint32_t *ptr;
 175     int offset, data_size, target;
 176     uint8_t *data_ptr;
 177     uint32_t insn;
 178
 179     data_size = (uint8_t *)data_end - (uint8_t *)data_start;
 180
 181     if (gen_jmp) {
 182         /* generate branch to skip the data */
 183         if (data_size == 0)
 184             return gen_code_ptr;
 185         target = (long)gen_code_ptr + data_size + 4;
 186         arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
 187         gen_code_ptr += 4;
 188     }
 189
 190     /* copy the data */
 191     data_ptr = gen_code_ptr;
 192     memcpy(gen_code_ptr, data_start, data_size);
 193     gen_code_ptr += data_size;
 194
 195     /* patch the ldr to point to the data */
 196     for(le = ldr_start; le < ldr_end; le++) {
 197         ptr = (uint32_t *)le->ptr;
 198         offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +
 199             (unsigned long)data_ptr -
 200             (unsigned long)ptr - 8;
 201         insn = *ptr & ~(0xfff | 0x00800000);
 202         if (offset < 0) {
 203             offset = - offset;
 204         } else {
 205             insn |= 0x00800000;
 206         }
 207         if (offset > 0xfff) {
 208             fprintf(stderr, "Error ldr offset\n");
 209             abort();
 210         }
 211         insn |= offset;
 212         *ptr = insn;
 213     }
 214     return gen_code_ptr;
 215 }
 216
 217 #endif /* __arm__ */
 218
 219 #ifdef __ia64
 220
 221
 222 /* Patch instruction with "val" where "mask" has 1 bits. */
 223 static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
 224 {
 225     uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
 226 #   define insn_mask ((1UL << 41) - 1)
 227     unsigned long shift;
 228
 229     b0 = b[0]; b1 = b[1];
 230     shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */
 231     if (shift >= 64) {
 232         m1 = mask << (shift - 64);
 233         v1 = val << (shift - 64);
 234     } else {
 235         m0 = mask << shift; m1 = mask >> (64 - shift);
 236         v0 = val  << shift; v1 = val >> (64 - shift);
 237         b[0] = (b0 & ~m0) | (v0 & m0);
 238     }
 239     b[1] = (b1 & ~m1) | (v1 & m1);
 240 }
 241
 242 static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val)
 243 {
 244         ia64_patch(insn_addr,
 245                    0x011ffffe000UL,
 246                    (  ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
 247                     | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
 248         ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
 249 }
 250
 251 static inline void ia64_imm64 (void *insn, uint64_t val)
 252 {
 253     /* Ignore the slot number of the relocation; GCC and Intel
 254        toolchains differed for some time on whether IMM64 relocs are
 255        against slot 1 (Intel) or slot 2 (GCC).  */
 256     uint64_t insn_addr = (uint64_t) insn & ~3UL;
 257
 258     ia64_patch(insn_addr + 2,
 259                0x01fffefe000UL,
 260                (  ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
 261                 | ((val & 0x0000000000200000UL) <<  0) /* bit 21 -> 21 */
 262                 | ((val & 0x00000000001f0000UL) <<  6) /* bit 16 -> 22 */
 263                 | ((val & 0x000000000000ff80UL) << 20) /* bit  7 -> 27 */
 264                 | ((val & 0x000000000000007fUL) << 13) /* bit  0 -> 13 */)
 265             );
 266     ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
 267 }
 268
 269 static inline void ia64_imm60b (void *insn, uint64_t val)
 270 {
 271     /* Ignore the slot number of the relocation; GCC and Intel
 272        toolchains differed for some time on whether IMM64 relocs are
 273        against slot 1 (Intel) or slot 2 (GCC).  */
 274     uint64_t insn_addr = (uint64_t) insn & ~3UL;
 275
 276     if (val + ((uint64_t) 1 << 59) >= (1UL << 60))
 277         fprintf(stderr, "%s: value %ld out of IMM60 range\n",
 278                 __FUNCTION__, (int64_t) val);
 279     ia64_patch_imm60(insn_addr + 2, val);
 280 }
 281
 282 static inline void ia64_imm22 (void *insn, uint64_t val)
 283 {
 284     if (val + (1 << 21) >= (1 << 22))
 285         fprintf(stderr, "%s: value %li out of IMM22 range\n",
 286                 __FUNCTION__, (int64_t)val);
 287     ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
 288                (  ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
 289                 | ((val & 0x1f0000UL) <<  6) /* bit 16 -> 22 */
 290                 | ((val & 0x00ff80UL) << 20) /* bit  7 -> 27 */
 291                 | ((val & 0x00007fUL) << 13) /* bit  0 -> 13 */));
 292 }
 293
 294 /* Like ia64_imm22(), but also clear bits 20-21.  For addl, this has
 295    the effect of turning "addl rX=imm22,rY" into "addl
 296    rX=imm22,r0".  */
 297 static inline void ia64_imm22_r0 (void *insn, uint64_t val)
 298 {
 299     if (val + (1 << 21) >= (1 << 22))
 300         fprintf(stderr, "%s: value %li out of IMM22 range\n",
 301                 __FUNCTION__, (int64_t)val);
 302     ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20),
 303                (  ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
 304                 | ((val & 0x1f0000UL) <<  6) /* bit 16 -> 22 */
 305                 | ((val & 0x00ff80UL) << 20) /* bit  7 -> 27 */
 306                 | ((val & 0x00007fUL) << 13) /* bit  0 -> 13 */));
 307 }
 308
 309 static inline void ia64_imm21b (void *insn, uint64_t val)
 310 {
 311     if (val + (1 << 20) >= (1 << 21))
 312         fprintf(stderr, "%s: value %li out of IMM21b range\n",
 313                 __FUNCTION__, (int64_t)val);
 314     ia64_patch((uint64_t) insn, 0x11ffffe000UL,
 315                (  ((val & 0x100000UL) << 16) /* bit 20 -> 36 */
 316                 | ((val & 0x0fffffUL) << 13) /* bit  0 -> 13 */));
 317 }
 318
 319 static inline void ia64_nop_b (void *insn)
 320 {
 321     ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37);
 322 }
 323
 324 static inline void ia64_ldxmov(void *insn, uint64_t val)
 325 {
 326     if (val + (1 << 21) < (1 << 22))
 327         ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37);
 328 }
 329
 330 static inline int ia64_patch_ltoff(void *insn, uint64_t val,
 331                                    int relaxable)
 332 {
 333     if (relaxable && (val + (1 << 21) < (1 << 22))) {
 334         ia64_imm22_r0(insn, val);
 335         return 0;
 336     }
 337     return 1;
 338 }
 339
 340 struct ia64_fixup {
 341     struct ia64_fixup *next;
 342     void *addr;                 /* address that needs to be patched */
 343     long value;
 344 };
 345
 346 #define IA64_PLT(insn, plt_index)                       \
 347 do {                                                    \
 348     struct ia64_fixup *fixup = alloca(sizeof(*fixup));  \
 349     fixup->next = plt_fixes;                            \
 350     plt_fixes = fixup;                                  \
 351     fixup->addr = (insn);                               \
 352     fixup->value = (plt_index);                         \
 353     plt_offset[(plt_index)] = 1;                        \
 354 } while (0)
 355
 356 #define IA64_LTOFF(insn, val, relaxable)                        \
 357 do {                                                            \
 358     if (ia64_patch_ltoff(insn, val, relaxable)) {               \
 359         struct ia64_fixup *fixup = alloca(sizeof(*fixup));      \
 360         fixup->next = ltoff_fixes;                              \
 361         ltoff_fixes = fixup;                                    \
 362         fixup->addr = (insn);                                   \
 363         fixup->value = (val);                                   \
 364     }                                                           \
 365 } while (0)
 366
 367 static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
 368                                      struct ia64_fixup *ltoff_fixes,
 369                                      uint64_t gp,
 370                                      struct ia64_fixup *plt_fixes,
 371                                      int num_plts,
 372                                      unsigned long *plt_target,
 373                                      unsigned int *plt_offset)
 374 {
 375     static const uint8_t plt_bundle[] = {
 376         0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */
 377         0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60,
 378
 379         0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */
 380         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
 381     };
 382     uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start, *vp;
 383     struct ia64_fixup *fixup;
 384     unsigned int offset = 0;
 385     struct fdesc {
 386         long ip;
 387         long gp;
 388     } *fdesc;
 389     int i;
 390
 391     if (plt_fixes) {
 392         plt_start = gen_code_ptr;
 393
 394         for (i = 0; i < num_plts; ++i) {
 395             if (plt_offset[i]) {
 396                 plt_offset[i] = offset;
 397                 offset += sizeof(plt_bundle);
 398
 399                 fdesc = (struct fdesc *) plt_target[i];
 400                 memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
 401                 ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
 402                 ia64_imm60b(gen_code_ptr + 0x12,
 403                             (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4);
 404                 gen_code_ptr += sizeof(plt_bundle);
 405             }
 406         }
 407
 408         for (fixup = plt_fixes; fixup; fixup = fixup->next)
 409             ia64_imm21b(fixup->addr,
 410                         ((long) plt_start + plt_offset[fixup->value]
 411                          - ((long) fixup->addr & ~0xf)) >> 4);
 412     }
 413
 414     got_start = gen_code_ptr;
 415
 416     /* First, create the GOT: */
 417     for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
 418         /* first check if we already have this value in the GOT: */
 419         for (vp = got_start; vp < gen_code_ptr; ++vp)
 420             if (*(uint64_t *) vp == fixup->value)
 421                 break;
 422         if (vp == gen_code_ptr) {
 423             /* Nope, we need to put the value in the GOT: */
 424             *(uint64_t *) vp = fixup->value;
 425             gen_code_ptr += 8;
 426         }
 427         ia64_imm22(fixup->addr, (long) vp - gp);
 428     }
 429     /* Keep code ptr aligned. */
 430     if ((long) gen_code_ptr & 15)
 431         gen_code_ptr += 8;
 432     *gen_code_pp = gen_code_ptr;
 433 }
 434
 435 #endif