2 * QEMU Crystal CS4231 audio chip emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
32 #define CS_MAXADDR 0x3f
35 #define CS_MAXDREG (CS_DREGS - 1)
37 typedef struct CSState
{
38 uint32_t regs
[CS_REGS
];
39 uint8_t dregs
[CS_DREGS
];
43 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
45 #define CS_CDC_VER 0x8a
48 #define DPRINTF(fmt, args...) \
49 do { printf("CS: " fmt , ##args); } while (0)
50 #define pic_set_irq_new(intctl, irq, level) \
51 do { printf("CS: set_irq(%d): %d\n", (irq), (level)); \
52 pic_set_irq_new((intctl), (irq),(level));} while (0)
54 #define DPRINTF(fmt, args...)
57 static void cs_reset(void *opaque
)
61 memset(s
->regs
, 0, CS_REGS
* 4);
62 memset(s
->dregs
, 0, CS_DREGS
);
63 s
->dregs
[12] = CS_CDC_VER
;
64 s
->dregs
[25] = CS_VER
;
67 static uint32_t cs_mem_readl(void *opaque
, target_phys_addr_t addr
)
72 saddr
= (addr
& CS_MAXADDR
) >> 2;
80 ret
= s
->dregs
[CS_RAP(s
)];
83 DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s
), ret
);
87 DPRINTF("read reg[%d]: 0x%8.8x\n", saddr
, ret
);
93 static void cs_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
98 saddr
= (addr
& CS_MAXADDR
) >> 2;
99 DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr
, s
->regs
[saddr
], val
);
102 DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s
), s
->dregs
[CS_RAP(s
)], val
);
105 case 25: // Read only
109 val
|= CS_CDC_VER
; // Codec version
110 s
->dregs
[CS_RAP(s
)] = val
;
113 s
->dregs
[CS_RAP(s
)] = val
;
123 s
->regs
[saddr
] = val
;
126 s
->regs
[saddr
] = val
;
131 static CPUReadMemoryFunc
*cs_mem_read
[3] = {
137 static CPUWriteMemoryFunc
*cs_mem_write
[3] = {
143 static void cs_save(QEMUFile
*f
, void *opaque
)
148 for (i
= 0; i
< CS_REGS
; i
++)
149 qemu_put_be32s(f
, &s
->regs
[i
]);
151 qemu_put_buffer(f
, s
->dregs
, CS_DREGS
);
154 static int cs_load(QEMUFile
*f
, void *opaque
, int version_id
)
162 for (i
= 0; i
< CS_REGS
; i
++)
163 qemu_get_be32s(f
, &s
->regs
[i
]);
165 qemu_get_buffer(f
, s
->dregs
, CS_DREGS
);
169 void cs_init(target_phys_addr_t base
, int irq
, void *intctl
)
174 s
= qemu_mallocz(sizeof(CSState
));
178 cs_io_memory
= cpu_register_io_memory(0, cs_mem_read
, cs_mem_write
, s
);
179 cpu_register_physical_memory(base
, CS_MAXADDR
, cs_io_memory
);
180 register_savevm("cs4231", base
, 1, cs_save
, cs_load
, s
);
181 qemu_register_reset(cs_reset
, s
);
185 * QEMU Crystal CS4231 audio chip emulation
187 * Copyright (c) 2006 Fabrice Bellard
189 * Permission is hereby granted, free of charge, to any person obtaining a copy
190 * of this software and associated documentation files (the "Software"), to deal
191 * in the Software without restriction, including without limitation the rights
192 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
193 * copies of the Software, and to permit persons to whom the Software is
194 * furnished to do so, subject to the following conditions:
196 * The above copyright notice and this permission notice shall be included in
197 * all copies or substantial portions of the Software.
199 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
200 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
201 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
202 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
203 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
204 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
213 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
215 #define CS_MAXADDR 0x3f
218 #define CS_MAXDREG (CS_DREGS - 1)
220 typedef struct CSState
{
221 uint32_t regs
[CS_REGS
];
222 uint8_t dregs
[CS_DREGS
];
226 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
228 #define CS_CDC_VER 0x8a
231 #define DPRINTF(fmt, args...) \
232 do { printf("CS: " fmt , ##args); } while (0)
233 #define pic_set_irq_new(intctl, irq, level) \
234 do { printf("CS: set_irq(%d): %d\n", (irq), (level)); \
235 pic_set_irq_new((intctl), (irq),(level));} while (0)
237 #define DPRINTF(fmt, args...)
240 static void cs_reset(void *opaque
)
244 memset(s
->regs
, 0, CS_REGS
* 4);
245 memset(s
->dregs
, 0, CS_DREGS
);
246 s
->dregs
[12] = CS_CDC_VER
;
247 s
->dregs
[25] = CS_VER
;
250 static uint32_t cs_mem_readl(void *opaque
, target_phys_addr_t addr
)
255 saddr
= (addr
& CS_MAXADDR
) >> 2;
259 case 3: // Write only
263 ret
= s
->dregs
[CS_RAP(s
)];
266 DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s
), ret
);
269 ret
= s
->regs
[saddr
];
270 DPRINTF("read reg[%d]: 0x%8.8x\n", saddr
, ret
);
276 static void cs_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
281 saddr
= (addr
& CS_MAXADDR
) >> 2;
282 DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr
, s
->regs
[saddr
], val
);
285 DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s
), s
->dregs
[CS_RAP(s
)], val
);
288 case 25: // Read only
292 val
|= CS_CDC_VER
; // Codec version
293 s
->dregs
[CS_RAP(s
)] = val
;
296 s
->dregs
[CS_RAP(s
)] = val
;
306 s
->regs
[saddr
] = val
;
309 s
->regs
[saddr
] = val
;
314 static CPUReadMemoryFunc
*cs_mem_read
[3] = {
320 static CPUWriteMemoryFunc
*cs_mem_write
[3] = {
326 static void cs_save(QEMUFile
*f
, void *opaque
)
331 for (i
= 0; i
< CS_REGS
; i
++)
332 qemu_put_be32s(f
, &s
->regs
[i
]);
334 qemu_put_buffer(f
, s
->dregs
, CS_DREGS
);
337 static int cs_load(QEMUFile
*f
, void *opaque
, int version_id
)
345 for (i
= 0; i
< CS_REGS
; i
++)
346 qemu_get_be32s(f
, &s
->regs
[i
]);
348 qemu_get_buffer(f
, s
->dregs
, CS_DREGS
);
352 void cs_init(target_phys_addr_t base
, int irq
, void *intctl
)
357 s
= qemu_mallocz(sizeof(CSState
));
361 cs_io_memory
= cpu_register_io_memory(0, cs_mem_read
, cs_mem_write
, s
);
362 cpu_register_physical_memory(base
, CS_MAXADDR
, cs_io_memory
);
363 register_savevm("cs4231", base
, 1, cs_save
, cs_load
, s
);
364 qemu_register_reset(cs_reset
, s
);