cpu-all.h

   1 /*
   2  * defines common to all virtual CPUs
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ALL_H
  21 #define CPU_ALL_H
  22
  23 #if defined(__arm__) || defined(__sparc__) || defined(__mips__)
  24 #define WORDS_ALIGNED
  25 #endif
  26
  27 /* some important defines:
  28  *
  29  * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
  30  * memory accesses.
  31  *
  32  * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
  33  * otherwise little endian.
  34  *
  35  * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
  36  *
  37  * TARGET_WORDS_BIGENDIAN : same for target cpu
  38  */
  39
  40 #include "bswap.h"
  41
  42 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
  43 #define BSWAP_NEEDED
  44 #endif
  45
  46 #ifdef BSWAP_NEEDED
  47
  48 static inline uint16_t tswap16(uint16_t s)
  49 {
  50     return bswap16(s);
  51 }
  52
  53 static inline uint32_t tswap32(uint32_t s)
  54 {
  55     return bswap32(s);
  56 }
  57
  58 static inline uint64_t tswap64(uint64_t s)
  59 {
  60     return bswap64(s);
  61 }
  62
  63 static inline void tswap16s(uint16_t *s)
  64 {
  65     *s = bswap16(*s);
  66 }
  67
  68 static inline void tswap32s(uint32_t *s)
  69 {
  70     *s = bswap32(*s);
  71 }
  72
  73 static inline void tswap64s(uint64_t *s)
  74 {
  75     *s = bswap64(*s);
  76 }
  77
  78 #else
  79
  80 static inline uint16_t tswap16(uint16_t s)
  81 {
  82     return s;
  83 }
  84
  85 static inline uint32_t tswap32(uint32_t s)
  86 {
  87     return s;
  88 }
  89
  90 static inline uint64_t tswap64(uint64_t s)
  91 {
  92     return s;
  93 }
  94
  95 static inline void tswap16s(uint16_t *s)
  96 {
  97 }
  98
  99 static inline void tswap32s(uint32_t *s)
 100 {
 101 }
 102
 103 static inline void tswap64s(uint64_t *s)
 104 {
 105 }
 106
 107 #endif
 108
 109 #if TARGET_LONG_SIZE == 4
 110 #define tswapl(s) tswap32(s)
 111 #define tswapls(s) tswap32s((uint32_t *)(s))
 112 #define bswaptls(s) bswap32s(s)
 113 #else
 114 #define tswapl(s) tswap64(s)
 115 #define tswapls(s) tswap64s((uint64_t *)(s))
 116 #define bswaptls(s) bswap64s(s)
 117 #endif
 118
 119 typedef union {
 120     float32 f;
 121     uint32_t l;
 122 } CPU_FloatU;
 123
 124 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
 125    endian ! */
 126 typedef union {
 127     float64 d;
 128 #if defined(WORDS_BIGENDIAN) \
 129     || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
 130     struct {
 131         uint32_t upper;
 132         uint32_t lower;
 133     } l;
 134 #else
 135     struct {
 136         uint32_t lower;
 137         uint32_t upper;
 138     } l;
 139 #endif
 140     uint64_t ll;
 141 } CPU_DoubleU;
 142
 143 #ifdef TARGET_SPARC
 144 typedef union {
 145     float128 q;
 146 #if defined(WORDS_BIGENDIAN) \
 147     || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
 148     struct {
 149         uint32_t upmost;
 150         uint32_t upper;
 151         uint32_t lower;
 152         uint32_t lowest;
 153     } l;
 154     struct {
 155         uint64_t upper;
 156         uint64_t lower;
 157     } ll;
 158 #else
 159     struct {
 160         uint32_t lowest;
 161         uint32_t lower;
 162         uint32_t upper;
 163         uint32_t upmost;
 164     } l;
 165     struct {
 166         uint64_t lower;
 167         uint64_t upper;
 168     } ll;
 169 #endif
 170 } CPU_QuadU;
 171 #endif
 172
 173 /* CPU memory access without any memory or io remapping */
 174
 175 /*
 176  * the generic syntax for the memory accesses is:
 177  *
 178  * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 179  *
 180  * store: st{type}{size}{endian}_{access_type}(ptr, val)
 181  *
 182  * type is:
 183  * (empty): integer access
 184  *   f    : float access
 185  *
 186  * sign is:
 187  * (empty): for floats or 32 bit size
 188  *   u    : unsigned
 189  *   s    : signed
 190  *
 191  * size is:
 192  *   b: 8 bits
 193  *   w: 16 bits
 194  *   l: 32 bits
 195  *   q: 64 bits
 196  *
 197  * endian is:
 198  * (empty): target cpu endianness or 8 bit access
 199  *   r    : reversed target cpu endianness (not implemented yet)
 200  *   be   : big endian (not implemented yet)
 201  *   le   : little endian (not implemented yet)
 202  *
 203  * access_type is:
 204  *   raw    : host memory access
 205  *   user   : user mode access using soft MMU
 206  *   kernel : kernel mode access using soft MMU
 207  */
 208 static inline int ldub_p(void *ptr)
 209 {
 210     return *(uint8_t *)ptr;
 211 }
 212
 213 static inline int ldsb_p(void *ptr)
 214 {
 215     return *(int8_t *)ptr;
 216 }
 217
 218 static inline void stb_p(void *ptr, int v)
 219 {
 220     *(uint8_t *)ptr = v;
 221 }
 222
 223 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
 224    kernel handles unaligned load/stores may give better results, but
 225    it is a system wide setting : bad */
 226 #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
 227
 228 /* conservative code for little endian unaligned accesses */
 229 static inline int lduw_le_p(void *ptr)
 230 {
 231 #ifdef __powerpc__
 232     int val;
 233     __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 234     return val;
 235 #else
 236     uint8_t *p = ptr;
 237     return p[0] | (p[1] << 8);
 238 #endif
 239 }
 240
 241 static inline int ldsw_le_p(void *ptr)
 242 {
 243 #ifdef __powerpc__
 244     int val;
 245     __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 246     return (int16_t)val;
 247 #else
 248     uint8_t *p = ptr;
 249     return (int16_t)(p[0] | (p[1] << 8));
 250 #endif
 251 }
 252
 253 static inline int ldl_le_p(void *ptr)
 254 {
 255 #ifdef __powerpc__
 256     int val;
 257     __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 258     return val;
 259 #else
 260     uint8_t *p = ptr;
 261     return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
 262 #endif
 263 }
 264
 265 static inline uint64_t ldq_le_p(void *ptr)
 266 {
 267     uint8_t *p = ptr;
 268     uint32_t v1, v2;
 269     v1 = ldl_le_p(p);
 270     v2 = ldl_le_p(p + 4);
 271     return v1 | ((uint64_t)v2 << 32);
 272 }
 273
 274 static inline void stw_le_p(void *ptr, int v)
 275 {
 276 #ifdef __powerpc__
 277     __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
 278 #else
 279     uint8_t *p = ptr;
 280     p[0] = v;
 281     p[1] = v >> 8;
 282 #endif
 283 }
 284
 285 static inline void stl_le_p(void *ptr, int v)
 286 {
 287 #ifdef __powerpc__
 288     __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
 289 #else
 290     uint8_t *p = ptr;
 291     p[0] = v;
 292     p[1] = v >> 8;
 293     p[2] = v >> 16;
 294     p[3] = v >> 24;
 295 #endif
 296 }
 297
 298 static inline void stq_le_p(void *ptr, uint64_t v)
 299 {
 300     uint8_t *p = ptr;
 301     stl_le_p(p, (uint32_t)v);
 302     stl_le_p(p + 4, v >> 32);
 303 }
 304
 305 /* float access */
 306
 307 static inline float32 ldfl_le_p(void *ptr)
 308 {
 309     union {
 310         float32 f;
 311         uint32_t i;
 312     } u;
 313     u.i = ldl_le_p(ptr);
 314     return u.f;
 315 }
 316
 317 static inline void stfl_le_p(void *ptr, float32 v)
 318 {
 319     union {
 320         float32 f;
 321         uint32_t i;
 322     } u;
 323     u.f = v;
 324     stl_le_p(ptr, u.i);
 325 }
 326
 327 static inline float64 ldfq_le_p(void *ptr)
 328 {
 329     CPU_DoubleU u;
 330     u.l.lower = ldl_le_p(ptr);
 331     u.l.upper = ldl_le_p(ptr + 4);
 332     return u.d;
 333 }
 334
 335 static inline void stfq_le_p(void *ptr, float64 v)
 336 {
 337     CPU_DoubleU u;
 338     u.d = v;
 339     stl_le_p(ptr, u.l.lower);
 340     stl_le_p(ptr + 4, u.l.upper);
 341 }
 342
 343 #else
 344
 345 static inline int lduw_le_p(void *ptr)
 346 {
 347     return *(uint16_t *)ptr;
 348 }
 349
 350 static inline int ldsw_le_p(void *ptr)
 351 {
 352     return *(int16_t *)ptr;
 353 }
 354
 355 static inline int ldl_le_p(void *ptr)
 356 {
 357     return *(uint32_t *)ptr;
 358 }
 359
 360 static inline uint64_t ldq_le_p(void *ptr)
 361 {
 362     return *(uint64_t *)ptr;
 363 }
 364
 365 static inline void stw_le_p(void *ptr, int v)
 366 {
 367     *(uint16_t *)ptr = v;
 368 }
 369
 370 static inline void stl_le_p(void *ptr, int v)
 371 {
 372     *(uint32_t *)ptr = v;
 373 }
 374
 375 static inline void stq_le_p(void *ptr, uint64_t v)
 376 {
 377     *(uint64_t *)ptr = v;
 378 }
 379
 380 /* float access */
 381
 382 static inline float32 ldfl_le_p(void *ptr)
 383 {
 384     return *(float32 *)ptr;
 385 }
 386
 387 static inline float64 ldfq_le_p(void *ptr)
 388 {
 389     return *(float64 *)ptr;
 390 }
 391
 392 static inline void stfl_le_p(void *ptr, float32 v)
 393 {
 394     *(float32 *)ptr = v;
 395 }
 396
 397 static inline void stfq_le_p(void *ptr, float64 v)
 398 {
 399     *(float64 *)ptr = v;
 400 }
 401 #endif
 402
 403 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
 404
 405 static inline int lduw_be_p(void *ptr)
 406 {
 407 #if defined(__i386__)
 408     int val;
 409     asm volatile ("movzwl %1, %0\n"
 410                   "xchgb %b0, %h0\n"
 411                   : "=q" (val)
 412                   : "m" (*(uint16_t *)ptr));
 413     return val;
 414 #else
 415     uint8_t *b = (uint8_t *) ptr;
 416     return ((b[0] << 8) | b[1]);
 417 #endif
 418 }
 419
 420 static inline int ldsw_be_p(void *ptr)
 421 {
 422 #if defined(__i386__)
 423     int val;
 424     asm volatile ("movzwl %1, %0\n"
 425                   "xchgb %b0, %h0\n"
 426                   : "=q" (val)
 427                   : "m" (*(uint16_t *)ptr));
 428     return (int16_t)val;
 429 #else
 430     uint8_t *b = (uint8_t *) ptr;
 431     return (int16_t)((b[0] << 8) | b[1]);
 432 #endif
 433 }
 434
 435 static inline int ldl_be_p(void *ptr)
 436 {
 437 #if defined(__i386__) || defined(__x86_64__)
 438     int val;
 439     asm volatile ("movl %1, %0\n"
 440                   "bswap %0\n"
 441                   : "=r" (val)
 442                   : "m" (*(uint32_t *)ptr));
 443     return val;
 444 #else
 445     uint8_t *b = (uint8_t *) ptr;
 446     return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
 447 #endif
 448 }
 449
 450 static inline uint64_t ldq_be_p(void *ptr)
 451 {
 452     uint32_t a,b;
 453     a = ldl_be_p(ptr);
 454     b = ldl_be_p(ptr+4);
 455     return (((uint64_t)a<<32)|b);
 456 }
 457
 458 static inline void stw_be_p(void *ptr, int v)
 459 {
 460 #if defined(__i386__)
 461     asm volatile ("xchgb %b0, %h0\n"
 462                   "movw %w0, %1\n"
 463                   : "=q" (v)
 464                   : "m" (*(uint16_t *)ptr), "0" (v));
 465 #else
 466     uint8_t *d = (uint8_t *) ptr;
 467     d[0] = v >> 8;
 468     d[1] = v;
 469 #endif
 470 }
 471
 472 static inline void stl_be_p(void *ptr, int v)
 473 {
 474 #if defined(__i386__) || defined(__x86_64__)
 475     asm volatile ("bswap %0\n"
 476                   "movl %0, %1\n"
 477                   : "=r" (v)
 478                   : "m" (*(uint32_t *)ptr), "0" (v));
 479 #else
 480     uint8_t *d = (uint8_t *) ptr;
 481     d[0] = v >> 24;
 482     d[1] = v >> 16;
 483     d[2] = v >> 8;
 484     d[3] = v;
 485 #endif
 486 }
 487
 488 static inline void stq_be_p(void *ptr, uint64_t v)
 489 {
 490     stl_be_p(ptr, v >> 32);
 491     stl_be_p(ptr + 4, v);
 492 }
 493
 494 /* float access */
 495
 496 static inline float32 ldfl_be_p(void *ptr)
 497 {
 498     union {
 499         float32 f;
 500         uint32_t i;
 501     } u;
 502     u.i = ldl_be_p(ptr);
 503     return u.f;
 504 }
 505
 506 static inline void stfl_be_p(void *ptr, float32 v)
 507 {
 508     union {
 509         float32 f;
 510         uint32_t i;
 511     } u;
 512     u.f = v;
 513     stl_be_p(ptr, u.i);
 514 }
 515
 516 static inline float64 ldfq_be_p(void *ptr)
 517 {
 518     CPU_DoubleU u;
 519     u.l.upper = ldl_be_p(ptr);
 520     u.l.lower = ldl_be_p(ptr + 4);
 521     return u.d;
 522 }
 523
 524 static inline void stfq_be_p(void *ptr, float64 v)
 525 {
 526     CPU_DoubleU u;
 527     u.d = v;
 528     stl_be_p(ptr, u.l.upper);
 529     stl_be_p(ptr + 4, u.l.lower);
 530 }
 531
 532 #else
 533
 534 static inline int lduw_be_p(void *ptr)
 535 {
 536     return *(uint16_t *)ptr;
 537 }
 538
 539 static inline int ldsw_be_p(void *ptr)
 540 {
 541     return *(int16_t *)ptr;
 542 }
 543
 544 static inline int ldl_be_p(void *ptr)
 545 {
 546     return *(uint32_t *)ptr;
 547 }
 548
 549 static inline uint64_t ldq_be_p(void *ptr)
 550 {
 551     return *(uint64_t *)ptr;
 552 }
 553
 554 static inline void stw_be_p(void *ptr, int v)
 555 {
 556     *(uint16_t *)ptr = v;
 557 }
 558
 559 static inline void stl_be_p(void *ptr, int v)
 560 {
 561     *(uint32_t *)ptr = v;
 562 }
 563
 564 static inline void stq_be_p(void *ptr, uint64_t v)
 565 {
 566     *(uint64_t *)ptr = v;
 567 }
 568
 569 /* float access */
 570
 571 static inline float32 ldfl_be_p(void *ptr)
 572 {
 573     return *(float32 *)ptr;
 574 }
 575
 576 static inline float64 ldfq_be_p(void *ptr)
 577 {
 578     return *(float64 *)ptr;
 579 }
 580
 581 static inline void stfl_be_p(void *ptr, float32 v)
 582 {
 583     *(float32 *)ptr = v;
 584 }
 585
 586 static inline void stfq_be_p(void *ptr, float64 v)
 587 {
 588     *(float64 *)ptr = v;
 589 }
 590
 591 #endif
 592
 593 /* target CPU memory access functions */
 594 #if defined(TARGET_WORDS_BIGENDIAN)
 595 #define lduw_p(p) lduw_be_p(p)
 596 #define ldsw_p(p) ldsw_be_p(p)
 597 #define ldl_p(p) ldl_be_p(p)
 598 #define ldq_p(p) ldq_be_p(p)
 599 #define ldfl_p(p) ldfl_be_p(p)
 600 #define ldfq_p(p) ldfq_be_p(p)
 601 #define stw_p(p, v) stw_be_p(p, v)
 602 #define stl_p(p, v) stl_be_p(p, v)
 603 #define stq_p(p, v) stq_be_p(p, v)
 604 #define stfl_p(p, v) stfl_be_p(p, v)
 605 #define stfq_p(p, v) stfq_be_p(p, v)
 606 #else
 607 #define lduw_p(p) lduw_le_p(p)
 608 #define ldsw_p(p) ldsw_le_p(p)
 609 #define ldl_p(p) ldl_le_p(p)
 610 #define ldq_p(p) ldq_le_p(p)
 611 #define ldfl_p(p) ldfl_le_p(p)
 612 #define ldfq_p(p) ldfq_le_p(p)
 613 #define stw_p(p, v) stw_le_p(p, v)
 614 #define stl_p(p, v) stl_le_p(p, v)
 615 #define stq_p(p, v) stq_le_p(p, v)
 616 #define stfl_p(p, v) stfl_le_p(p, v)
 617 #define stfq_p(p, v) stfq_le_p(p, v)
 618 #endif
 619
 620 /* MMU memory access macros */
 621
 622 #if defined(CONFIG_USER_ONLY)
 623 /* On some host systems the guest address space is reserved on the host.
 624  * This allows the guest address space to be offset to a convenient location.
 625  */
 626 //#define GUEST_BASE 0x20000000
 627 #define GUEST_BASE 0
 628
 629 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
 630 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
 631 #define h2g(x) ((target_ulong)(x - GUEST_BASE))
 632
 633 #define saddr(x) g2h(x)
 634 #define laddr(x) g2h(x)
 635
 636 #else /* !CONFIG_USER_ONLY */
 637 /* NOTE: we use double casts if pointers and target_ulong have
 638    different sizes */
 639 #define saddr(x) (uint8_t *)(long)(x)
 640 #define laddr(x) (uint8_t *)(long)(x)
 641 #endif
 642
 643 #define ldub_raw(p) ldub_p(laddr((p)))
 644 #define ldsb_raw(p) ldsb_p(laddr((p)))
 645 #define lduw_raw(p) lduw_p(laddr((p)))
 646 #define ldsw_raw(p) ldsw_p(laddr((p)))
 647 #define ldl_raw(p) ldl_p(laddr((p)))
 648 #define ldq_raw(p) ldq_p(laddr((p)))
 649 #define ldfl_raw(p) ldfl_p(laddr((p)))
 650 #define ldfq_raw(p) ldfq_p(laddr((p)))
 651 #define stb_raw(p, v) stb_p(saddr((p)), v)
 652 #define stw_raw(p, v) stw_p(saddr((p)), v)
 653 #define stl_raw(p, v) stl_p(saddr((p)), v)
 654 #define stq_raw(p, v) stq_p(saddr((p)), v)
 655 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
 656 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
 657
 658
 659 #if defined(CONFIG_USER_ONLY)
 660
 661 /* if user mode, no other memory access functions */
 662 #define ldub(p) ldub_raw(p)
 663 #define ldsb(p) ldsb_raw(p)
 664 #define lduw(p) lduw_raw(p)
 665 #define ldsw(p) ldsw_raw(p)
 666 #define ldl(p) ldl_raw(p)
 667 #define ldq(p) ldq_raw(p)
 668 #define ldfl(p) ldfl_raw(p)
 669 #define ldfq(p) ldfq_raw(p)
 670 #define stb(p, v) stb_raw(p, v)
 671 #define stw(p, v) stw_raw(p, v)
 672 #define stl(p, v) stl_raw(p, v)
 673 #define stq(p, v) stq_raw(p, v)
 674 #define stfl(p, v) stfl_raw(p, v)
 675 #define stfq(p, v) stfq_raw(p, v)
 676
 677 #define ldub_code(p) ldub_raw(p)
 678 #define ldsb_code(p) ldsb_raw(p)
 679 #define lduw_code(p) lduw_raw(p)
 680 #define ldsw_code(p) ldsw_raw(p)
 681 #define ldl_code(p) ldl_raw(p)
 682 #define ldq_code(p) ldq_raw(p)
 683
 684 #define ldub_kernel(p) ldub_raw(p)
 685 #define ldsb_kernel(p) ldsb_raw(p)
 686 #define lduw_kernel(p) lduw_raw(p)
 687 #define ldsw_kernel(p) ldsw_raw(p)
 688 #define ldl_kernel(p) ldl_raw(p)
 689 #define ldq_kernel(p) ldq_raw(p)
 690 #define ldfl_kernel(p) ldfl_raw(p)
 691 #define ldfq_kernel(p) ldfq_raw(p)
 692 #define stb_kernel(p, v) stb_raw(p, v)
 693 #define stw_kernel(p, v) stw_raw(p, v)
 694 #define stl_kernel(p, v) stl_raw(p, v)
 695 #define stq_kernel(p, v) stq_raw(p, v)
 696 #define stfl_kernel(p, v) stfl_raw(p, v)
 697 #define stfq_kernel(p, vt) stfq_raw(p, v)
 698
 699 #endif /* defined(CONFIG_USER_ONLY) */
 700
 701 /* page related stuff */
 702
 703 #define TARGET_PAGE_SIZE (1ul << TARGET_PAGE_BITS)
 704 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
 705 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
 706
 707 /* ??? These should be the larger of unsigned long and target_ulong.  */
 708 extern unsigned long qemu_real_host_page_size;
 709 extern unsigned long qemu_host_page_bits;
 710 extern unsigned long qemu_host_page_size;
 711 extern unsigned long qemu_host_page_mask;
 712
 713 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
 714
 715 /* same as PROT_xxx */
 716 #define PAGE_READ      0x0001
 717 #define PAGE_WRITE     0x0002
 718 #define PAGE_EXEC      0x0004
 719 #define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
 720 #define PAGE_VALID     0x0008
 721 /* original state of the write flag (used when tracking self-modifying
 722    code */
 723 #define PAGE_WRITE_ORG 0x0010
 724 #define PAGE_RESERVED  0x0020
 725
 726 void page_dump(FILE *f);
 727 int page_get_flags(target_ulong address);
 728 void page_set_flags(target_ulong start, target_ulong end, int flags);
 729 int page_check_range(target_ulong start, target_ulong len, int flags);
 730
 731 CPUState *cpu_copy(CPUState *env);
 732
 733 void cpu_dump_state(CPUState *env, FILE *f,
 734                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 735                     int flags);
 736 void cpu_dump_statistics (CPUState *env, FILE *f,
 737                           int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 738                           int flags);
 739
 740 void cpu_abort(CPUState *env, const char *fmt, ...)
 741     __attribute__ ((__format__ (__printf__, 2, 3)))
 742     __attribute__ ((__noreturn__));
 743 extern CPUState *first_cpu;
 744 extern CPUState *cpu_single_env;
 745 extern int code_copy_enabled;
 746
 747 #define CPU_INTERRUPT_EXIT   0x01 /* wants exit from main loop */
 748 #define CPU_INTERRUPT_HARD   0x02 /* hardware interrupt pending */
 749 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
 750 #define CPU_INTERRUPT_TIMER  0x08 /* internal timer exception pending */
 751 #define CPU_INTERRUPT_FIQ    0x10 /* Fast interrupt pending.  */
 752 #define CPU_INTERRUPT_HALT   0x20 /* CPU halt wanted */
 753 #define CPU_INTERRUPT_SMI    0x40 /* (x86 only) SMI interrupt pending */
 754 #define CPU_INTERRUPT_DEBUG  0x80 /* Debug event occured.  */
 755 #define CPU_INTERRUPT_VIRQ   0x100 /* virtual interrupt pending.  */
 756
 757 void cpu_interrupt(CPUState *s, int mask);
 758 void cpu_reset_interrupt(CPUState *env, int mask);
 759
 760 int cpu_watchpoint_insert(CPUState *env, target_ulong addr);
 761 int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
 762 int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
 763 int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
 764 void cpu_single_step(CPUState *env, int enabled);
 765 void cpu_reset(CPUState *s);
 766
 767 /* Return the physical page corresponding to a virtual one. Use it
 768    only for debugging because no protection checks are done. Return -1
 769    if no page found. */
 770 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
 771
 772 #define CPU_LOG_TB_OUT_ASM (1 << 0)
 773 #define CPU_LOG_TB_IN_ASM  (1 << 1)
 774 #define CPU_LOG_TB_OP      (1 << 2)
 775 #define CPU_LOG_TB_OP_OPT  (1 << 3)
 776 #define CPU_LOG_INT        (1 << 4)
 777 #define CPU_LOG_EXEC       (1 << 5)
 778 #define CPU_LOG_PCALL      (1 << 6)
 779 #define CPU_LOG_IOPORT     (1 << 7)
 780 #define CPU_LOG_TB_CPU     (1 << 8)
 781
 782 /* define log items */
 783 typedef struct CPULogItem {
 784     int mask;
 785     const char *name;
 786     const char *help;
 787 } CPULogItem;
 788
 789 extern CPULogItem cpu_log_items[];
 790
 791 void cpu_set_log(int log_flags);
 792 void cpu_set_log_filename(const char *filename);
 793 int cpu_str_to_log_mask(const char *str);
 794
 795 /* IO ports API */
 796
 797 /* NOTE: as these functions may be even used when there is an isa
 798    brige on non x86 targets, we always defined them */
 799 #ifndef NO_CPU_IO_DEFS
 800 void cpu_outb(CPUState *env, int addr, int val);
 801 void cpu_outw(CPUState *env, int addr, int val);
 802 void cpu_outl(CPUState *env, int addr, int val);
 803 int cpu_inb(CPUState *env, int addr);
 804 int cpu_inw(CPUState *env, int addr);
 805 int cpu_inl(CPUState *env, int addr);
 806 #endif
 807
 808 /* memory API */
 809
 810 extern ram_addr_t phys_ram_size;
 811 extern int phys_ram_fd;
 812 extern uint8_t *phys_ram_base;
 813 extern uint8_t *phys_ram_dirty;
 814 extern uint8_t *bios_mem;
 815
 816 /* physical memory access */
 817 #define TLB_INVALID_MASK   (1 << 3)
 818 #define IO_MEM_SHIFT       4
 819 #define IO_MEM_NB_ENTRIES  (1 << (TARGET_PAGE_BITS  - IO_MEM_SHIFT))
 820
 821 #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
 822 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 823 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 824 #define IO_MEM_NOTDIRTY    (4 << IO_MEM_SHIFT) /* used internally, never use directly */
 825 /* acts like a ROM when read and like a device when written. As an
 826    exception, the write memory callback gets the ram offset instead of
 827    the physical address */
 828 #define IO_MEM_ROMD        (1)
 829 #define IO_MEM_SUBPAGE     (2)
 830 #define IO_MEM_SUBWIDTH    (4)
 831
 832 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
 833 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
 834
 835 void cpu_register_physical_memory(target_phys_addr_t start_addr,
 836                                   unsigned long size,
 837                                   unsigned long phys_offset);
 838 uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
 839 ram_addr_t qemu_ram_alloc(unsigned long size);
 840 void qemu_ram_free(ram_addr_t addr);
 841 int cpu_register_io_memory(int io_index,
 842                            CPUReadMemoryFunc **mem_read,
 843                            CPUWriteMemoryFunc **mem_write,
 844                            void *opaque);
 845 void cpu_unregister_io_memory(int table_address);
 846 CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
 847 CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
 848
 849 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
 850                             int len, int is_write);
 851 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
 852                                             uint8_t *buf, int len)
 853 {
 854     cpu_physical_memory_rw(addr, buf, len, 0);
 855 }
 856 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
 857                                              const uint8_t *buf, int len)
 858 {
 859     cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
 860 }
 861 uint32_t ldub_phys(target_phys_addr_t addr);
 862 uint32_t lduw_phys(target_phys_addr_t addr);
 863 uint32_t ldl_phys(target_phys_addr_t addr);
 864 uint64_t ldq_phys(target_phys_addr_t addr);
 865 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 866 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 867 void stb_phys(target_phys_addr_t addr, uint32_t val);
 868 void stw_phys(target_phys_addr_t addr, uint32_t val);
 869 void stl_phys(target_phys_addr_t addr, uint32_t val);
 870 void stq_phys(target_phys_addr_t addr, uint64_t val);
 871
 872 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 873                                    const uint8_t *buf, int len);
 874 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
 875                         uint8_t *buf, int len, int is_write);
 876
 877 #define VGA_DIRTY_FLAG  0x01
 878 #define CODE_DIRTY_FLAG 0x02
 879 #define MIGRATION_DIRTY_FLAG 0x08
 880
 881 /* read dirty bit (return 0 or 1) */
 882 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
 883 {
 884     return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
 885 }
 886
 887 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
 888                                                 int dirty_flags)
 889 {
 890     return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
 891 }
 892
 893 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
 894 {
 895     phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
 896 }
 897
 898 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
 899                                      int dirty_flags);
 900 void cpu_tlb_update_dirty(CPUState *env);
 901
 902 int cpu_physical_memory_set_dirty_tracking(int enable);
 903
 904 int cpu_physical_memory_get_dirty_tracking(void);
 905
 906 void dump_exec_info(FILE *f,
 907                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 908
 909 /*******************************************/
 910 /* host CPU ticks (if available) */
 911
 912 #if defined(__powerpc__)
 913
 914 static inline uint32_t get_tbl(void)
 915 {
 916     uint32_t tbl;
 917     asm volatile("mftb %0" : "=r" (tbl));
 918     return tbl;
 919 }
 920
 921 static inline uint32_t get_tbu(void)
 922 {
 923         uint32_t tbl;
 924         asm volatile("mftbu %0" : "=r" (tbl));
 925         return tbl;
 926 }
 927
 928 static inline int64_t cpu_get_real_ticks(void)
 929 {
 930     uint32_t l, h, h1;
 931     /* NOTE: we test if wrapping has occurred */
 932     do {
 933         h = get_tbu();
 934         l = get_tbl();
 935         h1 = get_tbu();
 936     } while (h != h1);
 937     return ((int64_t)h << 32) | l;
 938 }
 939
 940 #elif defined(__i386__)
 941
 942 static inline int64_t cpu_get_real_ticks(void)
 943 {
 944     int64_t val;
 945     asm volatile ("rdtsc" : "=A" (val));
 946     return val;
 947 }
 948
 949 #elif defined(__x86_64__)
 950
 951 static inline int64_t cpu_get_real_ticks(void)
 952 {
 953     uint32_t low,high;
 954     int64_t val;
 955     asm volatile("rdtsc" : "=a" (low), "=d" (high));
 956     val = high;
 957     val <<= 32;
 958     val |= low;
 959     return val;
 960 }
 961
 962 #elif defined(__ia64)
 963
 964 static inline int64_t cpu_get_real_ticks(void)
 965 {
 966         int64_t val;
 967         asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
 968         return val;
 969 }
 970
 971 #elif defined(__s390__)
 972
 973 static inline int64_t cpu_get_real_ticks(void)
 974 {
 975     int64_t val;
 976     asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
 977     return val;
 978 }
 979
 980 #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
 981
 982 static inline int64_t cpu_get_real_ticks (void)
 983 {
 984 #if     defined(_LP64)
 985         uint64_t        rval;
 986         asm volatile("rd %%tick,%0" : "=r"(rval));
 987         return rval;
 988 #else
 989         union {
 990                 uint64_t i64;
 991                 struct {
 992                         uint32_t high;
 993                         uint32_t low;
 994                 }       i32;
 995         } rval;
 996         asm volatile("rd %%tick,%1; srlx %1,32,%0"
 997                 : "=r"(rval.i32.high), "=r"(rval.i32.low));
 998         return rval.i64;
 999 #endif
1000 }
1001
1002 #elif defined(__mips__)
1003
1004 static inline int64_t cpu_get_real_ticks(void)
1005 {
1006 #if __mips_isa_rev >= 2
1007     uint32_t count;
1008     static uint32_t cyc_per_count = 0;
1009
1010     if (!cyc_per_count)
1011         __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));
1012
1013     __asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
1014     return (int64_t)(count * cyc_per_count);
1015 #else
1016     /* FIXME */
1017     static int64_t ticks = 0;
1018     return ticks++;
1019 #endif
1020 }
1021
1022 #else
1023 /* The host CPU doesn't have an easily accessible cycle counter.
1024    Just return a monotonically increasing value.  This will be
1025    totally wrong, but hopefully better than nothing.  */
1026 static inline int64_t cpu_get_real_ticks (void)
1027 {
1028     static int64_t ticks = 0;
1029     return ticks++;
1030 }
1031 #endif
1032
1033 /* profiling */
1034 #ifdef CONFIG_PROFILER
1035 static inline int64_t profile_getclock(void)
1036 {
1037     return cpu_get_real_ticks();
1038 }
1039
1040 extern int64_t kqemu_time, kqemu_time_start;
1041 extern int64_t qemu_time, qemu_time_start;
1042 extern int64_t tlb_flush_time;
1043 extern int64_t kqemu_exec_count;
1044 extern int64_t dev_time;
1045 extern int64_t kqemu_ret_int_count;
1046 extern int64_t kqemu_ret_excp_count;
1047 extern int64_t kqemu_ret_intr_count;
1048
1049 extern int64_t dyngen_tb_count1;
1050 extern int64_t dyngen_tb_count;
1051 extern int64_t dyngen_op_count;
1052 extern int64_t dyngen_old_op_count;
1053 extern int64_t dyngen_tcg_del_op_count;
1054 extern int dyngen_op_count_max;
1055 extern int64_t dyngen_code_in_len;
1056 extern int64_t dyngen_code_out_len;
1057 extern int64_t dyngen_interm_time;
1058 extern int64_t dyngen_code_time;
1059 extern int64_t dyngen_restore_count;
1060 extern int64_t dyngen_restore_time;
1061 #endif
1062
1063 #endif /* CPU_ALL_H */