4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifdef CONFIG_USER_ONLY
32 #include "qemu-common.h"
33 #include "qemu-char.h"
39 #include "qemu_socket.h"
41 /* XXX: these constants may be independent of the host ones even for Unix */
61 typedef struct GDBState
{
62 CPUState
*env
; /* current CPU */
63 enum RSState state
; /* parsing state */
67 uint8_t last_packet
[4100];
69 #ifdef CONFIG_USER_ONLY
77 #ifdef CONFIG_USER_ONLY
78 /* XXX: This is not thread safe. Do we care? */
79 static int gdbserver_fd
= -1;
81 /* XXX: remove this hack. */
82 static GDBState gdbserver_state
;
84 static int get_char(GDBState
*s
)
90 ret
= recv(s
->fd
, &ch
, 1, 0);
92 if (errno
!= EINTR
&& errno
!= EAGAIN
)
94 } else if (ret
== 0) {
104 /* GDB stub state for use by semihosting syscalls. */
105 static GDBState
*gdb_syscall_state
;
106 static gdb_syscall_complete_cb gdb_current_syscall_cb
;
114 /* If gdb is connected when the first semihosting syscall occurs then use
115 remote gdb syscalls. Otherwise use native file IO. */
116 int use_gdb_syscalls(void)
118 if (gdb_syscall_mode
== GDB_SYS_UNKNOWN
) {
119 gdb_syscall_mode
= (gdb_syscall_state
? GDB_SYS_ENABLED
122 return gdb_syscall_mode
== GDB_SYS_ENABLED
;
125 static void put_buffer(GDBState
*s
, const uint8_t *buf
, int len
)
127 #ifdef CONFIG_USER_ONLY
131 ret
= send(s
->fd
, buf
, len
, 0);
133 if (errno
!= EINTR
&& errno
!= EAGAIN
)
141 qemu_chr_write(s
->chr
, buf
, len
);
145 static inline int fromhex(int v
)
147 if (v
>= '0' && v
<= '9')
149 else if (v
>= 'A' && v
<= 'F')
151 else if (v
>= 'a' && v
<= 'f')
157 static inline int tohex(int v
)
165 static void memtohex(char *buf
, const uint8_t *mem
, int len
)
170 for(i
= 0; i
< len
; i
++) {
172 *q
++ = tohex(c
>> 4);
173 *q
++ = tohex(c
& 0xf);
178 static void hextomem(uint8_t *mem
, const char *buf
, int len
)
182 for(i
= 0; i
< len
; i
++) {
183 mem
[i
] = (fromhex(buf
[0]) << 4) | fromhex(buf
[1]);
188 /* return -1 if error, 0 if OK */
189 static int put_packet(GDBState
*s
, char *buf
)
195 printf("reply='%s'\n", buf
);
205 for(i
= 0; i
< len
; i
++) {
209 *(p
++) = tohex((csum
>> 4) & 0xf);
210 *(p
++) = tohex((csum
) & 0xf);
212 s
->last_packet_len
= p
- s
->last_packet
;
213 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
215 #ifdef CONFIG_USER_ONLY
228 #if defined(TARGET_I386)
230 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
233 uint32_t *registers
= (uint32_t *)mem_buf
;
236 /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
237 uint64_t *registers64
= (uint64_t *)mem_buf
;
239 if (env
->hflags
& HF_CS64_MASK
) {
240 registers64
[0] = tswap64(env
->regs
[R_EAX
]);
241 registers64
[1] = tswap64(env
->regs
[R_EBX
]);
242 registers64
[2] = tswap64(env
->regs
[R_ECX
]);
243 registers64
[3] = tswap64(env
->regs
[R_EDX
]);
244 registers64
[4] = tswap64(env
->regs
[R_ESI
]);
245 registers64
[5] = tswap64(env
->regs
[R_EDI
]);
246 registers64
[6] = tswap64(env
->regs
[R_EBP
]);
247 registers64
[7] = tswap64(env
->regs
[R_ESP
]);
248 for(i
= 8; i
< 16; i
++) {
249 registers64
[i
] = tswap64(env
->regs
[i
]);
251 registers64
[16] = tswap64(env
->eip
);
253 registers
= (uint32_t *)®isters64
[17];
254 registers
[0] = tswap32(env
->eflags
);
255 registers
[1] = tswap32(env
->segs
[R_CS
].selector
);
256 registers
[2] = tswap32(env
->segs
[R_SS
].selector
);
257 registers
[3] = tswap32(env
->segs
[R_DS
].selector
);
258 registers
[4] = tswap32(env
->segs
[R_ES
].selector
);
259 registers
[5] = tswap32(env
->segs
[R_FS
].selector
);
260 registers
[6] = tswap32(env
->segs
[R_GS
].selector
);
261 /* XXX: convert floats */
262 for(i
= 0; i
< 8; i
++) {
263 memcpy(mem_buf
+ 16 * 8 + 7 * 4 + i
* 10, &env
->fpregs
[i
], 10);
265 registers
[27] = tswap32(env
->fpuc
); /* fctrl */
266 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
267 registers
[28] = tswap32(fpus
); /* fstat */
268 registers
[29] = 0; /* ftag */
269 registers
[30] = 0; /* fiseg */
270 registers
[31] = 0; /* fioff */
271 registers
[32] = 0; /* foseg */
272 registers
[33] = 0; /* fooff */
273 registers
[34] = 0; /* fop */
274 for(i
= 0; i
< 16; i
++) {
275 memcpy(mem_buf
+ 16 * 8 + 35 * 4 + i
* 16, &env
->xmm_regs
[i
], 16);
277 registers
[99] = tswap32(env
->mxcsr
);
279 return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
283 for(i
= 0; i
< 8; i
++) {
284 registers
[i
] = env
->regs
[i
];
286 registers
[8] = env
->eip
;
287 registers
[9] = env
->eflags
;
288 registers
[10] = env
->segs
[R_CS
].selector
;
289 registers
[11] = env
->segs
[R_SS
].selector
;
290 registers
[12] = env
->segs
[R_DS
].selector
;
291 registers
[13] = env
->segs
[R_ES
].selector
;
292 registers
[14] = env
->segs
[R_FS
].selector
;
293 registers
[15] = env
->segs
[R_GS
].selector
;
294 /* XXX: convert floats */
295 for(i
= 0; i
< 8; i
++) {
296 memcpy(mem_buf
+ 16 * 4 + i
* 10, &env
->fpregs
[i
], 10);
298 registers
[36] = env
->fpuc
;
299 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
300 registers
[37] = fpus
;
301 registers
[38] = 0; /* XXX: convert tags */
302 registers
[39] = 0; /* fiseg */
303 registers
[40] = 0; /* fioff */
304 registers
[41] = 0; /* foseg */
305 registers
[42] = 0; /* fooff */
306 registers
[43] = 0; /* fop */
308 for(i
= 0; i
< 16; i
++)
309 tswapls(®isters
[i
]);
310 for(i
= 36; i
< 44; i
++)
311 tswapls(®isters
[i
]);
315 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
317 uint32_t *registers
= (uint32_t *)mem_buf
;
320 for(i
= 0; i
< 8; i
++) {
321 env
->regs
[i
] = tswapl(registers
[i
]);
323 env
->eip
= tswapl(registers
[8]);
324 env
->eflags
= tswapl(registers
[9]);
325 #if defined(CONFIG_USER_ONLY)
326 #define LOAD_SEG(index, sreg)\
327 if (tswapl(registers[index]) != env->segs[sreg].selector)\
328 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
338 #elif defined (TARGET_PPC)
339 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
341 uint32_t *registers
= (uint32_t *)mem_buf
, tmp
;
345 for(i
= 0; i
< 32; i
++) {
346 registers
[i
] = tswapl(env
->gpr
[i
]);
349 for (i
= 0; i
< 32; i
++) {
350 registers
[(i
* 2) + 32] = tswapl(*((uint32_t *)&env
->fpr
[i
]));
351 registers
[(i
* 2) + 33] = tswapl(*((uint32_t *)&env
->fpr
[i
] + 1));
353 /* nip, msr, ccr, lnk, ctr, xer, mq */
354 registers
[96] = tswapl(env
->nip
);
355 registers
[97] = tswapl(env
->msr
);
357 for (i
= 0; i
< 8; i
++)
358 tmp
|= env
->crf
[i
] << (32 - ((i
+ 1) * 4));
359 registers
[98] = tswapl(tmp
);
360 registers
[99] = tswapl(env
->lr
);
361 registers
[100] = tswapl(env
->ctr
);
362 registers
[101] = tswapl(ppc_load_xer(env
));
368 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
370 uint32_t *registers
= (uint32_t *)mem_buf
;
374 for (i
= 0; i
< 32; i
++) {
375 env
->gpr
[i
] = tswapl(registers
[i
]);
378 for (i
= 0; i
< 32; i
++) {
379 *((uint32_t *)&env
->fpr
[i
]) = tswapl(registers
[(i
* 2) + 32]);
380 *((uint32_t *)&env
->fpr
[i
] + 1) = tswapl(registers
[(i
* 2) + 33]);
382 /* nip, msr, ccr, lnk, ctr, xer, mq */
383 env
->nip
= tswapl(registers
[96]);
384 ppc_store_msr(env
, tswapl(registers
[97]));
385 registers
[98] = tswapl(registers
[98]);
386 for (i
= 0; i
< 8; i
++)
387 env
->crf
[i
] = (registers
[98] >> (32 - ((i
+ 1) * 4))) & 0xF;
388 env
->lr
= tswapl(registers
[99]);
389 env
->ctr
= tswapl(registers
[100]);
390 ppc_store_xer(env
, tswapl(registers
[101]));
392 #elif defined (TARGET_SPARC)
393 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
395 target_ulong
*registers
= (target_ulong
*)mem_buf
;
399 for(i
= 0; i
< 8; i
++) {
400 registers
[i
] = tswapl(env
->gregs
[i
]);
402 /* fill in register window */
403 for(i
= 0; i
< 24; i
++) {
404 registers
[i
+ 8] = tswapl(env
->regwptr
[i
]);
406 #ifndef TARGET_SPARC64
408 for (i
= 0; i
< 32; i
++) {
409 registers
[i
+ 32] = tswapl(*((uint32_t *)&env
->fpr
[i
]));
411 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
412 registers
[64] = tswapl(env
->y
);
417 registers
[65] = tswapl(tmp
);
419 registers
[66] = tswapl(env
->wim
);
420 registers
[67] = tswapl(env
->tbr
);
421 registers
[68] = tswapl(env
->pc
);
422 registers
[69] = tswapl(env
->npc
);
423 registers
[70] = tswapl(env
->fsr
);
424 registers
[71] = 0; /* csr */
426 return 73 * sizeof(target_ulong
);
429 for (i
= 0; i
< 64; i
+= 2) {
432 tmp
= ((uint64_t)*(uint32_t *)&env
->fpr
[i
]) << 32;
433 tmp
|= *(uint32_t *)&env
->fpr
[i
+ 1];
434 registers
[i
/ 2 + 32] = tswap64(tmp
);
436 registers
[64] = tswapl(env
->pc
);
437 registers
[65] = tswapl(env
->npc
);
438 registers
[66] = tswapl(((uint64_t)GET_CCR(env
) << 32) |
439 ((env
->asi
& 0xff) << 24) |
440 ((env
->pstate
& 0xfff) << 8) |
442 registers
[67] = tswapl(env
->fsr
);
443 registers
[68] = tswapl(env
->fprs
);
444 registers
[69] = tswapl(env
->y
);
445 return 70 * sizeof(target_ulong
);
449 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
451 target_ulong
*registers
= (target_ulong
*)mem_buf
;
455 for(i
= 0; i
< 7; i
++) {
456 env
->gregs
[i
] = tswapl(registers
[i
]);
458 /* fill in register window */
459 for(i
= 0; i
< 24; i
++) {
460 env
->regwptr
[i
] = tswapl(registers
[i
+ 8]);
462 #ifndef TARGET_SPARC64
464 for (i
= 0; i
< 32; i
++) {
465 *((uint32_t *)&env
->fpr
[i
]) = tswapl(registers
[i
+ 32]);
467 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
468 env
->y
= tswapl(registers
[64]);
469 PUT_PSR(env
, tswapl(registers
[65]));
470 env
->wim
= tswapl(registers
[66]);
471 env
->tbr
= tswapl(registers
[67]);
472 env
->pc
= tswapl(registers
[68]);
473 env
->npc
= tswapl(registers
[69]);
474 env
->fsr
= tswapl(registers
[70]);
476 for (i
= 0; i
< 64; i
+= 2) {
479 tmp
= tswap64(registers
[i
/ 2 + 32]);
480 *((uint32_t *)&env
->fpr
[i
]) = tmp
>> 32;
481 *((uint32_t *)&env
->fpr
[i
+ 1]) = tmp
& 0xffffffff;
483 env
->pc
= tswapl(registers
[64]);
484 env
->npc
= tswapl(registers
[65]);
486 uint64_t tmp
= tswapl(registers
[66]);
488 PUT_CCR(env
, tmp
>> 32);
489 env
->asi
= (tmp
>> 24) & 0xff;
490 env
->pstate
= (tmp
>> 8) & 0xfff;
491 PUT_CWP64(env
, tmp
& 0xff);
493 env
->fsr
= tswapl(registers
[67]);
494 env
->fprs
= tswapl(registers
[68]);
495 env
->y
= tswapl(registers
[69]);
498 #elif defined (TARGET_ARM)
499 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
505 /* 16 core integer registers (4 bytes each). */
506 for (i
= 0; i
< 16; i
++)
508 *(uint32_t *)ptr
= tswapl(env
->regs
[i
]);
511 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
512 Not yet implemented. */
513 memset (ptr
, 0, 8 * 12 + 4);
515 /* CPSR (4 bytes). */
516 *(uint32_t *)ptr
= tswapl (cpsr_read(env
));
519 return ptr
- mem_buf
;
522 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
528 /* Core integer registers. */
529 for (i
= 0; i
< 16; i
++)
531 env
->regs
[i
] = tswapl(*(uint32_t *)ptr
);
534 /* Ignore FPA regs and scr. */
536 cpsr_write (env
, tswapl(*(uint32_t *)ptr
), 0xffffffff);
538 #elif defined (TARGET_M68K)
539 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
547 for (i
= 0; i
< 8; i
++) {
548 *(uint32_t *)ptr
= tswapl(env
->dregs
[i
]);
552 for (i
= 0; i
< 8; i
++) {
553 *(uint32_t *)ptr
= tswapl(env
->aregs
[i
]);
556 *(uint32_t *)ptr
= tswapl(env
->sr
);
558 *(uint32_t *)ptr
= tswapl(env
->pc
);
560 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
561 ColdFire has 8-bit double precision registers. */
562 for (i
= 0; i
< 8; i
++) {
564 *(uint32_t *)ptr
= tswap32(u
.l
.upper
);
565 *(uint32_t *)ptr
= tswap32(u
.l
.lower
);
567 /* FP control regs (not implemented). */
568 memset (ptr
, 0, 3 * 4);
571 return ptr
- mem_buf
;
574 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
582 for (i
= 0; i
< 8; i
++) {
583 env
->dregs
[i
] = tswapl(*(uint32_t *)ptr
);
587 for (i
= 0; i
< 8; i
++) {
588 env
->aregs
[i
] = tswapl(*(uint32_t *)ptr
);
591 env
->sr
= tswapl(*(uint32_t *)ptr
);
593 env
->pc
= tswapl(*(uint32_t *)ptr
);
595 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
596 ColdFire has 8-bit double precision registers. */
597 for (i
= 0; i
< 8; i
++) {
598 u
.l
.upper
= tswap32(*(uint32_t *)ptr
);
599 u
.l
.lower
= tswap32(*(uint32_t *)ptr
);
602 /* FP control regs (not implemented). */
605 #elif defined (TARGET_MIPS)
606 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
612 for (i
= 0; i
< 32; i
++)
614 *(target_ulong
*)ptr
= tswapl(env
->gpr
[i
][env
->current_tc
]);
615 ptr
+= sizeof(target_ulong
);
618 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_Status
);
619 ptr
+= sizeof(target_ulong
);
621 *(target_ulong
*)ptr
= tswapl(env
->LO
[0][env
->current_tc
]);
622 ptr
+= sizeof(target_ulong
);
624 *(target_ulong
*)ptr
= tswapl(env
->HI
[0][env
->current_tc
]);
625 ptr
+= sizeof(target_ulong
);
627 *(target_ulong
*)ptr
= tswapl(env
->CP0_BadVAddr
);
628 ptr
+= sizeof(target_ulong
);
630 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_Cause
);
631 ptr
+= sizeof(target_ulong
);
633 *(target_ulong
*)ptr
= tswapl(env
->PC
[env
->current_tc
]);
634 ptr
+= sizeof(target_ulong
);
636 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
638 for (i
= 0; i
< 32; i
++)
640 if (env
->CP0_Status
& (1 << CP0St_FR
))
641 *(target_ulong
*)ptr
= tswapl(env
->fpu
->fpr
[i
].d
);
643 *(target_ulong
*)ptr
= tswap32(env
->fpu
->fpr
[i
].w
[FP_ENDIAN_IDX
]);
644 ptr
+= sizeof(target_ulong
);
647 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->fpu
->fcr31
);
648 ptr
+= sizeof(target_ulong
);
650 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->fpu
->fcr0
);
651 ptr
+= sizeof(target_ulong
);
654 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
655 *(target_ulong
*)ptr
= 0;
656 ptr
+= sizeof(target_ulong
);
658 /* Registers for embedded use, we just pad them. */
659 for (i
= 0; i
< 16; i
++)
661 *(target_ulong
*)ptr
= 0;
662 ptr
+= sizeof(target_ulong
);
666 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_PRid
);
667 ptr
+= sizeof(target_ulong
);
669 return ptr
- mem_buf
;
672 /* convert MIPS rounding mode in FCR31 to IEEE library */
673 static unsigned int ieee_rm
[] =
675 float_round_nearest_even
,
680 #define RESTORE_ROUNDING_MODE \
681 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
683 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
689 for (i
= 0; i
< 32; i
++)
691 env
->gpr
[i
][env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
692 ptr
+= sizeof(target_ulong
);
695 env
->CP0_Status
= tswapl(*(target_ulong
*)ptr
);
696 ptr
+= sizeof(target_ulong
);
698 env
->LO
[0][env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
699 ptr
+= sizeof(target_ulong
);
701 env
->HI
[0][env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
702 ptr
+= sizeof(target_ulong
);
704 env
->CP0_BadVAddr
= tswapl(*(target_ulong
*)ptr
);
705 ptr
+= sizeof(target_ulong
);
707 env
->CP0_Cause
= tswapl(*(target_ulong
*)ptr
);
708 ptr
+= sizeof(target_ulong
);
710 env
->PC
[env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
711 ptr
+= sizeof(target_ulong
);
713 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
715 for (i
= 0; i
< 32; i
++)
717 if (env
->CP0_Status
& (1 << CP0St_FR
))
718 env
->fpu
->fpr
[i
].d
= tswapl(*(target_ulong
*)ptr
);
720 env
->fpu
->fpr
[i
].w
[FP_ENDIAN_IDX
] = tswapl(*(target_ulong
*)ptr
);
721 ptr
+= sizeof(target_ulong
);
724 env
->fpu
->fcr31
= tswapl(*(target_ulong
*)ptr
) & 0xFF83FFFF;
725 ptr
+= sizeof(target_ulong
);
727 /* The remaining registers are assumed to be read-only. */
729 /* set rounding mode */
730 RESTORE_ROUNDING_MODE
;
732 #ifndef CONFIG_SOFTFLOAT
733 /* no floating point exception for native float */
734 SET_FP_ENABLE(env
->fcr31
, 0);
738 #elif defined (TARGET_SH4)
740 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
742 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
744 uint32_t *ptr
= (uint32_t *)mem_buf
;
747 #define SAVE(x) *ptr++=tswapl(x)
748 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
749 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
+ 16]);
751 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
]);
753 for (i
= 8; i
< 16; i
++) SAVE(env
->gregs
[i
]);
763 for (i
= 0; i
< 16; i
++)
764 SAVE(env
->fregs
[i
+ ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
767 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
]);
768 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
+ 16]);
769 return ((uint8_t *)ptr
- mem_buf
);
772 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
774 uint32_t *ptr
= (uint32_t *)mem_buf
;
777 #define LOAD(x) (x)=*ptr++;
778 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
779 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
+ 16]);
781 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
]);
783 for (i
= 8; i
< 16; i
++) LOAD(env
->gregs
[i
]);
793 for (i
= 0; i
< 16; i
++)
794 LOAD(env
->fregs
[i
+ ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
797 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
]);
798 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
+ 16]);
800 #elif defined (TARGET_CRIS)
802 static int cris_save_32 (unsigned char *d
, uint32_t value
)
805 *d
++ = (value
>>= 8);
806 *d
++ = (value
>>= 8);
807 *d
++ = (value
>>= 8);
810 static int cris_save_16 (unsigned char *d
, uint32_t value
)
813 *d
++ = (value
>>= 8);
816 static int cris_save_8 (unsigned char *d
, uint32_t value
)
822 /* FIXME: this will bug on archs not supporting unaligned word accesses. */
823 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
825 uint8_t *ptr
= mem_buf
;
829 for (i
= 0; i
< 16; i
++)
830 ptr
+= cris_save_32 (ptr
, env
->regs
[i
]);
832 srs
= env
->pregs
[SR_SRS
];
834 ptr
+= cris_save_8 (ptr
, env
->pregs
[0]);
835 ptr
+= cris_save_8 (ptr
, env
->pregs
[1]);
836 ptr
+= cris_save_32 (ptr
, env
->pregs
[2]);
837 ptr
+= cris_save_8 (ptr
, srs
);
838 ptr
+= cris_save_16 (ptr
, env
->pregs
[4]);
840 for (i
= 5; i
< 16; i
++)
841 ptr
+= cris_save_32 (ptr
, env
->pregs
[i
]);
843 ptr
+= cris_save_32 (ptr
, env
->pc
);
845 for (i
= 0; i
< 16; i
++)
846 ptr
+= cris_save_32 (ptr
, env
->sregs
[srs
][i
]);
848 return ((uint8_t *)ptr
- mem_buf
);
851 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
853 uint32_t *ptr
= (uint32_t *)mem_buf
;
856 #define LOAD(x) (x)=*ptr++;
857 for (i
= 0; i
< 16; i
++) LOAD(env
->regs
[i
]);
861 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
866 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
872 static int gdb_handle_packet(GDBState
*s
, CPUState
*env
, const char *line_buf
)
875 int ch
, reg_size
, type
;
877 uint8_t mem_buf
[4096];
879 target_ulong addr
, len
;
882 printf("command='%s'\n", line_buf
);
888 /* TODO: Make this return the correct value for user-mode. */
889 snprintf(buf
, sizeof(buf
), "S%02x", SIGTRAP
);
894 addr
= strtoull(p
, (char **)&p
, 16);
895 #if defined(TARGET_I386)
898 kvm_load_registers(env
);
900 #elif defined (TARGET_PPC)
902 #elif defined (TARGET_SPARC)
905 #elif defined (TARGET_ARM)
906 env
->regs
[15] = addr
;
907 #elif defined (TARGET_SH4)
909 #elif defined (TARGET_MIPS)
910 env
->PC
[env
->current_tc
] = addr
;
911 #elif defined (TARGET_CRIS)
915 #ifdef CONFIG_USER_ONLY
916 s
->running_state
= 1;
923 addr
= strtoull(p
, (char **)&p
, 16);
924 #if defined(TARGET_I386)
927 kvm_load_registers(env
);
929 #elif defined (TARGET_PPC)
931 #elif defined (TARGET_SPARC)
934 #elif defined (TARGET_ARM)
935 env
->regs
[15] = addr
;
936 #elif defined (TARGET_SH4)
938 #elif defined (TARGET_MIPS)
939 env
->PC
[env
->current_tc
] = addr
;
940 #elif defined (TARGET_CRIS)
944 cpu_single_step(env
, 1);
945 #ifdef CONFIG_USER_ONLY
946 s
->running_state
= 1;
956 ret
= strtoull(p
, (char **)&p
, 16);
959 err
= strtoull(p
, (char **)&p
, 16);
966 if (gdb_current_syscall_cb
)
967 gdb_current_syscall_cb(s
->env
, ret
, err
);
969 put_packet(s
, "T02");
971 #ifdef CONFIG_USER_ONLY
972 s
->running_state
= 1;
981 kvm_save_registers(env
);
983 reg_size
= cpu_gdb_read_registers(env
, mem_buf
);
984 memtohex(buf
, mem_buf
, reg_size
);
988 registers
= (void *)mem_buf
;
990 hextomem((uint8_t *)registers
, p
, len
);
991 cpu_gdb_write_registers(env
, mem_buf
, len
);
993 kvm_load_registers(env
);
998 addr
= strtoull(p
, (char **)&p
, 16);
1001 len
= strtoull(p
, NULL
, 16);
1002 if (cpu_memory_rw_debug(env
, addr
, mem_buf
, len
, 0) != 0) {
1003 put_packet (s
, "E14");
1005 memtohex(buf
, mem_buf
, len
);
1010 addr
= strtoull(p
, (char **)&p
, 16);
1013 len
= strtoull(p
, (char **)&p
, 16);
1016 hextomem(mem_buf
, p
, len
);
1017 if (cpu_memory_rw_debug(env
, addr
, mem_buf
, len
, 1) != 0)
1018 put_packet(s
, "E14");
1020 put_packet(s
, "OK");
1023 type
= strtoul(p
, (char **)&p
, 16);
1026 addr
= strtoull(p
, (char **)&p
, 16);
1029 len
= strtoull(p
, (char **)&p
, 16);
1030 if (type
== 0 || type
== 1) {
1031 if (cpu_breakpoint_insert(env
, addr
) < 0)
1032 goto breakpoint_error
;
1033 put_packet(s
, "OK");
1034 #ifndef CONFIG_USER_ONLY
1035 } else if (type
== 2) {
1036 if (cpu_watchpoint_insert(env
, addr
) < 0)
1037 goto breakpoint_error
;
1038 put_packet(s
, "OK");
1042 put_packet(s
, "E22");
1046 type
= strtoul(p
, (char **)&p
, 16);
1049 addr
= strtoull(p
, (char **)&p
, 16);
1052 len
= strtoull(p
, (char **)&p
, 16);
1053 if (type
== 0 || type
== 1) {
1054 cpu_breakpoint_remove(env
, addr
);
1055 put_packet(s
, "OK");
1056 #ifndef CONFIG_USER_ONLY
1057 } else if (type
== 2) {
1058 cpu_watchpoint_remove(env
, addr
);
1059 put_packet(s
, "OK");
1062 goto breakpoint_error
;
1065 #ifdef CONFIG_LINUX_USER
1067 if (strncmp(p
, "Offsets", 7) == 0) {
1068 TaskState
*ts
= env
->opaque
;
1071 "Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
1072 ";Bss=" TARGET_ABI_FMT_lx
,
1073 ts
->info
->code_offset
,
1074 ts
->info
->data_offset
,
1075 ts
->info
->data_offset
);
1083 /* put empty packet */
1091 extern void tb_flush(CPUState
*env
);
1093 #ifndef CONFIG_USER_ONLY
1094 static void gdb_vm_stopped(void *opaque
, int reason
)
1096 GDBState
*s
= opaque
;
1100 if (s
->state
== RS_SYSCALL
)
1103 /* disable single step if it was enable */
1104 cpu_single_step(s
->env
, 0);
1106 if (reason
== EXCP_DEBUG
) {
1107 if (s
->env
->watchpoint_hit
) {
1108 snprintf(buf
, sizeof(buf
), "T%02xwatch:" TARGET_FMT_lx
";",
1110 s
->env
->watchpoint
[s
->env
->watchpoint_hit
- 1].vaddr
);
1112 s
->env
->watchpoint_hit
= 0;
1117 } else if (reason
== EXCP_INTERRUPT
) {
1122 snprintf(buf
, sizeof(buf
), "S%02x", ret
);
1127 /* Send a gdb syscall request.
1128 This accepts limited printf-style format specifiers, specifically:
1129 %x - target_ulong argument printed in hex.
1130 %lx - 64-bit argument printed in hex.
1131 %s - string pointer (target_ulong) and length (int) pair. */
1132 void gdb_do_syscall(gdb_syscall_complete_cb cb
, char *fmt
, ...)
1141 s
= gdb_syscall_state
;
1144 gdb_current_syscall_cb
= cb
;
1145 s
->state
= RS_SYSCALL
;
1146 #ifndef CONFIG_USER_ONLY
1147 vm_stop(EXCP_DEBUG
);
1158 addr
= va_arg(va
, target_ulong
);
1159 p
+= sprintf(p
, TARGET_FMT_lx
, addr
);
1162 if (*(fmt
++) != 'x')
1164 i64
= va_arg(va
, uint64_t);
1165 p
+= sprintf(p
, "%" PRIx64
, i64
);
1168 addr
= va_arg(va
, target_ulong
);
1169 p
+= sprintf(p
, TARGET_FMT_lx
"/%x", addr
, va_arg(va
, int));
1173 fprintf(stderr
, "gdbstub: Bad syscall format string '%s'\n",
1184 #ifdef CONFIG_USER_ONLY
1185 gdb_handlesig(s
->env
, 0);
1187 cpu_interrupt(s
->env
, CPU_INTERRUPT_EXIT
);
1191 static void gdb_read_byte(GDBState
*s
, int ch
)
1193 CPUState
*env
= s
->env
;
1197 #ifndef CONFIG_USER_ONLY
1198 if (s
->last_packet_len
) {
1199 /* Waiting for a response to the last packet. If we see the start
1200 of a new command then abandon the previous response. */
1203 printf("Got NACK, retransmitting\n");
1205 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
1209 printf("Got ACK\n");
1211 printf("Got '%c' when expecting ACK/NACK\n", ch
);
1213 if (ch
== '+' || ch
== '$')
1214 s
->last_packet_len
= 0;
1219 /* when the CPU is running, we cannot do anything except stop
1220 it when receiving a char */
1221 vm_stop(EXCP_INTERRUPT
);
1228 s
->line_buf_index
= 0;
1229 s
->state
= RS_GETLINE
;
1234 s
->state
= RS_CHKSUM1
;
1235 } else if (s
->line_buf_index
>= sizeof(s
->line_buf
) - 1) {
1238 s
->line_buf
[s
->line_buf_index
++] = ch
;
1242 s
->line_buf
[s
->line_buf_index
] = '\0';
1243 s
->line_csum
= fromhex(ch
) << 4;
1244 s
->state
= RS_CHKSUM2
;
1247 s
->line_csum
|= fromhex(ch
);
1249 for(i
= 0; i
< s
->line_buf_index
; i
++) {
1250 csum
+= s
->line_buf
[i
];
1252 if (s
->line_csum
!= (csum
& 0xff)) {
1254 put_buffer(s
, &reply
, 1);
1258 put_buffer(s
, &reply
, 1);
1259 s
->state
= gdb_handle_packet(s
, env
, s
->line_buf
);
1268 #ifdef CONFIG_USER_ONLY
1270 gdb_handlesig (CPUState
*env
, int sig
)
1276 if (gdbserver_fd
< 0)
1279 s
= &gdbserver_state
;
1281 /* disable single step if it was enabled */
1282 cpu_single_step(env
, 0);
1287 snprintf(buf
, sizeof(buf
), "S%02x", sig
);
1293 s
->running_state
= 0;
1294 while (s
->running_state
== 0) {
1295 n
= read (s
->fd
, buf
, 256);
1300 for (i
= 0; i
< n
; i
++)
1301 gdb_read_byte (s
, buf
[i
]);
1303 else if (n
== 0 || errno
!= EAGAIN
)
1305 /* XXX: Connection closed. Should probably wait for annother
1306 connection before continuing. */
1313 /* Tell the remote gdb that the process has exited. */
1314 void gdb_exit(CPUState
*env
, int code
)
1319 if (gdbserver_fd
< 0)
1322 s
= &gdbserver_state
;
1324 snprintf(buf
, sizeof(buf
), "W%02x", code
);
1329 static void gdb_accept(void *opaque
)
1332 struct sockaddr_in sockaddr
;
1337 len
= sizeof(sockaddr
);
1338 fd
= accept(gdbserver_fd
, (struct sockaddr
*)&sockaddr
, &len
);
1339 if (fd
< 0 && errno
!= EINTR
) {
1342 } else if (fd
>= 0) {
1347 /* set short latency */
1349 setsockopt(fd
, IPPROTO_TCP
, TCP_NODELAY
, (char *)&val
, sizeof(val
));
1351 s
= &gdbserver_state
;
1352 memset (s
, 0, sizeof (GDBState
));
1353 s
->env
= first_cpu
; /* XXX: allow to change CPU */
1356 gdb_syscall_state
= s
;
1358 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
1361 static int gdbserver_open(int port
)
1363 struct sockaddr_in sockaddr
;
1366 fd
= socket(PF_INET
, SOCK_STREAM
, 0);
1372 /* allow fast reuse */
1374 setsockopt(fd
, SOL_SOCKET
, SO_REUSEADDR
, (char *)&val
, sizeof(val
));
1376 sockaddr
.sin_family
= AF_INET
;
1377 sockaddr
.sin_port
= htons(port
);
1378 sockaddr
.sin_addr
.s_addr
= 0;
1379 ret
= bind(fd
, (struct sockaddr
*)&sockaddr
, sizeof(sockaddr
));
1384 ret
= listen(fd
, 0);
1392 int gdbserver_start(int port
)
1394 gdbserver_fd
= gdbserver_open(port
);
1395 if (gdbserver_fd
< 0)
1397 /* accept connections */
1402 static int gdb_chr_can_receive(void *opaque
)
1407 static void gdb_chr_receive(void *opaque
, const uint8_t *buf
, int size
)
1409 GDBState
*s
= opaque
;
1412 for (i
= 0; i
< size
; i
++) {
1413 gdb_read_byte(s
, buf
[i
]);
1417 static void gdb_chr_event(void *opaque
, int event
)
1420 case CHR_EVENT_RESET
:
1421 vm_stop(EXCP_INTERRUPT
);
1422 gdb_syscall_state
= opaque
;
1429 int gdbserver_start(const char *port
)
1432 char gdbstub_port_name
[128];
1435 CharDriverState
*chr
;
1437 if (!port
|| !*port
)
1440 port_num
= strtol(port
, &p
, 10);
1442 /* A numeric value is interpreted as a port number. */
1443 snprintf(gdbstub_port_name
, sizeof(gdbstub_port_name
),
1444 "tcp::%d,nowait,nodelay,server", port_num
);
1445 port
= gdbstub_port_name
;
1448 chr
= qemu_chr_open(port
);
1452 s
= qemu_mallocz(sizeof(GDBState
));
1456 s
->env
= first_cpu
; /* XXX: allow to change CPU */
1458 qemu_chr_add_handlers(chr
, gdb_chr_can_receive
, gdb_chr_receive
,
1460 qemu_add_vm_stop_handler(gdb_vm_stopped
, s
);