hw/ppc4xx.h

   1 /*
   2  * QEMU PowerPC 4xx emulation shared definitions
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Copyright 2008 IBM Corp.
   7  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #if !defined(PPC_4XX_H)
  29 #define PPC_4XX_H
  30
  31 /* PowerPC 4xx core initialization */
  32 CPUState *ppc4xx_init (const char *cpu_model,
  33                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  34                        uint32_t sysclk);
  35
  36 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
  37 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
  38                           target_phys_addr_t offset, uint32_t len,
  39                           CPUReadMemoryFunc **mem_read,
  40                           CPUWriteMemoryFunc **mem_write, void *opaque);
  41 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
  42
  43 /* PowerPC 4xx universal interrupt controller */
  44 enum {
  45     PPCUIC_OUTPUT_INT = 0,
  46     PPCUIC_OUTPUT_CINT = 1,
  47     PPCUIC_OUTPUT_NB,
  48 };
  49 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
  50                        uint32_t dcr_base, int has_ssr, int has_vr);
  51
  52
  53 struct pci_master_map {
  54     uint32_t la;
  55     uint32_t ma;
  56     uint32_t pcila;
  57     uint32_t pciha;
  58 };
  59
  60 struct pci_target_map {
  61     uint32_t ms;
  62     uint32_t la;
  63     uint32_t bar;
  64 };
  65
  66 #define PPC44x_PCI_NR_PMMS 3
  67 #define PPC44x_PCI_NR_PTMS 2
  68
  69 struct ppc4xx_pci_t {
  70     target_phys_addr_t config_space;
  71     target_phys_addr_t registers;
  72     struct pci_master_map pmm[PPC44x_PCI_NR_PMMS];
  73     struct pci_target_map ptm[PPC44x_PCI_NR_PTMS];
  74
  75     unsigned int pmm_offset_flags;
  76     qemu_irq *pic;
  77
  78     uint32_t pcic0_cfgaddr;
  79     PCIBus *bus;
  80 };
  81 typedef struct ppc4xx_pci_t ppc4xx_pci_t;
  82
  83 ppc4xx_pci_t *ppc4xx_pci_init(CPUState *env, qemu_irq *pic,
  84                               target_phys_addr_t config_space,
  85                               target_phys_addr_t int_ack,
  86                               target_phys_addr_t special_cycle,
  87                               target_phys_addr_t registers);
  88
  89 #endif /* !defined(PPC_4XX_H) */