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Fix io.h include merge confilict
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blob3c82ebe84e77774f8f664cd03814b711f012b247
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #ifndef _WIN32
35 #include <sys/mman.h>
36 #endif
37 #include "qemu-kvm.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
56
57 // ID
58 #define CIRRUS_ID_CLGD5422 (0x23<<2)
59 #define CIRRUS_ID_CLGD5426 (0x24<<2)
60 #define CIRRUS_ID_CLGD5424 (0x25<<2)
61 #define CIRRUS_ID_CLGD5428 (0x26<<2)
62 #define CIRRUS_ID_CLGD5430 (0x28<<2)
63 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
64 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
65 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
66
67 // sequencer 0x07
68 #define CIRRUS_SR7_BPP_VGA 0x00
69 #define CIRRUS_SR7_BPP_SVGA 0x01
70 #define CIRRUS_SR7_BPP_MASK 0x0e
71 #define CIRRUS_SR7_BPP_8 0x00
72 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
73 #define CIRRUS_SR7_BPP_24 0x04
74 #define CIRRUS_SR7_BPP_16 0x06
75 #define CIRRUS_SR7_BPP_32 0x08
76 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
77
78 // sequencer 0x0f
79 #define CIRRUS_MEMSIZE_512k 0x08
80 #define CIRRUS_MEMSIZE_1M 0x10
81 #define CIRRUS_MEMSIZE_2M 0x18
82 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
83
84 // sequencer 0x12
85 #define CIRRUS_CURSOR_SHOW 0x01
86 #define CIRRUS_CURSOR_HIDDENPEL 0x02
87 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
88
89 // sequencer 0x17
90 #define CIRRUS_BUSTYPE_VLBFAST 0x10
91 #define CIRRUS_BUSTYPE_PCI 0x20
92 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
93 #define CIRRUS_BUSTYPE_ISA 0x38
94 #define CIRRUS_MMIO_ENABLE 0x04
95 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
96 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
97
98 // control 0x0b
99 #define CIRRUS_BANKING_DUAL 0x01
100 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
101
102 // control 0x30
103 #define CIRRUS_BLTMODE_BACKWARDS 0x01
104 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
105 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
106 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
107 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
108 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
109 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
110 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
111 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
112 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
113 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
114
115 // control 0x31
116 #define CIRRUS_BLT_BUSY 0x01
117 #define CIRRUS_BLT_START 0x02
118 #define CIRRUS_BLT_RESET 0x04
119 #define CIRRUS_BLT_FIFOUSED 0x10
120 #define CIRRUS_BLT_AUTOSTART 0x80
121
122 // control 0x32
123 #define CIRRUS_ROP_0 0x00
124 #define CIRRUS_ROP_SRC_AND_DST 0x05
125 #define CIRRUS_ROP_NOP 0x06
126 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
127 #define CIRRUS_ROP_NOTDST 0x0b
128 #define CIRRUS_ROP_SRC 0x0d
129 #define CIRRUS_ROP_1 0x0e
130 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
131 #define CIRRUS_ROP_SRC_XOR_DST 0x59
132 #define CIRRUS_ROP_SRC_OR_DST 0x6d
133 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
134 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
135 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
136 #define CIRRUS_ROP_NOTSRC 0xd0
137 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
138 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
139
140 #define CIRRUS_ROP_NOP_INDEX 2
141 #define CIRRUS_ROP_SRC_INDEX 5
142
143 // control 0x33
144 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
145 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
146 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
147
148 // memory-mapped IO
149 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
150 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
151 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
152 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
153 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
154 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
155 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
156 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
157 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
158 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
159 #define CIRRUS_MMIO_BLTROP 0x1a // byte
160 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
161 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
162 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
163 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
164 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
165 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
166 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
169 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
170 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
171 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
172 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
173 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
174 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
175 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
176 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
177 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
178
179 // PCI 0x00: vendor, 0x02: device
180 #define PCI_VENDOR_CIRRUS 0x1013
181 #define PCI_DEVICE_CLGD5462 0x00d0
182 #define PCI_DEVICE_CLGD5465 0x00d6
183
184 // PCI 0x04: command(word), 0x06(word): status
185 #define PCI_COMMAND_IOACCESS 0x0001
186 #define PCI_COMMAND_MEMACCESS 0x0002
187 #define PCI_COMMAND_BUSMASTER 0x0004
188 #define PCI_COMMAND_SPECIALCYCLE 0x0008
189 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
190 #define PCI_COMMAND_PALETTESNOOPING 0x0020
191 #define PCI_COMMAND_PARITYDETECTION 0x0040
192 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
193 #define PCI_COMMAND_SERR 0x0100
194 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
195 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
196 #define PCI_CLASS_BASE_DISPLAY 0x03
197 // PCI 0x08, 0x00ff0000
198 #define PCI_CLASS_SUB_VGA 0x00
199 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
200 #define PCI_CLASS_HEADERTYPE_00h 0x00
201 // 0x10-0x3f (headertype 00h)
202 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
203 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
204 #define PCI_MAP_MEM 0x0
205 #define PCI_MAP_IO 0x1
206 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
207 #define PCI_MAP_IO_ADDR_MASK (~0x3)
208 #define PCI_MAP_MEMFLAGS_32BIT 0x0
209 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
210 #define PCI_MAP_MEMFLAGS_64BIT 0x4
211 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
212 // PCI 0x28: cardbus CIS pointer
213 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
214 // PCI 0x30: expansion ROM base address
215 #define PCI_ROMBIOS_ENABLED 0x1
216 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
217 // PCI 0x38: reserved
218 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
219
220 #define CIRRUS_PNPMMIO_SIZE 0x1000
221
222
223 /* I/O and memory hook */
224 #define CIRRUS_HOOK_NOT_HANDLED 0
225 #define CIRRUS_HOOK_HANDLED 1
226
227 #define BLTUNSAFE(s) \
228 ( \
229 ( /* check dst is within bounds */ \
230 (s)->cirrus_blt_height * (s)->cirrus_blt_dstpitch \
231 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
232 (s)->vram_size \
233 ) || \
234 ( /* check src is within bounds */ \
235 (s)->cirrus_blt_height * (s)->cirrus_blt_srcpitch \
236 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
237 (s)->vram_size \
238 ) \
239 )
240
241 struct CirrusVGAState;
242 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
243 uint8_t * dst, const uint8_t * src,
244 int dstpitch, int srcpitch,
245 int bltwidth, int bltheight);
246 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
247 uint8_t *dst, int dst_pitch, int width, int height);
248
249 typedef struct CirrusVGAState {
250 VGA_STATE_COMMON
251
252 int cirrus_linear_io_addr;
253 int cirrus_linear_bitblt_io_addr;
254 int cirrus_mmio_io_addr;
255 unsigned long cirrus_lfb_addr;
256 unsigned long cirrus_lfb_end;
257 uint32_t cirrus_addr_mask;
258 uint32_t linear_mmio_mask;
259 uint8_t cirrus_shadow_gr0;
260 uint8_t cirrus_shadow_gr1;
261 uint8_t cirrus_hidden_dac_lockindex;
262 uint8_t cirrus_hidden_dac_data;
263 uint32_t cirrus_bank_base[2];
264 uint32_t cirrus_bank_limit[2];
265 uint8_t cirrus_hidden_palette[48];
266 uint32_t hw_cursor_x;
267 uint32_t hw_cursor_y;
268 int cirrus_blt_pixelwidth;
269 int cirrus_blt_width;
270 int cirrus_blt_height;
271 int cirrus_blt_dstpitch;
272 int cirrus_blt_srcpitch;
273 uint32_t cirrus_blt_fgcol;
274 uint32_t cirrus_blt_bgcol;
275 uint32_t cirrus_blt_dstaddr;
276 uint32_t cirrus_blt_srcaddr;
277 uint8_t cirrus_blt_mode;
278 uint8_t cirrus_blt_modeext;
279 cirrus_bitblt_rop_t cirrus_rop;
280 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
281 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
282 uint8_t *cirrus_srcptr;
283 uint8_t *cirrus_srcptr_end;
284 uint32_t cirrus_srccounter;
285 /* hwcursor display state */
286 int last_hw_cursor_size;
287 int last_hw_cursor_x;
288 int last_hw_cursor_y;
289 int last_hw_cursor_y_start;
290 int last_hw_cursor_y_end;
291 int real_vram_size; /* XXX: suppress that */
292 CPUWriteMemoryFunc **cirrus_linear_write;
293 } CirrusVGAState;
294
295 typedef struct PCICirrusVGAState {
296 PCIDevice dev;
297 CirrusVGAState cirrus_vga;
298 } PCICirrusVGAState;
299
300 static uint8_t rop_to_index[256];
301
302 /***************************************
303 *
304 * prototypes.
305 *
306 ***************************************/
307
308
309 static void cirrus_bitblt_reset(CirrusVGAState *s);
310 static void cirrus_update_memory_access(CirrusVGAState *s);
311
312 /***************************************
313 *
314 * raster operations
315 *
316 ***************************************/
317
318 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
319 uint8_t *dst,const uint8_t *src,
320 int dstpitch,int srcpitch,
321 int bltwidth,int bltheight)
322 {
323 }
324
325 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
326 uint8_t *dst,
327 int dstpitch, int bltwidth,int bltheight)
328 {
329 }
330
331 #define ROP_NAME 0
332 #define ROP_OP(d, s) d = 0
333 #include "cirrus_vga_rop.h"
334
335 #define ROP_NAME src_and_dst
336 #define ROP_OP(d, s) d = (s) & (d)
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_and_notdst
340 #define ROP_OP(d, s) d = (s) & (~(d))
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME notdst
344 #define ROP_OP(d, s) d = ~(d)
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME src
348 #define ROP_OP(d, s) d = s
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME 1
352 #define ROP_OP(d, s) d = ~0
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME notsrc_and_dst
356 #define ROP_OP(d, s) d = (~(s)) & (d)
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME src_xor_dst
360 #define ROP_OP(d, s) d = (s) ^ (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME src_or_dst
364 #define ROP_OP(d, s) d = (s) | (d)
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME notsrc_or_notdst
368 #define ROP_OP(d, s) d = (~(s)) | (~(d))
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME src_notxor_dst
372 #define ROP_OP(d, s) d = ~((s) ^ (d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME src_or_notdst
376 #define ROP_OP(d, s) d = (s) | (~(d))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME notsrc
380 #define ROP_OP(d, s) d = (~(s))
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc_or_dst
384 #define ROP_OP(d, s) d = (~(s)) | (d)
385 #include "cirrus_vga_rop.h"
386
387 #define ROP_NAME notsrc_and_notdst
388 #define ROP_OP(d, s) d = (~(s)) & (~(d))
389 #include "cirrus_vga_rop.h"
390
391 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
392 cirrus_bitblt_rop_fwd_0,
393 cirrus_bitblt_rop_fwd_src_and_dst,
394 cirrus_bitblt_rop_nop,
395 cirrus_bitblt_rop_fwd_src_and_notdst,
396 cirrus_bitblt_rop_fwd_notdst,
397 cirrus_bitblt_rop_fwd_src,
398 cirrus_bitblt_rop_fwd_1,
399 cirrus_bitblt_rop_fwd_notsrc_and_dst,
400 cirrus_bitblt_rop_fwd_src_xor_dst,
401 cirrus_bitblt_rop_fwd_src_or_dst,
402 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
403 cirrus_bitblt_rop_fwd_src_notxor_dst,
404 cirrus_bitblt_rop_fwd_src_or_notdst,
405 cirrus_bitblt_rop_fwd_notsrc,
406 cirrus_bitblt_rop_fwd_notsrc_or_dst,
407 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
408 };
409
410 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
411 cirrus_bitblt_rop_bkwd_0,
412 cirrus_bitblt_rop_bkwd_src_and_dst,
413 cirrus_bitblt_rop_nop,
414 cirrus_bitblt_rop_bkwd_src_and_notdst,
415 cirrus_bitblt_rop_bkwd_notdst,
416 cirrus_bitblt_rop_bkwd_src,
417 cirrus_bitblt_rop_bkwd_1,
418 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
419 cirrus_bitblt_rop_bkwd_src_xor_dst,
420 cirrus_bitblt_rop_bkwd_src_or_dst,
421 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
422 cirrus_bitblt_rop_bkwd_src_notxor_dst,
423 cirrus_bitblt_rop_bkwd_src_or_notdst,
424 cirrus_bitblt_rop_bkwd_notsrc,
425 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
426 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
427 };
428
429 #define TRANSP_ROP(name) {\
430 name ## _8,\
431 name ## _16,\
432 }
433 #define TRANSP_NOP(func) {\
434 func,\
435 func,\
436 }
437
438 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
441 TRANSP_NOP(cirrus_bitblt_rop_nop),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
455 };
456
457 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
460 TRANSP_NOP(cirrus_bitblt_rop_nop),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
474 };
475
476 #define ROP2(name) {\
477 name ## _8,\
478 name ## _16,\
479 name ## _24,\
480 name ## _32,\
481 }
482
483 #define ROP_NOP2(func) {\
484 func,\
485 func,\
486 func,\
487 func,\
488 }
489
490 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
491 ROP2(cirrus_patternfill_0),
492 ROP2(cirrus_patternfill_src_and_dst),
493 ROP_NOP2(cirrus_bitblt_rop_nop),
494 ROP2(cirrus_patternfill_src_and_notdst),
495 ROP2(cirrus_patternfill_notdst),
496 ROP2(cirrus_patternfill_src),
497 ROP2(cirrus_patternfill_1),
498 ROP2(cirrus_patternfill_notsrc_and_dst),
499 ROP2(cirrus_patternfill_src_xor_dst),
500 ROP2(cirrus_patternfill_src_or_dst),
501 ROP2(cirrus_patternfill_notsrc_or_notdst),
502 ROP2(cirrus_patternfill_src_notxor_dst),
503 ROP2(cirrus_patternfill_src_or_notdst),
504 ROP2(cirrus_patternfill_notsrc),
505 ROP2(cirrus_patternfill_notsrc_or_dst),
506 ROP2(cirrus_patternfill_notsrc_and_notdst),
507 };
508
509 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
510 ROP2(cirrus_colorexpand_transp_0),
511 ROP2(cirrus_colorexpand_transp_src_and_dst),
512 ROP_NOP2(cirrus_bitblt_rop_nop),
513 ROP2(cirrus_colorexpand_transp_src_and_notdst),
514 ROP2(cirrus_colorexpand_transp_notdst),
515 ROP2(cirrus_colorexpand_transp_src),
516 ROP2(cirrus_colorexpand_transp_1),
517 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
518 ROP2(cirrus_colorexpand_transp_src_xor_dst),
519 ROP2(cirrus_colorexpand_transp_src_or_dst),
520 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
521 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
522 ROP2(cirrus_colorexpand_transp_src_or_notdst),
523 ROP2(cirrus_colorexpand_transp_notsrc),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
525 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
526 };
527
528 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
529 ROP2(cirrus_colorexpand_0),
530 ROP2(cirrus_colorexpand_src_and_dst),
531 ROP_NOP2(cirrus_bitblt_rop_nop),
532 ROP2(cirrus_colorexpand_src_and_notdst),
533 ROP2(cirrus_colorexpand_notdst),
534 ROP2(cirrus_colorexpand_src),
535 ROP2(cirrus_colorexpand_1),
536 ROP2(cirrus_colorexpand_notsrc_and_dst),
537 ROP2(cirrus_colorexpand_src_xor_dst),
538 ROP2(cirrus_colorexpand_src_or_dst),
539 ROP2(cirrus_colorexpand_notsrc_or_notdst),
540 ROP2(cirrus_colorexpand_src_notxor_dst),
541 ROP2(cirrus_colorexpand_src_or_notdst),
542 ROP2(cirrus_colorexpand_notsrc),
543 ROP2(cirrus_colorexpand_notsrc_or_dst),
544 ROP2(cirrus_colorexpand_notsrc_and_notdst),
545 };
546
547 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
548 ROP2(cirrus_colorexpand_pattern_transp_0),
549 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
550 ROP_NOP2(cirrus_bitblt_rop_nop),
551 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_src),
554 ROP2(cirrus_colorexpand_pattern_transp_1),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
559 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
560 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
563 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
564 };
565
566 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
567 ROP2(cirrus_colorexpand_pattern_0),
568 ROP2(cirrus_colorexpand_pattern_src_and_dst),
569 ROP_NOP2(cirrus_bitblt_rop_nop),
570 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
571 ROP2(cirrus_colorexpand_pattern_notdst),
572 ROP2(cirrus_colorexpand_pattern_src),
573 ROP2(cirrus_colorexpand_pattern_1),
574 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
575 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
576 ROP2(cirrus_colorexpand_pattern_src_or_dst),
577 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
578 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
579 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
580 ROP2(cirrus_colorexpand_pattern_notsrc),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
582 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
583 };
584
585 static const cirrus_fill_t cirrus_fill[16][4] = {
586 ROP2(cirrus_fill_0),
587 ROP2(cirrus_fill_src_and_dst),
588 ROP_NOP2(cirrus_bitblt_fill_nop),
589 ROP2(cirrus_fill_src_and_notdst),
590 ROP2(cirrus_fill_notdst),
591 ROP2(cirrus_fill_src),
592 ROP2(cirrus_fill_1),
593 ROP2(cirrus_fill_notsrc_and_dst),
594 ROP2(cirrus_fill_src_xor_dst),
595 ROP2(cirrus_fill_src_or_dst),
596 ROP2(cirrus_fill_notsrc_or_notdst),
597 ROP2(cirrus_fill_src_notxor_dst),
598 ROP2(cirrus_fill_src_or_notdst),
599 ROP2(cirrus_fill_notsrc),
600 ROP2(cirrus_fill_notsrc_or_dst),
601 ROP2(cirrus_fill_notsrc_and_notdst),
602 };
603
604 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
605 {
606 unsigned int color;
607 switch (s->cirrus_blt_pixelwidth) {
608 case 1:
609 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
610 break;
611 case 2:
612 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
613 s->cirrus_blt_fgcol = le16_to_cpu(color);
614 break;
615 case 3:
616 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
617 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
618 break;
619 default:
620 case 4:
621 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
622 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
623 s->cirrus_blt_fgcol = le32_to_cpu(color);
624 break;
625 }
626 }
627
628 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
629 {
630 unsigned int color;
631 switch (s->cirrus_blt_pixelwidth) {
632 case 1:
633 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
634 break;
635 case 2:
636 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
637 s->cirrus_blt_bgcol = le16_to_cpu(color);
638 break;
639 case 3:
640 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
641 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
642 break;
643 default:
644 case 4:
645 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
646 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
647 s->cirrus_blt_bgcol = le32_to_cpu(color);
648 break;
649 }
650 }
651
652 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
653 int off_pitch, int bytesperline,
654 int lines)
655 {
656 int y;
657 int off_cur;
658 int off_cur_end;
659
660 for (y = 0; y < lines; y++) {
661 off_cur = off_begin;
662 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
663 off_cur &= TARGET_PAGE_MASK;
664 while (off_cur < off_cur_end) {
665 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
666 off_cur += TARGET_PAGE_SIZE;
667 }
668 off_begin += off_pitch;
669 }
670 }
671
672 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
673 const uint8_t * src)
674 {
675 uint8_t *dst;
676
677 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
678
679 if (BLTUNSAFE(s))
680 return 0;
681
682 (*s->cirrus_rop) (s, dst, src,
683 s->cirrus_blt_dstpitch, 0,
684 s->cirrus_blt_width, s->cirrus_blt_height);
685 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
686 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
687 s->cirrus_blt_height);
688 return 1;
689 }
690
691 /* fill */
692
693 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
694 {
695 cirrus_fill_t rop_func;
696
697 if (BLTUNSAFE(s))
698 return 0;
699 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
700 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
701 s->cirrus_blt_dstpitch,
702 s->cirrus_blt_width, s->cirrus_blt_height);
703 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
704 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
705 s->cirrus_blt_height);
706 cirrus_bitblt_reset(s);
707 return 1;
708 }
709
710 /***************************************
711 *
712 * bitblt (video-to-video)
713 *
714 ***************************************/
715
716 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
717 {
718 return cirrus_bitblt_common_patterncopy(s,
719 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
720 s->cirrus_addr_mask));
721 }
722
723 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
724 {
725 int sx, sy;
726 int dx, dy;
727 int width, height;
728 int depth;
729 int notify = 0;
730
731 depth = s->get_bpp((VGAState *)s) / 8;
732 s->get_resolution((VGAState *)s, &width, &height);
733
734 /* extra x, y */
735 sx = (src % (width * depth)) / depth;
736 sy = (src / (width * depth));
737 dx = (dst % (width *depth)) / depth;
738 dy = (dst / (width * depth));
739
740 /* normalize width */
741 w /= depth;
742
743 /* if we're doing a backward copy, we have to adjust
744 our x/y to be the upper left corner (instead of the lower
745 right corner) */
746 if (s->cirrus_blt_dstpitch < 0) {
747 sx -= (s->cirrus_blt_width / depth) - 1;
748 dx -= (s->cirrus_blt_width / depth) - 1;
749 sy -= s->cirrus_blt_height - 1;
750 dy -= s->cirrus_blt_height - 1;
751 }
752
753 /* are we in the visible portion of memory? */
754 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
755 (sx + w) <= width && (sy + h) <= height &&
756 (dx + w) <= width && (dy + h) <= height) {
757 notify = 1;
758 }
759
760 /* make to sure only copy if it's a plain copy ROP */
761 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
762 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
763 notify = 0;
764
765 /* we have to flush all pending changes so that the copy
766 is generated at the appropriate moment in time */
767 if (notify)
768 vga_hw_update();
769
770 (*s->cirrus_rop) (s, s->vram_ptr +
771 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
772 s->vram_ptr +
773 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
774 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
775 s->cirrus_blt_width, s->cirrus_blt_height);
776
777 if (notify)
778 qemu_console_copy(s->console,
779 sx, sy, dx, dy,
780 s->cirrus_blt_width / depth,
781 s->cirrus_blt_height);
782
783 /* we don't have to notify the display that this portion has
784 changed since qemu_console_copy implies this */
785
786 if (!notify)
787 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
788 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
789 s->cirrus_blt_height);
790 }
791
792 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
793 {
794 if (BLTUNSAFE(s))
795 return 0;
796
797 if (s->ds->dpy_copy) {
798 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
799 s->cirrus_blt_srcaddr - s->start_addr,
800 s->cirrus_blt_width, s->cirrus_blt_height);
801 } else {
802 (*s->cirrus_rop) (s, s->vram_ptr +
803 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
804 s->vram_ptr +
805 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
806 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
807 s->cirrus_blt_width, s->cirrus_blt_height);
808
809 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
810 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
811 s->cirrus_blt_height);
812 }
813
814 return 1;
815 }
816
817 /***************************************
818 *
819 * bitblt (cpu-to-video)
820 *
821 ***************************************/
822
823 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
824 {
825 int copy_count;
826 uint8_t *end_ptr;
827
828 if (s->cirrus_srccounter > 0) {
829 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
830 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
831 the_end:
832 s->cirrus_srccounter = 0;
833 cirrus_bitblt_reset(s);
834 } else {
835 /* at least one scan line */
836 do {
837 (*s->cirrus_rop)(s, s->vram_ptr +
838 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
839 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
840 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
841 s->cirrus_blt_width, 1);
842 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
843 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
844 if (s->cirrus_srccounter <= 0)
845 goto the_end;
846 /* more bytes than needed can be transfered because of
847 word alignment, so we keep them for the next line */
848 /* XXX: keep alignment to speed up transfer */
849 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
850 copy_count = s->cirrus_srcptr_end - end_ptr;
851 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
852 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
853 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
854 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
855 }
856 }
857 }
858
859 /***************************************
860 *
861 * bitblt wrapper
862 *
863 ***************************************/
864
865 static void cirrus_bitblt_reset(CirrusVGAState * s)
866 {
867 s->gr[0x31] &=
868 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
869 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
870 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
871 s->cirrus_srccounter = 0;
872 cirrus_update_memory_access(s);
873 }
874
875 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
876 {
877 int w;
878
879 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
880 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
881 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
882
883 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
884 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
885 s->cirrus_blt_srcpitch = 8;
886 } else {
887 /* XXX: check for 24 bpp */
888 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
889 }
890 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
891 } else {
892 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
893 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
894 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
895 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
896 else
897 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
898 } else {
899 /* always align input size to 32 bits */
900 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
901 }
902 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
903 }
904 s->cirrus_srcptr = s->cirrus_bltbuf;
905 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
906 cirrus_update_memory_access(s);
907 return 1;
908 }
909
910 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
911 {
912 /* XXX */
913 #ifdef DEBUG_BITBLT
914 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
915 #endif
916 return 0;
917 }
918
919 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
920 {
921 int ret;
922
923 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
924 ret = cirrus_bitblt_videotovideo_patterncopy(s);
925 } else {
926 ret = cirrus_bitblt_videotovideo_copy(s);
927 }
928 if (ret)
929 cirrus_bitblt_reset(s);
930 return ret;
931 }
932
933 static void cirrus_bitblt_start(CirrusVGAState * s)
934 {
935 uint8_t blt_rop;
936
937 s->gr[0x31] |= CIRRUS_BLT_BUSY;
938
939 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
940 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
941 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
942 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
943 s->cirrus_blt_dstaddr =
944 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
945 s->cirrus_blt_srcaddr =
946 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
947 s->cirrus_blt_mode = s->gr[0x30];
948 s->cirrus_blt_modeext = s->gr[0x33];
949 blt_rop = s->gr[0x32];
950
951 #ifdef DEBUG_BITBLT
952 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
953 blt_rop,
954 s->cirrus_blt_mode,
955 s->cirrus_blt_modeext,
956 s->cirrus_blt_width,
957 s->cirrus_blt_height,
958 s->cirrus_blt_dstpitch,
959 s->cirrus_blt_srcpitch,
960 s->cirrus_blt_dstaddr,
961 s->cirrus_blt_srcaddr,
962 s->gr[0x2f]);
963 #endif
964
965 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
966 case CIRRUS_BLTMODE_PIXELWIDTH8:
967 s->cirrus_blt_pixelwidth = 1;
968 break;
969 case CIRRUS_BLTMODE_PIXELWIDTH16:
970 s->cirrus_blt_pixelwidth = 2;
971 break;
972 case CIRRUS_BLTMODE_PIXELWIDTH24:
973 s->cirrus_blt_pixelwidth = 3;
974 break;
975 case CIRRUS_BLTMODE_PIXELWIDTH32:
976 s->cirrus_blt_pixelwidth = 4;
977 break;
978 default:
979 #ifdef DEBUG_BITBLT
980 printf("cirrus: bitblt - pixel width is unknown\n");
981 #endif
982 goto bitblt_ignore;
983 }
984 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
985
986 if ((s->
987 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
988 CIRRUS_BLTMODE_MEMSYSDEST))
989 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
990 #ifdef DEBUG_BITBLT
991 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
992 #endif
993 goto bitblt_ignore;
994 }
995
996 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
997 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
998 CIRRUS_BLTMODE_TRANSPARENTCOMP |
999 CIRRUS_BLTMODE_PATTERNCOPY |
1000 CIRRUS_BLTMODE_COLOREXPAND)) ==
1001 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1002 cirrus_bitblt_fgcol(s);
1003 cirrus_bitblt_solidfill(s, blt_rop);
1004 } else {
1005 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1006 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1007 CIRRUS_BLTMODE_COLOREXPAND) {
1008
1009 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1010 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1011 cirrus_bitblt_bgcol(s);
1012 else
1013 cirrus_bitblt_fgcol(s);
1014 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1015 } else {
1016 cirrus_bitblt_fgcol(s);
1017 cirrus_bitblt_bgcol(s);
1018 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1019 }
1020 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1021 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1022 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1023 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1024 cirrus_bitblt_bgcol(s);
1025 else
1026 cirrus_bitblt_fgcol(s);
1027 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 } else {
1029 cirrus_bitblt_fgcol(s);
1030 cirrus_bitblt_bgcol(s);
1031 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1032 }
1033 } else {
1034 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1035 }
1036 } else {
1037 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1038 if (s->cirrus_blt_pixelwidth > 2) {
1039 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1040 goto bitblt_ignore;
1041 }
1042 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1043 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1044 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1045 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1046 } else {
1047 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1048 }
1049 } else {
1050 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1051 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1052 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1053 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1054 } else {
1055 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1056 }
1057 }
1058 }
1059 // setup bitblt engine.
1060 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1061 if (!cirrus_bitblt_cputovideo(s))
1062 goto bitblt_ignore;
1063 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1064 if (!cirrus_bitblt_videotocpu(s))
1065 goto bitblt_ignore;
1066 } else {
1067 if (!cirrus_bitblt_videotovideo(s))
1068 goto bitblt_ignore;
1069 }
1070 }
1071 return;
1072 bitblt_ignore:;
1073 cirrus_bitblt_reset(s);
1074 }
1075
1076 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1077 {
1078 unsigned old_value;
1079
1080 old_value = s->gr[0x31];
1081 s->gr[0x31] = reg_value;
1082
1083 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1084 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1085 cirrus_bitblt_reset(s);
1086 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1087 ((reg_value & CIRRUS_BLT_START) != 0)) {
1088 cirrus_bitblt_start(s);
1089 }
1090 }
1091
1092
1093 /***************************************
1094 *
1095 * basic parameters
1096 *
1097 ***************************************/
1098
1099 static void cirrus_get_offsets(VGAState *s1,
1100 uint32_t *pline_offset,
1101 uint32_t *pstart_addr,
1102 uint32_t *pline_compare)
1103 {
1104 CirrusVGAState * s = (CirrusVGAState *)s1;
1105 uint32_t start_addr, line_offset, line_compare;
1106
1107 line_offset = s->cr[0x13]
1108 | ((s->cr[0x1b] & 0x10) << 4);
1109 line_offset <<= 3;
1110 *pline_offset = line_offset;
1111
1112 start_addr = (s->cr[0x0c] << 8)
1113 | s->cr[0x0d]
1114 | ((s->cr[0x1b] & 0x01) << 16)
1115 | ((s->cr[0x1b] & 0x0c) << 15)
1116 | ((s->cr[0x1d] & 0x80) << 12);
1117 *pstart_addr = start_addr;
1118
1119 line_compare = s->cr[0x18] |
1120 ((s->cr[0x07] & 0x10) << 4) |
1121 ((s->cr[0x09] & 0x40) << 3);
1122 *pline_compare = line_compare;
1123 }
1124
1125 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1126 {
1127 uint32_t ret = 16;
1128
1129 switch (s->cirrus_hidden_dac_data & 0xf) {
1130 case 0:
1131 ret = 15;
1132 break; /* Sierra HiColor */
1133 case 1:
1134 ret = 16;
1135 break; /* XGA HiColor */
1136 default:
1137 #ifdef DEBUG_CIRRUS
1138 printf("cirrus: invalid DAC value %x in 16bpp\n",
1139 (s->cirrus_hidden_dac_data & 0xf));
1140 #endif
1141 ret = 15; /* XXX */
1142 break;
1143 }
1144 return ret;
1145 }
1146
1147 static int cirrus_get_bpp(VGAState *s1)
1148 {
1149 CirrusVGAState * s = (CirrusVGAState *)s1;
1150 uint32_t ret = 8;
1151
1152 if ((s->sr[0x07] & 0x01) != 0) {
1153 /* Cirrus SVGA */
1154 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1155 case CIRRUS_SR7_BPP_8:
1156 ret = 8;
1157 break;
1158 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1159 ret = cirrus_get_bpp16_depth(s);
1160 break;
1161 case CIRRUS_SR7_BPP_24:
1162 ret = 24;
1163 break;
1164 case CIRRUS_SR7_BPP_16:
1165 ret = cirrus_get_bpp16_depth(s);
1166 break;
1167 case CIRRUS_SR7_BPP_32:
1168 ret = 32;
1169 break;
1170 default:
1171 #ifdef DEBUG_CIRRUS
1172 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1173 #endif
1174 ret = 8;
1175 break;
1176 }
1177 } else {
1178 /* VGA */
1179 ret = 0;
1180 }
1181
1182 return ret;
1183 }
1184
1185 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1186 {
1187 int width, height;
1188
1189 width = (s->cr[0x01] + 1) * 8;
1190 height = s->cr[0x12] |
1191 ((s->cr[0x07] & 0x02) << 7) |
1192 ((s->cr[0x07] & 0x40) << 3);
1193 height = (height + 1);
1194 /* interlace support */
1195 if (s->cr[0x1a] & 0x01)
1196 height = height * 2;
1197 *pwidth = width;
1198 *pheight = height;
1199 }
1200
1201 /***************************************
1202 *
1203 * bank memory
1204 *
1205 ***************************************/
1206
1207 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1208 {
1209 unsigned offset;
1210 unsigned limit;
1211
1212 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1213 offset = s->gr[0x09 + bank_index];
1214 else /* single bank */
1215 offset = s->gr[0x09];
1216
1217 if ((s->gr[0x0b] & 0x20) != 0)
1218 offset <<= 14;
1219 else
1220 offset <<= 12;
1221
1222 if (s->real_vram_size <= offset)
1223 limit = 0;
1224 else
1225 limit = s->real_vram_size - offset;
1226
1227 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1228 if (limit > 0x8000) {
1229 offset += 0x8000;
1230 limit -= 0x8000;
1231 } else {
1232 limit = 0;
1233 }
1234 }
1235
1236 if (limit > 0) {
1237 s->cirrus_bank_base[bank_index] = offset;
1238 s->cirrus_bank_limit[bank_index] = limit;
1239 } else {
1240 s->cirrus_bank_base[bank_index] = 0;
1241 s->cirrus_bank_limit[bank_index] = 0;
1242 }
1243 }
1244
1245 /***************************************
1246 *
1247 * I/O access between 0x3c4-0x3c5
1248 *
1249 ***************************************/
1250
1251 static int
1252 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1253 {
1254 switch (reg_index) {
1255 case 0x00: // Standard VGA
1256 case 0x01: // Standard VGA
1257 case 0x02: // Standard VGA
1258 case 0x03: // Standard VGA
1259 case 0x04: // Standard VGA
1260 return CIRRUS_HOOK_NOT_HANDLED;
1261 case 0x06: // Unlock Cirrus extensions
1262 *reg_value = s->sr[reg_index];
1263 break;
1264 case 0x10:
1265 case 0x30:
1266 case 0x50:
1267 case 0x70: // Graphics Cursor X
1268 case 0x90:
1269 case 0xb0:
1270 case 0xd0:
1271 case 0xf0: // Graphics Cursor X
1272 *reg_value = s->sr[0x10];
1273 break;
1274 case 0x11:
1275 case 0x31:
1276 case 0x51:
1277 case 0x71: // Graphics Cursor Y
1278 case 0x91:
1279 case 0xb1:
1280 case 0xd1:
1281 case 0xf1: // Graphics Cursor Y
1282 *reg_value = s->sr[0x11];
1283 break;
1284 case 0x05: // ???
1285 case 0x07: // Extended Sequencer Mode
1286 case 0x08: // EEPROM Control
1287 case 0x09: // Scratch Register 0
1288 case 0x0a: // Scratch Register 1
1289 case 0x0b: // VCLK 0
1290 case 0x0c: // VCLK 1
1291 case 0x0d: // VCLK 2
1292 case 0x0e: // VCLK 3
1293 case 0x0f: // DRAM Control
1294 case 0x12: // Graphics Cursor Attribute
1295 case 0x13: // Graphics Cursor Pattern Address
1296 case 0x14: // Scratch Register 2
1297 case 0x15: // Scratch Register 3
1298 case 0x16: // Performance Tuning Register
1299 case 0x17: // Configuration Readback and Extended Control
1300 case 0x18: // Signature Generator Control
1301 case 0x19: // Signal Generator Result
1302 case 0x1a: // Signal Generator Result
1303 case 0x1b: // VCLK 0 Denominator & Post
1304 case 0x1c: // VCLK 1 Denominator & Post
1305 case 0x1d: // VCLK 2 Denominator & Post
1306 case 0x1e: // VCLK 3 Denominator & Post
1307 case 0x1f: // BIOS Write Enable and MCLK select
1308 #ifdef DEBUG_CIRRUS
1309 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1310 #endif
1311 *reg_value = s->sr[reg_index];
1312 break;
1313 default:
1314 #ifdef DEBUG_CIRRUS
1315 printf("cirrus: inport sr_index %02x\n", reg_index);
1316 #endif
1317 *reg_value = 0xff;
1318 break;
1319 }
1320
1321 return CIRRUS_HOOK_HANDLED;
1322 }
1323
1324 static int
1325 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1326 {
1327 switch (reg_index) {
1328 case 0x00: // Standard VGA
1329 case 0x01: // Standard VGA
1330 case 0x02: // Standard VGA
1331 case 0x03: // Standard VGA
1332 case 0x04: // Standard VGA
1333 return CIRRUS_HOOK_NOT_HANDLED;
1334 case 0x06: // Unlock Cirrus extensions
1335 reg_value &= 0x17;
1336 if (reg_value == 0x12) {
1337 s->sr[reg_index] = 0x12;
1338 } else {
1339 s->sr[reg_index] = 0x0f;
1340 }
1341 break;
1342 case 0x10:
1343 case 0x30:
1344 case 0x50:
1345 case 0x70: // Graphics Cursor X
1346 case 0x90:
1347 case 0xb0:
1348 case 0xd0:
1349 case 0xf0: // Graphics Cursor X
1350 s->sr[0x10] = reg_value;
1351 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1352 break;
1353 case 0x11:
1354 case 0x31:
1355 case 0x51:
1356 case 0x71: // Graphics Cursor Y
1357 case 0x91:
1358 case 0xb1:
1359 case 0xd1:
1360 case 0xf1: // Graphics Cursor Y
1361 s->sr[0x11] = reg_value;
1362 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1363 break;
1364 case 0x07: // Extended Sequencer Mode
1365 case 0x08: // EEPROM Control
1366 case 0x09: // Scratch Register 0
1367 case 0x0a: // Scratch Register 1
1368 case 0x0b: // VCLK 0
1369 case 0x0c: // VCLK 1
1370 case 0x0d: // VCLK 2
1371 case 0x0e: // VCLK 3
1372 case 0x0f: // DRAM Control
1373 case 0x12: // Graphics Cursor Attribute
1374 case 0x13: // Graphics Cursor Pattern Address
1375 case 0x14: // Scratch Register 2
1376 case 0x15: // Scratch Register 3
1377 case 0x16: // Performance Tuning Register
1378 case 0x18: // Signature Generator Control
1379 case 0x19: // Signature Generator Result
1380 case 0x1a: // Signature Generator Result
1381 case 0x1b: // VCLK 0 Denominator & Post
1382 case 0x1c: // VCLK 1 Denominator & Post
1383 case 0x1d: // VCLK 2 Denominator & Post
1384 case 0x1e: // VCLK 3 Denominator & Post
1385 case 0x1f: // BIOS Write Enable and MCLK select
1386 s->sr[reg_index] = reg_value;
1387 #ifdef DEBUG_CIRRUS
1388 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1389 reg_index, reg_value);
1390 #endif
1391 if (reg_index == 0x07)
1392 cirrus_update_memory_access(s);
1393 break;
1394 case 0x17: // Configuration Readback and Extended Control
1395 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1396 cirrus_update_memory_access(s);
1397 break;
1398 default:
1399 #ifdef DEBUG_CIRRUS
1400 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1401 reg_value);
1402 #endif
1403 break;
1404 }
1405
1406 return CIRRUS_HOOK_HANDLED;
1407 }
1408
1409 /***************************************
1410 *
1411 * I/O access at 0x3c6
1412 *
1413 ***************************************/
1414
1415 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1416 {
1417 *reg_value = 0xff;
1418 if (++s->cirrus_hidden_dac_lockindex == 5) {
1419 *reg_value = s->cirrus_hidden_dac_data;
1420 s->cirrus_hidden_dac_lockindex = 0;
1421 }
1422 }
1423
1424 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1425 {
1426 if (s->cirrus_hidden_dac_lockindex == 4) {
1427 s->cirrus_hidden_dac_data = reg_value;
1428 #if defined(DEBUG_CIRRUS)
1429 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1430 #endif
1431 }
1432 s->cirrus_hidden_dac_lockindex = 0;
1433 }
1434
1435 /***************************************
1436 *
1437 * I/O access at 0x3c9
1438 *
1439 ***************************************/
1440
1441 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1442 {
1443 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1444 return CIRRUS_HOOK_NOT_HANDLED;
1445 *reg_value =
1446 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1447 s->dac_sub_index];
1448 if (++s->dac_sub_index == 3) {
1449 s->dac_sub_index = 0;
1450 s->dac_read_index++;
1451 }
1452 return CIRRUS_HOOK_HANDLED;
1453 }
1454
1455 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1456 {
1457 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1458 return CIRRUS_HOOK_NOT_HANDLED;
1459 s->dac_cache[s->dac_sub_index] = reg_value;
1460 if (++s->dac_sub_index == 3) {
1461 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1462 s->dac_cache, 3);
1463 /* XXX update cursor */
1464 s->dac_sub_index = 0;
1465 s->dac_write_index++;
1466 }
1467 return CIRRUS_HOOK_HANDLED;
1468 }
1469
1470 /***************************************
1471 *
1472 * I/O access between 0x3ce-0x3cf
1473 *
1474 ***************************************/
1475
1476 static int
1477 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1478 {
1479 switch (reg_index) {
1480 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1481 *reg_value = s->cirrus_shadow_gr0;
1482 return CIRRUS_HOOK_HANDLED;
1483 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1484 *reg_value = s->cirrus_shadow_gr1;
1485 return CIRRUS_HOOK_HANDLED;
1486 case 0x02: // Standard VGA
1487 case 0x03: // Standard VGA
1488 case 0x04: // Standard VGA
1489 case 0x06: // Standard VGA
1490 case 0x07: // Standard VGA
1491 case 0x08: // Standard VGA
1492 return CIRRUS_HOOK_NOT_HANDLED;
1493 case 0x05: // Standard VGA, Cirrus extended mode
1494 default:
1495 break;
1496 }
1497
1498 if (reg_index < 0x3a) {
1499 *reg_value = s->gr[reg_index];
1500 } else {
1501 #ifdef DEBUG_CIRRUS
1502 printf("cirrus: inport gr_index %02x\n", reg_index);
1503 #endif
1504 *reg_value = 0xff;
1505 }
1506
1507 return CIRRUS_HOOK_HANDLED;
1508 }
1509
1510 static int
1511 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1512 {
1513 #if defined(DEBUG_BITBLT) && 0
1514 printf("gr%02x: %02x\n", reg_index, reg_value);
1515 #endif
1516 switch (reg_index) {
1517 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1518 s->cirrus_shadow_gr0 = reg_value;
1519 return CIRRUS_HOOK_NOT_HANDLED;
1520 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1521 s->cirrus_shadow_gr1 = reg_value;
1522 return CIRRUS_HOOK_NOT_HANDLED;
1523 case 0x02: // Standard VGA
1524 case 0x03: // Standard VGA
1525 case 0x04: // Standard VGA
1526 case 0x06: // Standard VGA
1527 case 0x07: // Standard VGA
1528 case 0x08: // Standard VGA
1529 return CIRRUS_HOOK_NOT_HANDLED;
1530 case 0x05: // Standard VGA, Cirrus extended mode
1531 s->gr[reg_index] = reg_value & 0x7f;
1532 cirrus_update_memory_access(s);
1533 break;
1534 case 0x09: // bank offset #0
1535 case 0x0A: // bank offset #1
1536 s->gr[reg_index] = reg_value;
1537 cirrus_update_bank_ptr(s, 0);
1538 cirrus_update_bank_ptr(s, 1);
1539 cirrus_update_memory_access(s);
1540 break;
1541 case 0x0B:
1542 s->gr[reg_index] = reg_value;
1543 cirrus_update_bank_ptr(s, 0);
1544 cirrus_update_bank_ptr(s, 1);
1545 cirrus_update_memory_access(s);
1546 break;
1547 case 0x10: // BGCOLOR 0x0000ff00
1548 case 0x11: // FGCOLOR 0x0000ff00
1549 case 0x12: // BGCOLOR 0x00ff0000
1550 case 0x13: // FGCOLOR 0x00ff0000
1551 case 0x14: // BGCOLOR 0xff000000
1552 case 0x15: // FGCOLOR 0xff000000
1553 case 0x20: // BLT WIDTH 0x0000ff
1554 case 0x22: // BLT HEIGHT 0x0000ff
1555 case 0x24: // BLT DEST PITCH 0x0000ff
1556 case 0x26: // BLT SRC PITCH 0x0000ff
1557 case 0x28: // BLT DEST ADDR 0x0000ff
1558 case 0x29: // BLT DEST ADDR 0x00ff00
1559 case 0x2c: // BLT SRC ADDR 0x0000ff
1560 case 0x2d: // BLT SRC ADDR 0x00ff00
1561 case 0x2f: // BLT WRITEMASK
1562 case 0x30: // BLT MODE
1563 case 0x32: // RASTER OP
1564 case 0x33: // BLT MODEEXT
1565 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1566 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1567 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1568 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1569 s->gr[reg_index] = reg_value;
1570 break;
1571 case 0x21: // BLT WIDTH 0x001f00
1572 case 0x23: // BLT HEIGHT 0x001f00
1573 case 0x25: // BLT DEST PITCH 0x001f00
1574 case 0x27: // BLT SRC PITCH 0x001f00
1575 s->gr[reg_index] = reg_value & 0x1f;
1576 break;
1577 case 0x2a: // BLT DEST ADDR 0x3f0000
1578 s->gr[reg_index] = reg_value & 0x3f;
1579 /* if auto start mode, starts bit blt now */
1580 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1581 cirrus_bitblt_start(s);
1582 }
1583 break;
1584 case 0x2e: // BLT SRC ADDR 0x3f0000
1585 s->gr[reg_index] = reg_value & 0x3f;
1586 break;
1587 case 0x31: // BLT STATUS/START
1588 cirrus_write_bitblt(s, reg_value);
1589 break;
1590 default:
1591 #ifdef DEBUG_CIRRUS
1592 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1593 reg_value);
1594 #endif
1595 break;
1596 }
1597
1598 return CIRRUS_HOOK_HANDLED;
1599 }
1600
1601 /***************************************
1602 *
1603 * I/O access between 0x3d4-0x3d5
1604 *
1605 ***************************************/
1606
1607 static int
1608 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1609 {
1610 switch (reg_index) {
1611 case 0x00: // Standard VGA
1612 case 0x01: // Standard VGA
1613 case 0x02: // Standard VGA
1614 case 0x03: // Standard VGA
1615 case 0x04: // Standard VGA
1616 case 0x05: // Standard VGA
1617 case 0x06: // Standard VGA
1618 case 0x07: // Standard VGA
1619 case 0x08: // Standard VGA
1620 case 0x09: // Standard VGA
1621 case 0x0a: // Standard VGA
1622 case 0x0b: // Standard VGA
1623 case 0x0c: // Standard VGA
1624 case 0x0d: // Standard VGA
1625 case 0x0e: // Standard VGA
1626 case 0x0f: // Standard VGA
1627 case 0x10: // Standard VGA
1628 case 0x11: // Standard VGA
1629 case 0x12: // Standard VGA
1630 case 0x13: // Standard VGA
1631 case 0x14: // Standard VGA
1632 case 0x15: // Standard VGA
1633 case 0x16: // Standard VGA
1634 case 0x17: // Standard VGA
1635 case 0x18: // Standard VGA
1636 return CIRRUS_HOOK_NOT_HANDLED;
1637 case 0x24: // Attribute Controller Toggle Readback (R)
1638 *reg_value = (s->ar_flip_flop << 7);
1639 break;
1640 case 0x19: // Interlace End
1641 case 0x1a: // Miscellaneous Control
1642 case 0x1b: // Extended Display Control
1643 case 0x1c: // Sync Adjust and Genlock
1644 case 0x1d: // Overlay Extended Control
1645 case 0x22: // Graphics Data Latches Readback (R)
1646 case 0x25: // Part Status
1647 case 0x27: // Part ID (R)
1648 *reg_value = s->cr[reg_index];
1649 break;
1650 case 0x26: // Attribute Controller Index Readback (R)
1651 *reg_value = s->ar_index & 0x3f;
1652 break;
1653 default:
1654 #ifdef DEBUG_CIRRUS
1655 printf("cirrus: inport cr_index %02x\n", reg_index);
1656 *reg_value = 0xff;
1657 #endif
1658 break;
1659 }
1660
1661 return CIRRUS_HOOK_HANDLED;
1662 }
1663
1664 static int
1665 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1666 {
1667 switch (reg_index) {
1668 case 0x00: // Standard VGA
1669 case 0x01: // Standard VGA
1670 case 0x02: // Standard VGA
1671 case 0x03: // Standard VGA
1672 case 0x04: // Standard VGA
1673 case 0x05: // Standard VGA
1674 case 0x06: // Standard VGA
1675 case 0x07: // Standard VGA
1676 case 0x08: // Standard VGA
1677 case 0x09: // Standard VGA
1678 case 0x0a: // Standard VGA
1679 case 0x0b: // Standard VGA
1680 case 0x0c: // Standard VGA
1681 case 0x0d: // Standard VGA
1682 case 0x0e: // Standard VGA
1683 case 0x0f: // Standard VGA
1684 case 0x10: // Standard VGA
1685 case 0x11: // Standard VGA
1686 case 0x12: // Standard VGA
1687 case 0x13: // Standard VGA
1688 case 0x14: // Standard VGA
1689 case 0x15: // Standard VGA
1690 case 0x16: // Standard VGA
1691 case 0x17: // Standard VGA
1692 case 0x18: // Standard VGA
1693 return CIRRUS_HOOK_NOT_HANDLED;
1694 case 0x19: // Interlace End
1695 case 0x1a: // Miscellaneous Control
1696 case 0x1b: // Extended Display Control
1697 case 0x1c: // Sync Adjust and Genlock
1698 case 0x1d: // Overlay Extended Control
1699 s->cr[reg_index] = reg_value;
1700 #ifdef DEBUG_CIRRUS
1701 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1702 reg_index, reg_value);
1703 #endif
1704 break;
1705 case 0x22: // Graphics Data Latches Readback (R)
1706 case 0x24: // Attribute Controller Toggle Readback (R)
1707 case 0x26: // Attribute Controller Index Readback (R)
1708 case 0x27: // Part ID (R)
1709 break;
1710 case 0x25: // Part Status
1711 default:
1712 #ifdef DEBUG_CIRRUS
1713 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1714 reg_value);
1715 #endif
1716 break;
1717 }
1718
1719 return CIRRUS_HOOK_HANDLED;
1720 }
1721
1722 /***************************************
1723 *
1724 * memory-mapped I/O (bitblt)
1725 *
1726 ***************************************/
1727
1728 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1729 {
1730 int value = 0xff;
1731
1732 switch (address) {
1733 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1734 cirrus_hook_read_gr(s, 0x00, &value);
1735 break;
1736 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1737 cirrus_hook_read_gr(s, 0x10, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1740 cirrus_hook_read_gr(s, 0x12, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1743 cirrus_hook_read_gr(s, 0x14, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1746 cirrus_hook_read_gr(s, 0x01, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1749 cirrus_hook_read_gr(s, 0x11, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1752 cirrus_hook_read_gr(s, 0x13, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1755 cirrus_hook_read_gr(s, 0x15, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTWIDTH + 0):
1758 cirrus_hook_read_gr(s, 0x20, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTWIDTH + 1):
1761 cirrus_hook_read_gr(s, 0x21, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1764 cirrus_hook_read_gr(s, 0x22, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1767 cirrus_hook_read_gr(s, 0x23, &value);
1768 break;
1769 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1770 cirrus_hook_read_gr(s, 0x24, &value);
1771 break;
1772 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1773 cirrus_hook_read_gr(s, 0x25, &value);
1774 break;
1775 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1776 cirrus_hook_read_gr(s, 0x26, &value);
1777 break;
1778 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1779 cirrus_hook_read_gr(s, 0x27, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1782 cirrus_hook_read_gr(s, 0x28, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1785 cirrus_hook_read_gr(s, 0x29, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1788 cirrus_hook_read_gr(s, 0x2a, &value);
1789 break;
1790 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1791 cirrus_hook_read_gr(s, 0x2c, &value);
1792 break;
1793 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1794 cirrus_hook_read_gr(s, 0x2d, &value);
1795 break;
1796 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1797 cirrus_hook_read_gr(s, 0x2e, &value);
1798 break;
1799 case CIRRUS_MMIO_BLTWRITEMASK:
1800 cirrus_hook_read_gr(s, 0x2f, &value);
1801 break;
1802 case CIRRUS_MMIO_BLTMODE:
1803 cirrus_hook_read_gr(s, 0x30, &value);
1804 break;
1805 case CIRRUS_MMIO_BLTROP:
1806 cirrus_hook_read_gr(s, 0x32, &value);
1807 break;
1808 case CIRRUS_MMIO_BLTMODEEXT:
1809 cirrus_hook_read_gr(s, 0x33, &value);
1810 break;
1811 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1812 cirrus_hook_read_gr(s, 0x34, &value);
1813 break;
1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1815 cirrus_hook_read_gr(s, 0x35, &value);
1816 break;
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1818 cirrus_hook_read_gr(s, 0x38, &value);
1819 break;
1820 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1821 cirrus_hook_read_gr(s, 0x39, &value);
1822 break;
1823 case CIRRUS_MMIO_BLTSTATUS:
1824 cirrus_hook_read_gr(s, 0x31, &value);
1825 break;
1826 default:
1827 #ifdef DEBUG_CIRRUS
1828 printf("cirrus: mmio read - address 0x%04x\n", address);
1829 #endif
1830 break;
1831 }
1832
1833 return (uint8_t) value;
1834 }
1835
1836 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1837 uint8_t value)
1838 {
1839 switch (address) {
1840 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1841 cirrus_hook_write_gr(s, 0x00, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1844 cirrus_hook_write_gr(s, 0x10, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1847 cirrus_hook_write_gr(s, 0x12, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1850 cirrus_hook_write_gr(s, 0x14, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1853 cirrus_hook_write_gr(s, 0x01, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1856 cirrus_hook_write_gr(s, 0x11, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1859 cirrus_hook_write_gr(s, 0x13, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1862 cirrus_hook_write_gr(s, 0x15, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTWIDTH + 0):
1865 cirrus_hook_write_gr(s, 0x20, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTWIDTH + 1):
1868 cirrus_hook_write_gr(s, 0x21, value);
1869 break;
1870 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1871 cirrus_hook_write_gr(s, 0x22, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1874 cirrus_hook_write_gr(s, 0x23, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1877 cirrus_hook_write_gr(s, 0x24, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1880 cirrus_hook_write_gr(s, 0x25, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1883 cirrus_hook_write_gr(s, 0x26, value);
1884 break;
1885 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1886 cirrus_hook_write_gr(s, 0x27, value);
1887 break;
1888 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1889 cirrus_hook_write_gr(s, 0x28, value);
1890 break;
1891 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1892 cirrus_hook_write_gr(s, 0x29, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1895 cirrus_hook_write_gr(s, 0x2a, value);
1896 break;
1897 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1898 /* ignored */
1899 break;
1900 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1901 cirrus_hook_write_gr(s, 0x2c, value);
1902 break;
1903 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1904 cirrus_hook_write_gr(s, 0x2d, value);
1905 break;
1906 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1907 cirrus_hook_write_gr(s, 0x2e, value);
1908 break;
1909 case CIRRUS_MMIO_BLTWRITEMASK:
1910 cirrus_hook_write_gr(s, 0x2f, value);
1911 break;
1912 case CIRRUS_MMIO_BLTMODE:
1913 cirrus_hook_write_gr(s, 0x30, value);
1914 break;
1915 case CIRRUS_MMIO_BLTROP:
1916 cirrus_hook_write_gr(s, 0x32, value);
1917 break;
1918 case CIRRUS_MMIO_BLTMODEEXT:
1919 cirrus_hook_write_gr(s, 0x33, value);
1920 break;
1921 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1922 cirrus_hook_write_gr(s, 0x34, value);
1923 break;
1924 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1925 cirrus_hook_write_gr(s, 0x35, value);
1926 break;
1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1928 cirrus_hook_write_gr(s, 0x38, value);
1929 break;
1930 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1931 cirrus_hook_write_gr(s, 0x39, value);
1932 break;
1933 case CIRRUS_MMIO_BLTSTATUS:
1934 cirrus_hook_write_gr(s, 0x31, value);
1935 break;
1936 default:
1937 #ifdef DEBUG_CIRRUS
1938 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1939 address, value);
1940 #endif
1941 break;
1942 }
1943 }
1944
1945 /***************************************
1946 *
1947 * write mode 4/5
1948 *
1949 * assume TARGET_PAGE_SIZE >= 16
1950 *
1951 ***************************************/
1952
1953 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1954 unsigned mode,
1955 unsigned offset,
1956 uint32_t mem_value)
1957 {
1958 int x;
1959 unsigned val = mem_value;
1960 uint8_t *dst;
1961
1962 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1963 for (x = 0; x < 8; x++) {
1964 if (val & 0x80) {
1965 *dst = s->cirrus_shadow_gr1;
1966 } else if (mode == 5) {
1967 *dst = s->cirrus_shadow_gr0;
1968 }
1969 val <<= 1;
1970 dst++;
1971 }
1972 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1973 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1974 }
1975
1976 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1977 unsigned mode,
1978 unsigned offset,
1979 uint32_t mem_value)
1980 {
1981 int x;
1982 unsigned val = mem_value;
1983 uint8_t *dst;
1984
1985 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1986 for (x = 0; x < 8; x++) {
1987 if (val & 0x80) {
1988 *dst = s->cirrus_shadow_gr1;
1989 *(dst + 1) = s->gr[0x11];
1990 } else if (mode == 5) {
1991 *dst = s->cirrus_shadow_gr0;
1992 *(dst + 1) = s->gr[0x10];
1993 }
1994 val <<= 1;
1995 dst += 2;
1996 }
1997 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1998 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1999 }
2000
2001 /***************************************
2002 *
2003 * memory access between 0xa0000-0xbffff
2004 *
2005 ***************************************/
2006
2007 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2008 {
2009 CirrusVGAState *s = opaque;
2010 unsigned bank_index;
2011 unsigned bank_offset;
2012 uint32_t val;
2013
2014 if ((s->sr[0x07] & 0x01) == 0) {
2015 return vga_mem_readb(s, addr);
2016 }
2017
2018 addr &= 0x1ffff;
2019
2020 if (addr < 0x10000) {
2021 /* XXX handle bitblt */
2022 /* video memory */
2023 bank_index = addr >> 15;
2024 bank_offset = addr & 0x7fff;
2025 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2026 bank_offset += s->cirrus_bank_base[bank_index];
2027 if ((s->gr[0x0B] & 0x14) == 0x14) {
2028 bank_offset <<= 4;
2029 } else if (s->gr[0x0B] & 0x02) {
2030 bank_offset <<= 3;
2031 }
2032 bank_offset &= s->cirrus_addr_mask;
2033 val = *(s->vram_ptr + bank_offset);
2034 } else
2035 val = 0xff;
2036 } else if (addr >= 0x18000 && addr < 0x18100) {
2037 /* memory-mapped I/O */
2038 val = 0xff;
2039 if ((s->sr[0x17] & 0x44) == 0x04) {
2040 val = cirrus_mmio_blt_read(s, addr & 0xff);
2041 }
2042 } else {
2043 val = 0xff;
2044 #ifdef DEBUG_CIRRUS
2045 printf("cirrus: mem_readb %06x\n", addr);
2046 #endif
2047 }
2048 return val;
2049 }
2050
2051 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2052 {
2053 uint32_t v;
2054 #ifdef TARGET_WORDS_BIGENDIAN
2055 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2056 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2057 #else
2058 v = cirrus_vga_mem_readb(opaque, addr);
2059 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2060 #endif
2061 return v;
2062 }
2063
2064 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2065 {
2066 uint32_t v;
2067 #ifdef TARGET_WORDS_BIGENDIAN
2068 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2069 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2070 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2071 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2072 #else
2073 v = cirrus_vga_mem_readb(opaque, addr);
2074 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2075 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2076 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2077 #endif
2078 return v;
2079 }
2080
2081 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2082 uint32_t mem_value)
2083 {
2084 CirrusVGAState *s = opaque;
2085 unsigned bank_index;
2086 unsigned bank_offset;
2087 unsigned mode;
2088
2089 if ((s->sr[0x07] & 0x01) == 0) {
2090 vga_mem_writeb(s, addr, mem_value);
2091 return;
2092 }
2093
2094 addr &= 0x1ffff;
2095
2096 if (addr < 0x10000) {
2097 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2098 /* bitblt */
2099 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2100 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2101 cirrus_bitblt_cputovideo_next(s);
2102 }
2103 } else {
2104 /* video memory */
2105 bank_index = addr >> 15;
2106 bank_offset = addr & 0x7fff;
2107 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2108 bank_offset += s->cirrus_bank_base[bank_index];
2109 if ((s->gr[0x0B] & 0x14) == 0x14) {
2110 bank_offset <<= 4;
2111 } else if (s->gr[0x0B] & 0x02) {
2112 bank_offset <<= 3;
2113 }
2114 bank_offset &= s->cirrus_addr_mask;
2115 mode = s->gr[0x05] & 0x7;
2116 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2117 *(s->vram_ptr + bank_offset) = mem_value;
2118 cpu_physical_memory_set_dirty(s->vram_offset +
2119 bank_offset);
2120 } else {
2121 if ((s->gr[0x0B] & 0x14) != 0x14) {
2122 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2123 bank_offset,
2124 mem_value);
2125 } else {
2126 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2127 bank_offset,
2128 mem_value);
2129 }
2130 }
2131 }
2132 }
2133 } else if (addr >= 0x18000 && addr < 0x18100) {
2134 /* memory-mapped I/O */
2135 if ((s->sr[0x17] & 0x44) == 0x04) {
2136 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2137 }
2138 } else {
2139 #ifdef DEBUG_CIRRUS
2140 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2141 #endif
2142 }
2143 }
2144
2145 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2146 {
2147 #ifdef TARGET_WORDS_BIGENDIAN
2148 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2150 #else
2151 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2153 #endif
2154 }
2155
2156 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2157 {
2158 #ifdef TARGET_WORDS_BIGENDIAN
2159 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2160 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2161 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2163 #else
2164 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2165 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2166 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2167 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2168 #endif
2169 }
2170
2171 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2172 cirrus_vga_mem_readb,
2173 cirrus_vga_mem_readw,
2174 cirrus_vga_mem_readl,
2175 };
2176
2177 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2178 cirrus_vga_mem_writeb,
2179 cirrus_vga_mem_writew,
2180 cirrus_vga_mem_writel,
2181 };
2182
2183 /***************************************
2184 *
2185 * hardware cursor
2186 *
2187 ***************************************/
2188
2189 static inline void invalidate_cursor1(CirrusVGAState *s)
2190 {
2191 if (s->last_hw_cursor_size) {
2192 vga_invalidate_scanlines((VGAState *)s,
2193 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2194 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2195 }
2196 }
2197
2198 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2199 {
2200 const uint8_t *src;
2201 uint32_t content;
2202 int y, y_min, y_max;
2203
2204 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2205 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2206 src += (s->sr[0x13] & 0x3c) * 256;
2207 y_min = 64;
2208 y_max = -1;
2209 for(y = 0; y < 64; y++) {
2210 content = ((uint32_t *)src)[0] |
2211 ((uint32_t *)src)[1] |
2212 ((uint32_t *)src)[2] |
2213 ((uint32_t *)src)[3];
2214 if (content) {
2215 if (y < y_min)
2216 y_min = y;
2217 if (y > y_max)
2218 y_max = y;
2219 }
2220 src += 16;
2221 }
2222 } else {
2223 src += (s->sr[0x13] & 0x3f) * 256;
2224 y_min = 32;
2225 y_max = -1;
2226 for(y = 0; y < 32; y++) {
2227 content = ((uint32_t *)src)[0] |
2228 ((uint32_t *)(src + 128))[0];
2229 if (content) {
2230 if (y < y_min)
2231 y_min = y;
2232 if (y > y_max)
2233 y_max = y;
2234 }
2235 src += 4;
2236 }
2237 }
2238 if (y_min > y_max) {
2239 s->last_hw_cursor_y_start = 0;
2240 s->last_hw_cursor_y_end = 0;
2241 } else {
2242 s->last_hw_cursor_y_start = y_min;
2243 s->last_hw_cursor_y_end = y_max + 1;
2244 }
2245 }
2246
2247 /* NOTE: we do not currently handle the cursor bitmap change, so we
2248 update the cursor only if it moves. */
2249 static void cirrus_cursor_invalidate(VGAState *s1)
2250 {
2251 CirrusVGAState *s = (CirrusVGAState *)s1;
2252 int size;
2253
2254 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2255 size = 0;
2256 } else {
2257 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2258 size = 64;
2259 else
2260 size = 32;
2261 }
2262 /* invalidate last cursor and new cursor if any change */
2263 if (s->last_hw_cursor_size != size ||
2264 s->last_hw_cursor_x != s->hw_cursor_x ||
2265 s->last_hw_cursor_y != s->hw_cursor_y) {
2266
2267 invalidate_cursor1(s);
2268
2269 s->last_hw_cursor_size = size;
2270 s->last_hw_cursor_x = s->hw_cursor_x;
2271 s->last_hw_cursor_y = s->hw_cursor_y;
2272 /* compute the real cursor min and max y */
2273 cirrus_cursor_compute_yrange(s);
2274 invalidate_cursor1(s);
2275 }
2276 }
2277
2278 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2279 {
2280 CirrusVGAState *s = (CirrusVGAState *)s1;
2281 int w, h, bpp, x1, x2, poffset;
2282 unsigned int color0, color1;
2283 const uint8_t *palette, *src;
2284 uint32_t content;
2285
2286 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2287 return;
2288 /* fast test to see if the cursor intersects with the scan line */
2289 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2290 h = 64;
2291 } else {
2292 h = 32;
2293 }
2294 if (scr_y < s->hw_cursor_y ||
2295 scr_y >= (s->hw_cursor_y + h))
2296 return;
2297
2298 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2299 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2300 src += (s->sr[0x13] & 0x3c) * 256;
2301 src += (scr_y - s->hw_cursor_y) * 16;
2302 poffset = 8;
2303 content = ((uint32_t *)src)[0] |
2304 ((uint32_t *)src)[1] |
2305 ((uint32_t *)src)[2] |
2306 ((uint32_t *)src)[3];
2307 } else {
2308 src += (s->sr[0x13] & 0x3f) * 256;
2309 src += (scr_y - s->hw_cursor_y) * 4;
2310 poffset = 128;
2311 content = ((uint32_t *)src)[0] |
2312 ((uint32_t *)(src + 128))[0];
2313 }
2314 /* if nothing to draw, no need to continue */
2315 if (!content)
2316 return;
2317 w = h;
2318
2319 x1 = s->hw_cursor_x;
2320 if (x1 >= s->last_scr_width)
2321 return;
2322 x2 = s->hw_cursor_x + w;
2323 if (x2 > s->last_scr_width)
2324 x2 = s->last_scr_width;
2325 w = x2 - x1;
2326 palette = s->cirrus_hidden_palette;
2327 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2328 c6_to_8(palette[0x0 * 3 + 1]),
2329 c6_to_8(palette[0x0 * 3 + 2]));
2330 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2331 c6_to_8(palette[0xf * 3 + 1]),
2332 c6_to_8(palette[0xf * 3 + 2]));
2333 bpp = ((s->ds->depth + 7) >> 3);
2334 d1 += x1 * bpp;
2335 switch(s->ds->depth) {
2336 default:
2337 break;
2338 case 8:
2339 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2340 break;
2341 case 15:
2342 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2343 break;
2344 case 16:
2345 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2346 break;
2347 case 32:
2348 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2349 break;
2350 }
2351 }
2352
2353 /***************************************
2354 *
2355 * LFB memory access
2356 *
2357 ***************************************/
2358
2359 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2360 {
2361 CirrusVGAState *s = (CirrusVGAState *) opaque;
2362 uint32_t ret;
2363
2364 addr &= s->cirrus_addr_mask;
2365
2366 if (((s->sr[0x17] & 0x44) == 0x44) &&
2367 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2368 /* memory-mapped I/O */
2369 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2370 } else if (0) {
2371 /* XXX handle bitblt */
2372 ret = 0xff;
2373 } else {
2374 /* video memory */
2375 if ((s->gr[0x0B] & 0x14) == 0x14) {
2376 addr <<= 4;
2377 } else if (s->gr[0x0B] & 0x02) {
2378 addr <<= 3;
2379 }
2380 addr &= s->cirrus_addr_mask;
2381 ret = *(s->vram_ptr + addr);
2382 }
2383
2384 return ret;
2385 }
2386
2387 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2388 {
2389 uint32_t v;
2390 #ifdef TARGET_WORDS_BIGENDIAN
2391 v = cirrus_linear_readb(opaque, addr) << 8;
2392 v |= cirrus_linear_readb(opaque, addr + 1);
2393 #else
2394 v = cirrus_linear_readb(opaque, addr);
2395 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2396 #endif
2397 return v;
2398 }
2399
2400 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2401 {
2402 uint32_t v;
2403 #ifdef TARGET_WORDS_BIGENDIAN
2404 v = cirrus_linear_readb(opaque, addr) << 24;
2405 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2406 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2407 v |= cirrus_linear_readb(opaque, addr + 3);
2408 #else
2409 v = cirrus_linear_readb(opaque, addr);
2410 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2411 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2412 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2413 #endif
2414 return v;
2415 }
2416
2417 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2418 uint32_t val)
2419 {
2420 CirrusVGAState *s = (CirrusVGAState *) opaque;
2421 unsigned mode;
2422
2423 addr &= s->cirrus_addr_mask;
2424
2425 if (((s->sr[0x17] & 0x44) == 0x44) &&
2426 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2427 /* memory-mapped I/O */
2428 cirrus_mmio_blt_write(s, addr & 0xff, val);
2429 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2430 /* bitblt */
2431 *s->cirrus_srcptr++ = (uint8_t) val;
2432 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2433 cirrus_bitblt_cputovideo_next(s);
2434 }
2435 } else {
2436 /* video memory */
2437 if ((s->gr[0x0B] & 0x14) == 0x14) {
2438 addr <<= 4;
2439 } else if (s->gr[0x0B] & 0x02) {
2440 addr <<= 3;
2441 }
2442 addr &= s->cirrus_addr_mask;
2443
2444 mode = s->gr[0x05] & 0x7;
2445 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2446 *(s->vram_ptr + addr) = (uint8_t) val;
2447 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2448 } else {
2449 if ((s->gr[0x0B] & 0x14) != 0x14) {
2450 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2451 } else {
2452 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2453 }
2454 }
2455 }
2456 }
2457
2458 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2459 uint32_t val)
2460 {
2461 #ifdef TARGET_WORDS_BIGENDIAN
2462 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2463 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2464 #else
2465 cirrus_linear_writeb(opaque, addr, val & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2467 #endif
2468 }
2469
2470 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2471 uint32_t val)
2472 {
2473 #ifdef TARGET_WORDS_BIGENDIAN
2474 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2475 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2476 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2477 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2478 #else
2479 cirrus_linear_writeb(opaque, addr, val & 0xff);
2480 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2481 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2482 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2483 #endif
2484 }
2485
2486
2487 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2488 cirrus_linear_readb,
2489 cirrus_linear_readw,
2490 cirrus_linear_readl,
2491 };
2492
2493 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2494 cirrus_linear_writeb,
2495 cirrus_linear_writew,
2496 cirrus_linear_writel,
2497 };
2498
2499 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2500 uint32_t val)
2501 {
2502 CirrusVGAState *s = (CirrusVGAState *) opaque;
2503
2504 addr &= s->cirrus_addr_mask;
2505 *(s->vram_ptr + addr) = val;
2506 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2507 }
2508
2509 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2510 uint32_t val)
2511 {
2512 CirrusVGAState *s = (CirrusVGAState *) opaque;
2513
2514 addr &= s->cirrus_addr_mask;
2515 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2516 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2517 }
2518
2519 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2520 uint32_t val)
2521 {
2522 CirrusVGAState *s = (CirrusVGAState *) opaque;
2523
2524 addr &= s->cirrus_addr_mask;
2525 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2526 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2527 }
2528
2529 /***************************************
2530 *
2531 * system to screen memory access
2532 *
2533 ***************************************/
2534
2535
2536 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2537 {
2538 uint32_t ret;
2539
2540 /* XXX handle bitblt */
2541 ret = 0xff;
2542 return ret;
2543 }
2544
2545 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2546 {
2547 uint32_t v;
2548 #ifdef TARGET_WORDS_BIGENDIAN
2549 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2550 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2551 #else
2552 v = cirrus_linear_bitblt_readb(opaque, addr);
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2554 #endif
2555 return v;
2556 }
2557
2558 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2559 {
2560 uint32_t v;
2561 #ifdef TARGET_WORDS_BIGENDIAN
2562 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2563 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2564 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2565 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2566 #else
2567 v = cirrus_linear_bitblt_readb(opaque, addr);
2568 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2569 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2570 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2571 #endif
2572 return v;
2573 }
2574
2575 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2576 uint32_t val)
2577 {
2578 CirrusVGAState *s = (CirrusVGAState *) opaque;
2579
2580 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2581 /* bitblt */
2582 *s->cirrus_srcptr++ = (uint8_t) val;
2583 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2584 cirrus_bitblt_cputovideo_next(s);
2585 }
2586 }
2587 }
2588
2589 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2590 uint32_t val)
2591 {
2592 #ifdef TARGET_WORDS_BIGENDIAN
2593 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2594 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2595 #else
2596 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2598 #endif
2599 }
2600
2601 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2602 uint32_t val)
2603 {
2604 #ifdef TARGET_WORDS_BIGENDIAN
2605 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2606 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2608 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2609 #else
2610 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2611 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2612 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2613 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2614 #endif
2615 }
2616
2617
2618 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2619 cirrus_linear_bitblt_readb,
2620 cirrus_linear_bitblt_readw,
2621 cirrus_linear_bitblt_readl,
2622 };
2623
2624 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2625 cirrus_linear_bitblt_writeb,
2626 cirrus_linear_bitblt_writew,
2627 cirrus_linear_bitblt_writel,
2628 };
2629
2630 void set_vram_mapping(void *ptr, unsigned long begin, unsigned long end)
2631 {
2632 /* align begin and end address */
2633 begin = begin & TARGET_PAGE_MASK;
2634 end = begin + VGA_RAM_SIZE;
2635 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2636
2637 if (kvm_enabled()) {
2638 kvm_cpu_register_physical_memory(begin, end - begin,
2639 ptr - (void *)phys_ram_base);
2640 kvm_qemu_log_memory(begin, end - begin, 1);
2641 }
2642 }
2643
2644 void unset_vram_mapping(void *ptr, unsigned long begin, unsigned long end)
2645 {
2646 /* align begin and end address */
2647 end = begin + VGA_RAM_SIZE;
2648 begin = begin & TARGET_PAGE_MASK;
2649 end = (end + TARGET_PAGE_SIZE -1 ) & TARGET_PAGE_MASK;
2650
2651 if (kvm_enabled()) {
2652 kvm_qemu_log_memory(begin, end - begin, 0);
2653 kvm_cpu_unregister_physical_memory(begin, end - begin,
2654 ptr - (void *)phys_ram_base);
2655 }
2656 }
2657
2658 #ifdef CONFIG_X86
2659 static void kvm_update_vga_alias(CirrusVGAState *s, int ok, int bank)
2660 {
2661 unsigned limit, base;
2662
2663 if (!ok && !s->aliases_enabled)
2664 return;
2665 limit = s->cirrus_bank_limit[bank];
2666 if (limit > 0x8000)
2667 limit = 0x8000;
2668 base = s->cirrus_lfb_addr + s->cirrus_bank_base[bank];
2669 if (ok) {
2670 if (!s->aliases_enabled
2671 || base != s->aliased_bank_base[bank]
2672 || limit != s->aliased_bank_limit[bank]) {
2673 kvm_qemu_create_memory_alias(0xa0000 + bank * 0x8000,
2674 limit, base);
2675 s->aliased_bank_base[bank] = base;
2676 s->aliased_bank_limit[bank] = limit;
2677 }
2678 } else {
2679 kvm_qemu_destroy_memory_alias(0xa0000 + bank * 0x8000);
2680 }
2681 }
2682
2683 static void kvm_update_vga_aliases(CirrusVGAState *s, int ok)
2684 {
2685 if (kvm_enabled()) {
2686 kvm_update_vga_alias(s, ok, 0);
2687 kvm_update_vga_alias(s, ok, 1);
2688 }
2689 s->aliases_enabled = ok;
2690 }
2691 #endif
2692
2693 /* Compute the memory access functions */
2694 static void cirrus_update_memory_access(CirrusVGAState *s)
2695 {
2696 unsigned mode;
2697 #ifdef CONFIG_X86
2698 int want_vga_alias = 0;
2699 #endif
2700
2701 if ((s->sr[0x17] & 0x44) == 0x44) {
2702 goto generic_io;
2703 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2704 goto generic_io;
2705 } else {
2706 if ((s->gr[0x0B] & 0x14) == 0x14) {
2707 goto generic_io;
2708 } else if (s->gr[0x0B] & 0x02) {
2709 goto generic_io;
2710 }
2711
2712 mode = s->gr[0x05] & 0x7;
2713 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2714 if (kvm_enabled() && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2715 !s->map_addr) {
2716 set_vram_mapping(s->vram_ptr,
2717 s->cirrus_lfb_addr, s->cirrus_lfb_end);
2718 s->map_addr = s->cirrus_lfb_addr;
2719 s->map_end = s->cirrus_lfb_end;
2720 }
2721 #ifdef CONFIG_X86
2722 if (kvm_enabled()
2723 && !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2724 && !((s->sr[0x07] & 0x01) == 0)
2725 && !((s->gr[0x0B] & 0x14) == 0x14)
2726 && !(s->gr[0x0B] & 0x02))
2727 want_vga_alias = 1;
2728 #endif
2729 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2730 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2731 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2732 } else {
2733 generic_io:
2734 if (kvm_enabled() && s->cirrus_lfb_addr && s->cirrus_lfb_end &&
2735 s->map_addr) {
2736 unset_vram_mapping(s->vram_ptr,
2737 s->cirrus_lfb_addr,
2738 s->cirrus_lfb_end);
2739 s->map_addr = s->map_end = 0;
2740 }
2741 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2742 s->cirrus_linear_write[1] = cirrus_linear_writew;
2743 s->cirrus_linear_write[2] = cirrus_linear_writel;
2744 }
2745 }
2746 #if defined(CONFIG_X86)
2747 kvm_update_vga_aliases(s, want_vga_alias);
2748 #endif
2749
2750 }
2751
2752
2753 /* I/O ports */
2754
2755 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2756 {
2757 CirrusVGAState *s = opaque;
2758 int val, index;
2759
2760 /* check port range access depending on color/monochrome mode */
2761 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2762 || (addr >= 0x3d0 && addr <= 0x3df
2763 && !(s->msr & MSR_COLOR_EMULATION))) {
2764 val = 0xff;
2765 } else {
2766 switch (addr) {
2767 case 0x3c0:
2768 if (s->ar_flip_flop == 0) {
2769 val = s->ar_index;
2770 } else {
2771 val = 0;
2772 }
2773 break;
2774 case 0x3c1:
2775 index = s->ar_index & 0x1f;
2776 if (index < 21)
2777 val = s->ar[index];
2778 else
2779 val = 0;
2780 break;
2781 case 0x3c2:
2782 val = s->st00;
2783 break;
2784 case 0x3c4:
2785 val = s->sr_index;
2786 break;
2787 case 0x3c5:
2788 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2789 break;
2790 val = s->sr[s->sr_index];
2791 #ifdef DEBUG_VGA_REG
2792 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2793 #endif
2794 break;
2795 case 0x3c6:
2796 cirrus_read_hidden_dac(s, &val);
2797 break;
2798 case 0x3c7:
2799 val = s->dac_state;
2800 break;
2801 case 0x3c8:
2802 val = s->dac_write_index;
2803 s->cirrus_hidden_dac_lockindex = 0;
2804 break;
2805 case 0x3c9:
2806 if (cirrus_hook_read_palette(s, &val))
2807 break;
2808 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2809 if (++s->dac_sub_index == 3) {
2810 s->dac_sub_index = 0;
2811 s->dac_read_index++;
2812 }
2813 break;
2814 case 0x3ca:
2815 val = s->fcr;
2816 break;
2817 case 0x3cc:
2818 val = s->msr;
2819 break;
2820 case 0x3ce:
2821 val = s->gr_index;
2822 break;
2823 case 0x3cf:
2824 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2825 break;
2826 val = s->gr[s->gr_index];
2827 #ifdef DEBUG_VGA_REG
2828 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2829 #endif
2830 break;
2831 case 0x3b4:
2832 case 0x3d4:
2833 val = s->cr_index;
2834 break;
2835 case 0x3b5:
2836 case 0x3d5:
2837 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2838 break;
2839 val = s->cr[s->cr_index];
2840 #ifdef DEBUG_VGA_REG
2841 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2842 #endif
2843 break;
2844 case 0x3ba:
2845 case 0x3da:
2846 /* just toggle to fool polling */
2847 val = s->st01 = s->retrace((VGAState *) s);
2848 s->ar_flip_flop = 0;
2849 break;
2850 default:
2851 val = 0x00;
2852 break;
2853 }
2854 }
2855 #if defined(DEBUG_VGA)
2856 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2857 #endif
2858 return val;
2859 }
2860
2861 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2862 {
2863 CirrusVGAState *s = opaque;
2864 int index;
2865
2866 /* check port range access depending on color/monochrome mode */
2867 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2868 || (addr >= 0x3d0 && addr <= 0x3df
2869 && !(s->msr & MSR_COLOR_EMULATION)))
2870 return;
2871
2872 #ifdef DEBUG_VGA
2873 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2874 #endif
2875
2876 switch (addr) {
2877 case 0x3c0:
2878 if (s->ar_flip_flop == 0) {
2879 val &= 0x3f;
2880 s->ar_index = val;
2881 } else {
2882 index = s->ar_index & 0x1f;
2883 switch (index) {
2884 case 0x00 ... 0x0f:
2885 s->ar[index] = val & 0x3f;
2886 break;
2887 case 0x10:
2888 s->ar[index] = val & ~0x10;
2889 break;
2890 case 0x11:
2891 s->ar[index] = val;
2892 break;
2893 case 0x12:
2894 s->ar[index] = val & ~0xc0;
2895 break;
2896 case 0x13:
2897 s->ar[index] = val & ~0xf0;
2898 break;
2899 case 0x14:
2900 s->ar[index] = val & ~0xf0;
2901 break;
2902 default:
2903 break;
2904 }
2905 }
2906 s->ar_flip_flop ^= 1;
2907 break;
2908 case 0x3c2:
2909 s->msr = val & ~0x10;
2910 s->update_retrace_info((VGAState *) s);
2911 break;
2912 case 0x3c4:
2913 s->sr_index = val;
2914 break;
2915 case 0x3c5:
2916 if (cirrus_hook_write_sr(s, s->sr_index, val))
2917 break;
2918 #ifdef DEBUG_VGA_REG
2919 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2920 #endif
2921 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2922 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2923 break;
2924 case 0x3c6:
2925 cirrus_write_hidden_dac(s, val);
2926 break;
2927 case 0x3c7:
2928 s->dac_read_index = val;
2929 s->dac_sub_index = 0;
2930 s->dac_state = 3;
2931 break;
2932 case 0x3c8:
2933 s->dac_write_index = val;
2934 s->dac_sub_index = 0;
2935 s->dac_state = 0;
2936 break;
2937 case 0x3c9:
2938 if (cirrus_hook_write_palette(s, val))
2939 break;
2940 s->dac_cache[s->dac_sub_index] = val;
2941 if (++s->dac_sub_index == 3) {
2942 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2943 s->dac_sub_index = 0;
2944 s->dac_write_index++;
2945 }
2946 break;
2947 case 0x3ce:
2948 s->gr_index = val;
2949 break;
2950 case 0x3cf:
2951 if (cirrus_hook_write_gr(s, s->gr_index, val))
2952 break;
2953 #ifdef DEBUG_VGA_REG
2954 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2955 #endif
2956 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2957 break;
2958 case 0x3b4:
2959 case 0x3d4:
2960 s->cr_index = val;
2961 break;
2962 case 0x3b5:
2963 case 0x3d5:
2964 if (cirrus_hook_write_cr(s, s->cr_index, val))
2965 break;
2966 #ifdef DEBUG_VGA_REG
2967 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2968 #endif
2969 /* handle CR0-7 protection */
2970 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2971 /* can always write bit 4 of CR7 */
2972 if (s->cr_index == 7)
2973 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2974 return;
2975 }
2976 switch (s->cr_index) {
2977 case 0x01: /* horizontal display end */
2978 case 0x07:
2979 case 0x09:
2980 case 0x0c:
2981 case 0x0d:
2982 case 0x12: /* vertical display end */
2983 s->cr[s->cr_index] = val;
2984 break;
2985
2986 default:
2987 s->cr[s->cr_index] = val;
2988 break;
2989 }
2990
2991 switch(s->cr_index) {
2992 case 0x00:
2993 case 0x04:
2994 case 0x05:
2995 case 0x06:
2996 case 0x07:
2997 case 0x11:
2998 case 0x17:
2999 s->update_retrace_info((VGAState *) s);
3000 break;
3001 }
3002 break;
3003 case 0x3ba:
3004 case 0x3da:
3005 s->fcr = val & 0x10;
3006 break;
3007 }
3008 }
3009
3010 /***************************************
3011 *
3012 * memory-mapped I/O access
3013 *
3014 ***************************************/
3015
3016 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
3017 {
3018 CirrusVGAState *s = (CirrusVGAState *) opaque;
3019
3020 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3021
3022 if (addr >= 0x100) {
3023 return cirrus_mmio_blt_read(s, addr - 0x100);
3024 } else {
3025 return vga_ioport_read(s, addr + 0x3c0);
3026 }
3027 }
3028
3029 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
3030 {
3031 uint32_t v;
3032 #ifdef TARGET_WORDS_BIGENDIAN
3033 v = cirrus_mmio_readb(opaque, addr) << 8;
3034 v |= cirrus_mmio_readb(opaque, addr + 1);
3035 #else
3036 v = cirrus_mmio_readb(opaque, addr);
3037 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3038 #endif
3039 return v;
3040 }
3041
3042 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3043 {
3044 uint32_t v;
3045 #ifdef TARGET_WORDS_BIGENDIAN
3046 v = cirrus_mmio_readb(opaque, addr) << 24;
3047 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3048 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3049 v |= cirrus_mmio_readb(opaque, addr + 3);
3050 #else
3051 v = cirrus_mmio_readb(opaque, addr);
3052 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3053 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3054 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3055 #endif
3056 return v;
3057 }
3058
3059 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3060 uint32_t val)
3061 {
3062 CirrusVGAState *s = (CirrusVGAState *) opaque;
3063
3064 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3065
3066 if (addr >= 0x100) {
3067 cirrus_mmio_blt_write(s, addr - 0x100, val);
3068 } else {
3069 vga_ioport_write(s, addr + 0x3c0, val);
3070 }
3071 }
3072
3073 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3074 uint32_t val)
3075 {
3076 #ifdef TARGET_WORDS_BIGENDIAN
3077 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3078 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3079 #else
3080 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3081 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3082 #endif
3083 }
3084
3085 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3086 uint32_t val)
3087 {
3088 #ifdef TARGET_WORDS_BIGENDIAN
3089 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3090 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3091 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3092 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3093 #else
3094 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3095 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3096 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3097 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3098 #endif
3099 }
3100
3101
3102 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3103 cirrus_mmio_readb,
3104 cirrus_mmio_readw,
3105 cirrus_mmio_readl,
3106 };
3107
3108 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3109 cirrus_mmio_writeb,
3110 cirrus_mmio_writew,
3111 cirrus_mmio_writel,
3112 };
3113
3114 /* load/save state */
3115
3116 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3117 {
3118 CirrusVGAState *s = opaque;
3119
3120 if (s->pci_dev)
3121 pci_device_save(s->pci_dev, f);
3122
3123 qemu_put_be32s(f, &s->latch);
3124 qemu_put_8s(f, &s->sr_index);
3125 qemu_put_buffer(f, s->sr, 256);
3126 qemu_put_8s(f, &s->gr_index);
3127 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3128 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3129 qemu_put_buffer(f, s->gr + 2, 254);
3130 qemu_put_8s(f, &s->ar_index);
3131 qemu_put_buffer(f, s->ar, 21);
3132 qemu_put_be32(f, s->ar_flip_flop);
3133 qemu_put_8s(f, &s->cr_index);
3134 qemu_put_buffer(f, s->cr, 256);
3135 qemu_put_8s(f, &s->msr);
3136 qemu_put_8s(f, &s->fcr);
3137 qemu_put_8s(f, &s->st00);
3138 qemu_put_8s(f, &s->st01);
3139
3140 qemu_put_8s(f, &s->dac_state);
3141 qemu_put_8s(f, &s->dac_sub_index);
3142 qemu_put_8s(f, &s->dac_read_index);
3143 qemu_put_8s(f, &s->dac_write_index);
3144 qemu_put_buffer(f, s->dac_cache, 3);
3145 qemu_put_buffer(f, s->palette, 768);
3146
3147 qemu_put_be32(f, s->bank_offset);
3148
3149 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3150 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3151
3152 qemu_put_be32s(f, &s->hw_cursor_x);
3153 qemu_put_be32s(f, &s->hw_cursor_y);
3154 /* XXX: we do not save the bitblt state - we assume we do not save
3155 the state when the blitter is active */
3156
3157 if (kvm_enabled()) { /* XXX: KVM images ought to be loadable in QEMU */
3158 qemu_put_be32s(f, &s->real_vram_size);
3159 qemu_put_buffer(f, s->vram_ptr, s->real_vram_size);
3160 }
3161 }
3162
3163 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3164 {
3165 CirrusVGAState *s = opaque;
3166 int ret;
3167
3168 if (version_id > 2)
3169 return -EINVAL;
3170
3171 if (s->pci_dev && version_id >= 2) {
3172 ret = pci_device_load(s->pci_dev, f);
3173 if (ret < 0)
3174 return ret;
3175 }
3176
3177 qemu_get_be32s(f, &s->latch);
3178 qemu_get_8s(f, &s->sr_index);
3179 qemu_get_buffer(f, s->sr, 256);
3180 qemu_get_8s(f, &s->gr_index);
3181 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3182 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3183 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3184 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3185 qemu_get_buffer(f, s->gr + 2, 254);
3186 qemu_get_8s(f, &s->ar_index);
3187 qemu_get_buffer(f, s->ar, 21);
3188 s->ar_flip_flop=qemu_get_be32(f);
3189 qemu_get_8s(f, &s->cr_index);
3190 qemu_get_buffer(f, s->cr, 256);
3191 qemu_get_8s(f, &s->msr);
3192 qemu_get_8s(f, &s->fcr);
3193 qemu_get_8s(f, &s->st00);
3194 qemu_get_8s(f, &s->st01);
3195
3196 qemu_get_8s(f, &s->dac_state);
3197 qemu_get_8s(f, &s->dac_sub_index);
3198 qemu_get_8s(f, &s->dac_read_index);
3199 qemu_get_8s(f, &s->dac_write_index);
3200 qemu_get_buffer(f, s->dac_cache, 3);
3201 qemu_get_buffer(f, s->palette, 768);
3202
3203 s->bank_offset=qemu_get_be32(f);
3204
3205 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3206 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3207
3208 qemu_get_be32s(f, &s->hw_cursor_x);
3209 qemu_get_be32s(f, &s->hw_cursor_y);
3210
3211 if (kvm_enabled()) {
3212 int real_vram_size;
3213 qemu_get_be32s(f, &real_vram_size);
3214 if (real_vram_size != s->real_vram_size) {
3215 if (real_vram_size > s->real_vram_size)
3216 real_vram_size = s->real_vram_size;
3217 printf("%s: REAL_VRAM_SIZE MISMATCH !!!!!! SAVED=%d CURRENT=%d",
3218 __FUNCTION__, real_vram_size, s->real_vram_size);
3219 }
3220 qemu_get_buffer(f, s->vram_ptr, real_vram_size);
3221 cirrus_update_memory_access(s);
3222 }
3223
3224
3225 /* force refresh */
3226 s->graphic_mode = -1;
3227 cirrus_update_bank_ptr(s, 0);
3228 cirrus_update_bank_ptr(s, 1);
3229 return 0;
3230 }
3231
3232 /***************************************
3233 *
3234 * initialize
3235 *
3236 ***************************************/
3237
3238 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3239 {
3240 int vga_io_memory, i;
3241 static int inited;
3242
3243 if (!inited) {
3244 inited = 1;
3245 for(i = 0;i < 256; i++)
3246 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3247 rop_to_index[CIRRUS_ROP_0] = 0;
3248 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3249 rop_to_index[CIRRUS_ROP_NOP] = 2;
3250 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3251 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3252 rop_to_index[CIRRUS_ROP_SRC] = 5;
3253 rop_to_index[CIRRUS_ROP_1] = 6;
3254 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3255 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3256 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3257 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3258 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3259 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3260 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3261 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3262 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3263 }
3264
3265 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3266
3267 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3268 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3269 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3270 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3271
3272 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3273
3274 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3275 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3276 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3277 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3278
3279 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3280 cirrus_vga_mem_write, s);
3281 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3282 vga_io_memory);
3283 if (kvm_enabled())
3284 qemu_kvm_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3285
3286 s->sr[0x06] = 0x0f;
3287 if (device_id == CIRRUS_ID_CLGD5446) {
3288 /* 4MB 64 bit memory config, always PCI */
3289 s->sr[0x1F] = 0x2d; // MemClock
3290 s->gr[0x18] = 0x0f; // fastest memory configuration
3291 #if 1
3292 s->sr[0x0f] = 0x98;
3293 s->sr[0x17] = 0x20;
3294 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3295 s->real_vram_size = 4096 * 1024;
3296 #else
3297 s->sr[0x0f] = 0x18;
3298 s->sr[0x17] = 0x20;
3299 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3300 s->real_vram_size = 2048 * 1024;
3301 #endif
3302 } else {
3303 s->sr[0x1F] = 0x22; // MemClock
3304 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3305 if (is_pci)
3306 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3307 else
3308 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3309 s->real_vram_size = 2048 * 1024;
3310 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3311 }
3312 s->cr[0x27] = device_id;
3313
3314 /* Win2K seems to assume that the pattern buffer is at 0xff
3315 initially ! */
3316 memset(s->vram_ptr, 0xff, s->real_vram_size);
3317
3318 s->cirrus_hidden_dac_lockindex = 5;
3319 s->cirrus_hidden_dac_data = 0;
3320
3321 /* I/O handler for LFB */
3322 s->cirrus_linear_io_addr =
3323 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3324 s);
3325 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3326
3327 /* I/O handler for LFB */
3328 s->cirrus_linear_bitblt_io_addr =
3329 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3330 s);
3331
3332 /* I/O handler for memory-mapped I/O */
3333 s->cirrus_mmio_io_addr =
3334 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3335
3336 /* XXX: s->vram_size must be a power of two */
3337 s->cirrus_addr_mask = s->real_vram_size - 1;
3338 s->linear_mmio_mask = s->real_vram_size - 256;
3339
3340 s->get_bpp = cirrus_get_bpp;
3341 s->get_offsets = cirrus_get_offsets;
3342 s->get_resolution = cirrus_get_resolution;
3343 s->cursor_invalidate = cirrus_cursor_invalidate;
3344 s->cursor_draw_line = cirrus_cursor_draw_line;
3345
3346 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3347 }
3348
3349 /***************************************
3350 *
3351 * ISA bus support
3352 *
3353 ***************************************/
3354
3355 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3356 unsigned long vga_ram_offset, int vga_ram_size)
3357 {
3358 CirrusVGAState *s;
3359
3360 s = qemu_mallocz(sizeof(CirrusVGAState));
3361
3362 vga_common_init((VGAState *)s,
3363 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3364 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3365 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3366 s->screen_dump, s->text_update, s);
3367 /* XXX ISA-LFB support */
3368 }
3369
3370 /***************************************
3371 *
3372 * PCI bus support
3373 *
3374 ***************************************/
3375
3376 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3377 uint32_t addr, uint32_t size, int type)
3378 {
3379 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3380
3381 /* XXX: add byte swapping apertures */
3382 cpu_register_physical_memory(addr, s->vram_size,
3383 s->cirrus_linear_io_addr);
3384 if (kvm_enabled()) {
3385 s->cirrus_lfb_addr = addr;
3386 s->cirrus_lfb_end = addr + VGA_RAM_SIZE;
3387
3388 if (s->map_addr && (s->cirrus_lfb_addr != s->map_addr) &&
3389 (s->cirrus_lfb_end != s->map_end))
3390 printf("cirrus vga map change while on lfb mode\n");
3391 }
3392
3393 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3394 s->cirrus_linear_bitblt_io_addr);
3395 }
3396
3397 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3398 uint32_t addr, uint32_t size, int type)
3399 {
3400 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3401
3402 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3403 s->cirrus_mmio_io_addr);
3404 }
3405
3406 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3407 unsigned long vga_ram_offset, int vga_ram_size)
3408 {
3409 PCICirrusVGAState *d;
3410 uint8_t *pci_conf;
3411 CirrusVGAState *s;
3412 int device_id;
3413
3414 device_id = CIRRUS_ID_CLGD5446;
3415
3416 /* setup PCI configuration registers */
3417 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3418 sizeof(PCICirrusVGAState),
3419 -1, NULL, NULL);
3420 pci_conf = d->dev.config;
3421 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3422 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3423 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3424 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3425 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3426 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3427 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3428 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3429
3430 /* setup VGA */
3431 s = &d->cirrus_vga;
3432 vga_common_init((VGAState *)s,
3433 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3434 cirrus_init_common(s, device_id, 1);
3435
3436 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3437 s->screen_dump, s->text_update, s);
3438
3439 s->pci_dev = (PCIDevice *)d;
3440
3441 /* setup memory space */
3442 /* memory #0 LFB */
3443 /* memory #1 memory-mapped I/O */
3444 /* XXX: s->vram_size must be a power of two */
3445 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3446 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3447 if (device_id == CIRRUS_ID_CLGD5446) {
3448 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3449 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3450 }
3451 /* XXX: ROM BIOS */
3452 }
Patches shipped by Fedora