hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "fdc.h"
  27 #include "pci.h"
  28 #include "vmware_vga.h"
  29 #include "usb-uhci.h"
  30 #include "usb-ohci.h"
  31 #include "prep_pci.h"
  32 #include "apb_pci.h"
  33 #include "block.h"
  34 #include "sysemu.h"
  35 #include "audio/audio.h"
  36 #include "net.h"
  37 #include "smbus.h"
  38 #include "boards.h"
  39 #include "monitor.h"
  40 #include "fw_cfg.h"
  41 #include "hpet_emul.h"
  42 #include "watchdog.h"
  43 #include "smbios.h"
  44 #include "ide.h"
  45 #include "loader.h"
  46 #include "elf.h"
  47 #include "multiboot.h"
  48
  49 /* output Bochs bios info messages */
  50 //#define DEBUG_BIOS
  51
  52 #define BIOS_FILENAME "bios.bin"
  53
  54 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  55
  56 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  57 #define ACPI_DATA_SIZE       0x10000
  58 #define BIOS_CFG_IOPORT 0x510
  59 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  60 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  61 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  62 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  63
  64 #define MAX_IDE_BUS 2
  65
  66 static FDCtrl *floppy_controller;
  67 static RTCState *rtc_state;
  68 static PITState *pit;
  69 static PCII440FXState *i440fx_state;
  70
  71 #define E820_NR_ENTRIES         16
  72
  73 struct e820_entry {
  74     uint64_t address;
  75     uint64_t length;
  76     uint32_t type;
  77 };
  78
  79 struct e820_table {
  80     uint32_t count;
  81     struct e820_entry entry[E820_NR_ENTRIES];
  82 };
  83
  84 static struct e820_table e820_table;
  85
  86 typedef struct isa_irq_state {
  87     qemu_irq *i8259;
  88     qemu_irq *ioapic;
  89 } IsaIrqState;
  90
  91 static void isa_irq_handler(void *opaque, int n, int level)
  92 {
  93     IsaIrqState *isa = (IsaIrqState *)opaque;
  94
  95     if (n < 16) {
  96         qemu_set_irq(isa->i8259[n], level);
  97     }
  98     if (isa->ioapic)
  99         qemu_set_irq(isa->ioapic[n], level);
 100 };
 101
 102 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 103 {
 104 }
 105
 106 /* MSDOS compatibility mode FPU exception support */
 107 static qemu_irq ferr_irq;
 108 /* XXX: add IGNNE support */
 109 void cpu_set_ferr(CPUX86State *s)
 110 {
 111     qemu_irq_raise(ferr_irq);
 112 }
 113
 114 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 115 {
 116     qemu_irq_lower(ferr_irq);
 117 }
 118
 119 /* TSC handling */
 120 uint64_t cpu_get_tsc(CPUX86State *env)
 121 {
 122     return cpu_get_ticks();
 123 }
 124
 125 /* SMM support */
 126 void cpu_smm_update(CPUState *env)
 127 {
 128     if (i440fx_state && env == first_cpu)
 129         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 130 }
 131
 132
 133 /* IRQ handling */
 134 int cpu_get_pic_interrupt(CPUState *env)
 135 {
 136     int intno;
 137
 138     intno = apic_get_interrupt(env);
 139     if (intno >= 0) {
 140         /* set irq request if a PIC irq is still pending */
 141         /* XXX: improve that */
 142         pic_update_irq(isa_pic);
 143         return intno;
 144     }
 145     /* read the irq from the PIC */
 146     if (!apic_accept_pic_intr(env))
 147         return -1;
 148
 149     intno = pic_read_irq(isa_pic);
 150     return intno;
 151 }
 152
 153 static void pic_irq_request(void *opaque, int irq, int level)
 154 {
 155     CPUState *env = first_cpu;
 156
 157     if (env->apic_state) {
 158         while (env) {
 159             if (apic_accept_pic_intr(env))
 160                 apic_deliver_pic_intr(env, level);
 161             env = env->next_cpu;
 162         }
 163     } else {
 164         if (level)
 165             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 166         else
 167             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 168     }
 169 }
 170
 171 /* PC cmos mappings */
 172
 173 #define REG_EQUIPMENT_BYTE          0x14
 174
 175 static int cmos_get_fd_drive_type(int fd0)
 176 {
 177     int val;
 178
 179     switch (fd0) {
 180     case 0:
 181         /* 1.44 Mb 3"5 drive */
 182         val = 4;
 183         break;
 184     case 1:
 185         /* 2.88 Mb 3"5 drive */
 186         val = 5;
 187         break;
 188     case 2:
 189         /* 1.2 Mb 5"5 drive */
 190         val = 2;
 191         break;
 192     default:
 193         val = 0;
 194         break;
 195     }
 196     return val;
 197 }
 198
 199 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 200 {
 201     RTCState *s = rtc_state;
 202     int cylinders, heads, sectors;
 203     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 204     rtc_set_memory(s, type_ofs, 47);
 205     rtc_set_memory(s, info_ofs, cylinders);
 206     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 207     rtc_set_memory(s, info_ofs + 2, heads);
 208     rtc_set_memory(s, info_ofs + 3, 0xff);
 209     rtc_set_memory(s, info_ofs + 4, 0xff);
 210     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 211     rtc_set_memory(s, info_ofs + 6, cylinders);
 212     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 213     rtc_set_memory(s, info_ofs + 8, sectors);
 214 }
 215
 216 /* convert boot_device letter to something recognizable by the bios */
 217 static int boot_device2nibble(char boot_device)
 218 {
 219     switch(boot_device) {
 220     case 'a':
 221     case 'b':
 222         return 0x01; /* floppy boot */
 223     case 'c':
 224         return 0x02; /* hard drive boot */
 225     case 'd':
 226         return 0x03; /* CD-ROM boot */
 227     case 'n':
 228         return 0x04; /* Network boot */
 229     }
 230     return 0;
 231 }
 232
 233 static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk)
 234 {
 235 #define PC_MAX_BOOT_DEVICES 3
 236     int nbds, bds[3] = { 0, };
 237     int i;
 238
 239     nbds = strlen(boot_device);
 240     if (nbds > PC_MAX_BOOT_DEVICES) {
 241         error_report("Too many boot devices for PC");
 242         return(1);
 243     }
 244     for (i = 0; i < nbds; i++) {
 245         bds[i] = boot_device2nibble(boot_device[i]);
 246         if (bds[i] == 0) {
 247             error_report("Invalid boot device for PC: '%c'",
 248                          boot_device[i]);
 249             return(1);
 250         }
 251     }
 252     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 253     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 254     return(0);
 255 }
 256
 257 static int pc_boot_set(void *opaque, const char *boot_device)
 258 {
 259     return set_boot_dev(opaque, boot_device, 0);
 260 }
 261
 262 /* hd_table must contain 4 block drivers */
 263 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 264                       const char *boot_device, DriveInfo **hd_table)
 265 {
 266     RTCState *s = rtc_state;
 267     int val;
 268     int fd0, fd1, nb;
 269     int i;
 270
 271     /* various important CMOS locations needed by PC/Bochs bios */
 272
 273     /* memory size */
 274     val = 640; /* base memory in K */
 275     rtc_set_memory(s, 0x15, val);
 276     rtc_set_memory(s, 0x16, val >> 8);
 277
 278     val = (ram_size / 1024) - 1024;
 279     if (val > 65535)
 280         val = 65535;
 281     rtc_set_memory(s, 0x17, val);
 282     rtc_set_memory(s, 0x18, val >> 8);
 283     rtc_set_memory(s, 0x30, val);
 284     rtc_set_memory(s, 0x31, val >> 8);
 285
 286     if (above_4g_mem_size) {
 287         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 288         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 289         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 290     }
 291
 292     if (ram_size > (16 * 1024 * 1024))
 293         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 294     else
 295         val = 0;
 296     if (val > 65535)
 297         val = 65535;
 298     rtc_set_memory(s, 0x34, val);
 299     rtc_set_memory(s, 0x35, val >> 8);
 300
 301     /* set the number of CPU */
 302     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 303
 304     /* set boot devices, and disable floppy signature check if requested */
 305     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 306         exit(1);
 307     }
 308
 309     /* floppy type */
 310
 311     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 312     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 313
 314     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 315     rtc_set_memory(s, 0x10, val);
 316
 317     val = 0;
 318     nb = 0;
 319     if (fd0 < 3)
 320         nb++;
 321     if (fd1 < 3)
 322         nb++;
 323     switch (nb) {
 324     case 0:
 325         break;
 326     case 1:
 327         val |= 0x01; /* 1 drive, ready for boot */
 328         break;
 329     case 2:
 330         val |= 0x41; /* 2 drives, ready for boot */
 331         break;
 332     }
 333     val |= 0x02; /* FPU is there */
 334     val |= 0x04; /* PS/2 mouse installed */
 335     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 336
 337     /* hard drives */
 338
 339     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 340     if (hd_table[0])
 341         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
 342     if (hd_table[1])
 343         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
 344
 345     val = 0;
 346     for (i = 0; i < 4; i++) {
 347         if (hd_table[i]) {
 348             int cylinders, heads, sectors, translation;
 349             /* NOTE: bdrv_get_geometry_hint() returns the physical
 350                 geometry.  It is always such that: 1 <= sects <= 63, 1
 351                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 352                 geometry can be different if a translation is done. */
 353             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 354             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 355                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 356                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 357                     /* No translation. */
 358                     translation = 0;
 359                 } else {
 360                     /* LBA translation. */
 361                     translation = 1;
 362                 }
 363             } else {
 364                 translation--;
 365             }
 366             val |= translation << (i * 2);
 367         }
 368     }
 369     rtc_set_memory(s, 0x39, val);
 370 }
 371
 372 void ioport_set_a20(int enable)
 373 {
 374     /* XXX: send to all CPUs ? */
 375     cpu_x86_set_a20(first_cpu, enable);
 376 }
 377
 378 int ioport_get_a20(void)
 379 {
 380     return ((first_cpu->a20_mask >> 20) & 1);
 381 }
 382
 383 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 384 {
 385     ioport_set_a20((val >> 1) & 1);
 386     /* XXX: bit 0 is fast reset */
 387 }
 388
 389 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 390 {
 391     return ioport_get_a20() << 1;
 392 }
 393
 394 /***********************************************************/
 395 /* Bochs BIOS debug ports */
 396
 397 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 398 {
 399     static const char shutdown_str[8] = "Shutdown";
 400     static int shutdown_index = 0;
 401
 402     switch(addr) {
 403         /* Bochs BIOS messages */
 404     case 0x400:
 405     case 0x401:
 406         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 407         exit(1);
 408     case 0x402:
 409     case 0x403:
 410 #ifdef DEBUG_BIOS
 411         fprintf(stderr, "%c", val);
 412 #endif
 413         break;
 414     case 0x8900:
 415         /* same as Bochs power off */
 416         if (val == shutdown_str[shutdown_index]) {
 417             shutdown_index++;
 418             if (shutdown_index == 8) {
 419                 shutdown_index = 0;
 420                 qemu_system_shutdown_request();
 421             }
 422         } else {
 423             shutdown_index = 0;
 424         }
 425         break;
 426
 427         /* LGPL'ed VGA BIOS messages */
 428     case 0x501:
 429     case 0x502:
 430         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 431         exit(1);
 432     case 0x500:
 433     case 0x503:
 434 #ifdef DEBUG_BIOS
 435         fprintf(stderr, "%c", val);
 436 #endif
 437         break;
 438     }
 439 }
 440
 441 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 442 {
 443     int index = e820_table.count;
 444     struct e820_entry *entry;
 445
 446     if (index >= E820_NR_ENTRIES)
 447         return -EBUSY;
 448     entry = &e820_table.entry[index];
 449
 450     entry->address = address;
 451     entry->length = length;
 452     entry->type = type;
 453
 454     e820_table.count++;
 455     return e820_table.count;
 456 }
 457
 458 static void *bochs_bios_init(void)
 459 {
 460     void *fw_cfg;
 461     uint8_t *smbios_table;
 462     size_t smbios_len;
 463     uint64_t *numa_fw_cfg;
 464     int i, j;
 465
 466     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 467     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 468     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 469     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 470     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 471
 472     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 473     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 474     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 475     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 476
 477     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 478
 479     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 480     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 481     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 482                      acpi_tables_len);
 483     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 484
 485     smbios_table = smbios_get_table(&smbios_len);
 486     if (smbios_table)
 487         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 488                          smbios_table, smbios_len);
 489     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 490                      sizeof(struct e820_table));
 491
 492     /* allocate memory for the NUMA channel: one (64bit) word for the number
 493      * of nodes, one word for each VCPU->node and one word for each node to
 494      * hold the amount of memory.
 495      */
 496     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 497     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 498     for (i = 0; i < smp_cpus; i++) {
 499         for (j = 0; j < nb_numa_nodes; j++) {
 500             if (node_cpumask[j] & (1 << i)) {
 501                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 502                 break;
 503             }
 504         }
 505     }
 506     for (i = 0; i < nb_numa_nodes; i++) {
 507         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 508     }
 509     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 510                      (1 + smp_cpus + nb_numa_nodes) * 8);
 511
 512     return fw_cfg;
 513 }
 514
 515 static long get_file_size(FILE *f)
 516 {
 517     long where, size;
 518
 519     /* XXX: on Unix systems, using fstat() probably makes more sense */
 520
 521     where = ftell(f);
 522     fseek(f, 0, SEEK_END);
 523     size = ftell(f);
 524     fseek(f, where, SEEK_SET);
 525
 526     return size;
 527 }
 528
 529 static void load_linux(void *fw_cfg,
 530                        const char *kernel_filename,
 531                        const char *initrd_filename,
 532                        const char *kernel_cmdline,
 533                        target_phys_addr_t max_ram_size)
 534 {
 535     uint16_t protocol;
 536     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 537     uint32_t initrd_max;
 538     uint8_t header[8192], *setup, *kernel, *initrd_data;
 539     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 540     FILE *f;
 541     char *vmode;
 542
 543     /* Align to 16 bytes as a paranoia measure */
 544     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 545
 546     /* load the kernel header */
 547     f = fopen(kernel_filename, "rb");
 548     if (!f || !(kernel_size = get_file_size(f)) ||
 549         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 550         MIN(ARRAY_SIZE(header), kernel_size)) {
 551         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 552                 kernel_filename, strerror(errno));
 553         exit(1);
 554     }
 555
 556     /* kernel protocol version */
 557 #if 0
 558     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 559 #endif
 560     if (ldl_p(header+0x202) == 0x53726448)
 561         protocol = lduw_p(header+0x206);
 562     else {
 563         /* This looks like a multiboot kernel. If it is, let's stop
 564            treating it like a Linux kernel. */
 565         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 566                            kernel_cmdline, kernel_size, header))
 567             return;
 568         protocol = 0;
 569     }
 570
 571     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 572         /* Low kernel */
 573         real_addr    = 0x90000;
 574         cmdline_addr = 0x9a000 - cmdline_size;
 575         prot_addr    = 0x10000;
 576     } else if (protocol < 0x202) {
 577         /* High but ancient kernel */
 578         real_addr    = 0x90000;
 579         cmdline_addr = 0x9a000 - cmdline_size;
 580         prot_addr    = 0x100000;
 581     } else {
 582         /* High and recent kernel */
 583         real_addr    = 0x10000;
 584         cmdline_addr = 0x20000;
 585         prot_addr    = 0x100000;
 586     }
 587
 588 #if 0
 589     fprintf(stderr,
 590             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 591             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 592             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 593             real_addr,
 594             cmdline_addr,
 595             prot_addr);
 596 #endif
 597
 598     /* highest address for loading the initrd */
 599     if (protocol >= 0x203)
 600         initrd_max = ldl_p(header+0x22c);
 601     else
 602         initrd_max = 0x37ffffff;
 603
 604     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 605         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 606
 607     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 608     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 609     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 610                      (uint8_t*)strdup(kernel_cmdline),
 611                      strlen(kernel_cmdline)+1);
 612
 613     if (protocol >= 0x202) {
 614         stl_p(header+0x228, cmdline_addr);
 615     } else {
 616         stw_p(header+0x20, 0xA33F);
 617         stw_p(header+0x22, cmdline_addr-real_addr);
 618     }
 619
 620     /* handle vga= parameter */
 621     vmode = strstr(kernel_cmdline, "vga=");
 622     if (vmode) {
 623         unsigned int video_mode;
 624         /* skip "vga=" */
 625         vmode += 4;
 626         if (!strncmp(vmode, "normal", 6)) {
 627             video_mode = 0xffff;
 628         } else if (!strncmp(vmode, "ext", 3)) {
 629             video_mode = 0xfffe;
 630         } else if (!strncmp(vmode, "ask", 3)) {
 631             video_mode = 0xfffd;
 632         } else {
 633             video_mode = strtol(vmode, NULL, 0);
 634         }
 635         stw_p(header+0x1fa, video_mode);
 636     }
 637
 638     /* loader type */
 639     /* High nybble = B reserved for Qemu; low nybble is revision number.
 640        If this code is substantially changed, you may want to consider
 641        incrementing the revision. */
 642     if (protocol >= 0x200)
 643         header[0x210] = 0xB0;
 644
 645     /* heap */
 646     if (protocol >= 0x201) {
 647         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 648         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 649     }
 650
 651     /* load initrd */
 652     if (initrd_filename) {
 653         if (protocol < 0x200) {
 654             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 655             exit(1);
 656         }
 657
 658         initrd_size = get_image_size(initrd_filename);
 659         initrd_addr = (initrd_max-initrd_size) & ~4095;
 660
 661         initrd_data = qemu_malloc(initrd_size);
 662         load_image(initrd_filename, initrd_data);
 663
 664         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 665         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 666         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 667
 668         stl_p(header+0x218, initrd_addr);
 669         stl_p(header+0x21c, initrd_size);
 670     }
 671
 672     /* load kernel and setup */
 673     setup_size = header[0x1f1];
 674     if (setup_size == 0)
 675         setup_size = 4;
 676     setup_size = (setup_size+1)*512;
 677     kernel_size -= setup_size;
 678
 679     setup  = qemu_malloc(setup_size);
 680     kernel = qemu_malloc(kernel_size);
 681     fseek(f, 0, SEEK_SET);
 682     if (fread(setup, 1, setup_size, f) != setup_size) {
 683         fprintf(stderr, "fread() failed\n");
 684         exit(1);
 685     }
 686     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 687         fprintf(stderr, "fread() failed\n");
 688         exit(1);
 689     }
 690     fclose(f);
 691     memcpy(setup, header, MIN(sizeof(header), setup_size));
 692
 693     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 694     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 695     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 696
 697     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 698     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 699     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 700
 701     option_rom[nb_option_roms] = "linuxboot.bin";
 702     nb_option_roms++;
 703 }
 704
 705 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 706 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 707 static const int ide_irq[2] = { 14, 15 };
 708
 709 #define NE2000_NB_MAX 6
 710
 711 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 712                                               0x280, 0x380 };
 713 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 714
 715 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 716 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 717
 718 #ifdef HAS_AUDIO
 719 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 720 {
 721     struct soundhw *c;
 722
 723     for (c = soundhw; c->name; ++c) {
 724         if (c->enabled) {
 725             if (c->isa) {
 726                 c->init.init_isa(pic);
 727             } else {
 728                 if (pci_bus) {
 729                     c->init.init_pci(pci_bus);
 730                 }
 731             }
 732         }
 733     }
 734 }
 735 #endif
 736
 737 static void pc_init_ne2k_isa(NICInfo *nd)
 738 {
 739     static int nb_ne2k = 0;
 740
 741     if (nb_ne2k == NE2000_NB_MAX)
 742         return;
 743     isa_ne2000_init(ne2000_io[nb_ne2k],
 744                     ne2000_irq[nb_ne2k], nd);
 745     nb_ne2k++;
 746 }
 747
 748 int cpu_is_bsp(CPUState *env)
 749 {
 750     /* We hard-wire the BSP to the first CPU. */
 751     return env->cpu_index == 0;
 752 }
 753
 754 static CPUState *pc_new_cpu(const char *cpu_model)
 755 {
 756     CPUState *env;
 757
 758     env = cpu_init(cpu_model);
 759     if (!env) {
 760         fprintf(stderr, "Unable to find x86 CPU definition\n");
 761         exit(1);
 762     }
 763     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 764         env->cpuid_apic_id = env->cpu_index;
 765         /* APIC reset callback resets cpu */
 766         apic_init(env);
 767     } else {
 768         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 769     }
 770     return env;
 771 }
 772
 773 /* PC hardware initialisation */
 774 static void pc_init1(ram_addr_t ram_size,
 775                      const char *boot_device,
 776                      const char *kernel_filename,
 777                      const char *kernel_cmdline,
 778                      const char *initrd_filename,
 779                      const char *cpu_model,
 780                      int pci_enabled)
 781 {
 782     char *filename;
 783     int ret, linux_boot, i;
 784     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 785     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 786     int bios_size, isa_bios_size;
 787     PCIBus *pci_bus;
 788     ISADevice *isa_dev;
 789     int piix3_devfn = -1;
 790     CPUState *env;
 791     qemu_irq *cpu_irq;
 792     qemu_irq *isa_irq;
 793     qemu_irq *i8259;
 794     IsaIrqState *isa_irq_state;
 795     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 796     DriveInfo *fd[MAX_FD];
 797     void *fw_cfg;
 798
 799     if (ram_size >= 0xe0000000 ) {
 800         above_4g_mem_size = ram_size - 0xe0000000;
 801         below_4g_mem_size = 0xe0000000;
 802     } else {
 803         below_4g_mem_size = ram_size;
 804     }
 805
 806     linux_boot = (kernel_filename != NULL);
 807
 808     /* init CPUs */
 809     if (cpu_model == NULL) {
 810 #ifdef TARGET_X86_64
 811         cpu_model = "qemu64";
 812 #else
 813         cpu_model = "qemu32";
 814 #endif
 815     }
 816
 817     for (i = 0; i < smp_cpus; i++) {
 818         env = pc_new_cpu(cpu_model);
 819     }
 820
 821     vmport_init();
 822
 823     /* allocate RAM */
 824     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 825     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 826     cpu_register_physical_memory(0x100000,
 827                  below_4g_mem_size - 0x100000,
 828                  ram_addr + 0x100000);
 829
 830     /* above 4giga memory allocation */
 831     if (above_4g_mem_size > 0) {
 832 #if TARGET_PHYS_ADDR_BITS == 32
 833         hw_error("To much RAM for 32-bit physical address");
 834 #else
 835         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 836         cpu_register_physical_memory(0x100000000ULL,
 837                                      above_4g_mem_size,
 838                                      ram_addr);
 839 #endif
 840     }
 841
 842
 843     /* BIOS load */
 844     if (bios_name == NULL)
 845         bios_name = BIOS_FILENAME;
 846     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 847     if (filename) {
 848         bios_size = get_image_size(filename);
 849     } else {
 850         bios_size = -1;
 851     }
 852     if (bios_size <= 0 ||
 853         (bios_size % 65536) != 0) {
 854         goto bios_error;
 855     }
 856     bios_offset = qemu_ram_alloc(bios_size);
 857     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 858     if (ret != 0) {
 859     bios_error:
 860         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 861         exit(1);
 862     }
 863     if (filename) {
 864         qemu_free(filename);
 865     }
 866     /* map the last 128KB of the BIOS in ISA space */
 867     isa_bios_size = bios_size;
 868     if (isa_bios_size > (128 * 1024))
 869         isa_bios_size = 128 * 1024;
 870     cpu_register_physical_memory(0x100000 - isa_bios_size,
 871                                  isa_bios_size,
 872                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 873
 874     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 875     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 876
 877     /* map all the bios at the top of memory */
 878     cpu_register_physical_memory((uint32_t)(-bios_size),
 879                                  bios_size, bios_offset | IO_MEM_ROM);
 880
 881     fw_cfg = bochs_bios_init();
 882     rom_set_fw(fw_cfg);
 883
 884     if (linux_boot) {
 885         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 886     }
 887
 888     for (i = 0; i < nb_option_roms; i++) {
 889         rom_add_option(option_rom[i]);
 890     }
 891
 892     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 893     i8259 = i8259_init(cpu_irq[0]);
 894     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
 895     isa_irq_state->i8259 = i8259;
 896     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 897
 898     if (pci_enabled) {
 899         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
 900     } else {
 901         pci_bus = NULL;
 902         isa_bus_new(NULL);
 903     }
 904     isa_bus_irqs(isa_irq);
 905
 906     ferr_irq = isa_reserve_irq(13);
 907
 908     /* init basic PC hardware */
 909     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 910
 911     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 912
 913     if (cirrus_vga_enabled) {
 914         if (pci_enabled) {
 915             pci_cirrus_vga_init(pci_bus);
 916         } else {
 917             isa_cirrus_vga_init();
 918         }
 919     } else if (vmsvga_enabled) {
 920         if (pci_enabled)
 921             pci_vmsvga_init(pci_bus);
 922         else
 923             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 924     } else if (std_vga_enabled) {
 925         if (pci_enabled) {
 926             pci_vga_init(pci_bus, 0, 0);
 927         } else {
 928             isa_vga_init();
 929         }
 930     }
 931
 932     rtc_state = rtc_init(2000);
 933
 934     qemu_register_boot_set(pc_boot_set, rtc_state);
 935
 936     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
 937     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
 938
 939     if (pci_enabled) {
 940         isa_irq_state->ioapic = ioapic_init();
 941     }
 942     pit = pit_init(0x40, isa_reserve_irq(0));
 943     pcspk_init(pit);
 944     if (!no_hpet) {
 945         hpet_init(isa_irq);
 946     }
 947
 948     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 949         if (serial_hds[i]) {
 950             serial_isa_init(i, serial_hds[i]);
 951         }
 952     }
 953
 954     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 955         if (parallel_hds[i]) {
 956             parallel_init(i, parallel_hds[i]);
 957         }
 958     }
 959
 960     for(i = 0; i < nb_nics; i++) {
 961         NICInfo *nd = &nd_table[i];
 962
 963         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 964             pc_init_ne2k_isa(nd);
 965         else
 966             pci_nic_init_nofail(nd, "e1000", NULL);
 967     }
 968
 969     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 970         fprintf(stderr, "qemu: too many IDE bus\n");
 971         exit(1);
 972     }
 973
 974     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 975         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 976     }
 977
 978     if (pci_enabled) {
 979         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
 980     } else {
 981         for(i = 0; i < MAX_IDE_BUS; i++) {
 982             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 983                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 984         }
 985     }
 986
 987     isa_dev = isa_create_simple("i8042");
 988     DMA_init(0);
 989 #ifdef HAS_AUDIO
 990     audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
 991 #endif
 992
 993     for(i = 0; i < MAX_FD; i++) {
 994         fd[i] = drive_get(IF_FLOPPY, 0, i);
 995     }
 996     floppy_controller = fdctrl_init_isa(fd);
 997
 998     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
 999
1000     if (pci_enabled && usb_enabled) {
1001         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1002     }
1003
1004     if (pci_enabled && acpi_enabled) {
1005         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1006         i2c_bus *smbus;
1007
1008         /* TODO: Populate SPD eeprom data.  */
1009         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1010                               isa_reserve_irq(9));
1011         for (i = 0; i < 8; i++) {
1012             DeviceState *eeprom;
1013             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1014             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1015             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1016             qdev_init_nofail(eeprom);
1017         }
1018         piix4_acpi_system_hot_add_init(pci_bus);
1019     }
1020
1021     if (i440fx_state) {
1022         i440fx_init_memory_mappings(i440fx_state);
1023     }
1024
1025     if (pci_enabled) {
1026         int max_bus;
1027         int bus;
1028
1029         max_bus = drive_get_max_bus(IF_SCSI);
1030         for (bus = 0; bus <= max_bus; bus++) {
1031             pci_create_simple(pci_bus, -1, "lsi53c895a");
1032         }
1033     }
1034 }
1035
1036 static void pc_init_pci(ram_addr_t ram_size,
1037                         const char *boot_device,
1038                         const char *kernel_filename,
1039                         const char *kernel_cmdline,
1040                         const char *initrd_filename,
1041                         const char *cpu_model)
1042 {
1043     pc_init1(ram_size, boot_device,
1044              kernel_filename, kernel_cmdline,
1045              initrd_filename, cpu_model, 1);
1046 }
1047
1048 static void pc_init_isa(ram_addr_t ram_size,
1049                         const char *boot_device,
1050                         const char *kernel_filename,
1051                         const char *kernel_cmdline,
1052                         const char *initrd_filename,
1053                         const char *cpu_model)
1054 {
1055     if (cpu_model == NULL)
1056         cpu_model = "486";
1057     pc_init1(ram_size, boot_device,
1058              kernel_filename, kernel_cmdline,
1059              initrd_filename, cpu_model, 0);
1060 }
1061
1062 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1063    BIOS will read it and start S3 resume at POST Entry */
1064 void cmos_set_s3_resume(void)
1065 {
1066     if (rtc_state)
1067         rtc_set_memory(rtc_state, 0xF, 0xFE);
1068 }
1069
1070 static QEMUMachine pc_machine = {
1071     .name = "pc-0.13",
1072     .alias = "pc",
1073     .desc = "Standard PC",
1074     .init = pc_init_pci,
1075     .max_cpus = 255,
1076     .is_default = 1,
1077 };
1078
1079 static QEMUMachine pc_machine_v0_12 = {
1080     .name = "pc-0.12",
1081     .desc = "Standard PC",
1082     .init = pc_init_pci,
1083     .max_cpus = 255,
1084     .compat_props = (GlobalProperty[]) {
1085         {
1086             .driver   = "virtio-serial-pci",
1087             .property = "max_nr_ports",
1088             .value    = stringify(1),
1089         },{
1090             .driver   = "virtio-serial-pci",
1091             .property = "vectors",
1092             .value    = stringify(0),
1093         },
1094         { /* end of list */ }
1095     }
1096 };
1097
1098 static QEMUMachine pc_machine_v0_11 = {
1099     .name = "pc-0.11",
1100     .desc = "Standard PC, qemu 0.11",
1101     .init = pc_init_pci,
1102     .max_cpus = 255,
1103     .compat_props = (GlobalProperty[]) {
1104         {
1105             .driver   = "virtio-blk-pci",
1106             .property = "vectors",
1107             .value    = stringify(0),
1108         },{
1109             .driver   = "virtio-serial-pci",
1110             .property = "max_nr_ports",
1111             .value    = stringify(1),
1112         },{
1113             .driver   = "virtio-serial-pci",
1114             .property = "vectors",
1115             .value    = stringify(0),
1116         },{
1117             .driver   = "ide-drive",
1118             .property = "ver",
1119             .value    = "0.11",
1120         },{
1121             .driver   = "scsi-disk",
1122             .property = "ver",
1123             .value    = "0.11",
1124         },{
1125             .driver   = "PCI",
1126             .property = "rombar",
1127             .value    = stringify(0),
1128         },
1129         { /* end of list */ }
1130     }
1131 };
1132
1133 static QEMUMachine pc_machine_v0_10 = {
1134     .name = "pc-0.10",
1135     .desc = "Standard PC, qemu 0.10",
1136     .init = pc_init_pci,
1137     .max_cpus = 255,
1138     .compat_props = (GlobalProperty[]) {
1139         {
1140             .driver   = "virtio-blk-pci",
1141             .property = "class",
1142             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1143         },{
1144             .driver   = "virtio-serial-pci",
1145             .property = "class",
1146             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1147         },{
1148             .driver   = "virtio-serial-pci",
1149             .property = "max_nr_ports",
1150             .value    = stringify(1),
1151         },{
1152             .driver   = "virtio-serial-pci",
1153             .property = "vectors",
1154             .value    = stringify(0),
1155         },{
1156             .driver   = "virtio-net-pci",
1157             .property = "vectors",
1158             .value    = stringify(0),
1159         },{
1160             .driver   = "virtio-blk-pci",
1161             .property = "vectors",
1162             .value    = stringify(0),
1163         },{
1164             .driver   = "ide-drive",
1165             .property = "ver",
1166             .value    = "0.10",
1167         },{
1168             .driver   = "scsi-disk",
1169             .property = "ver",
1170             .value    = "0.10",
1171         },{
1172             .driver   = "PCI",
1173             .property = "rombar",
1174             .value    = stringify(0),
1175         },
1176         { /* end of list */ }
1177     },
1178 };
1179
1180 static QEMUMachine isapc_machine = {
1181     .name = "isapc",
1182     .desc = "ISA-only PC",
1183     .init = pc_init_isa,
1184     .max_cpus = 1,
1185 };
1186
1187 static void pc_machine_init(void)
1188 {
1189     qemu_register_machine(&pc_machine);
1190     qemu_register_machine(&pc_machine_v0_12);
1191     qemu_register_machine(&pc_machine_v0_11);
1192     qemu_register_machine(&pc_machine_v0_10);
1193     qemu_register_machine(&isapc_machine);
1194 }
1195
1196 machine_init(pc_machine_init);