hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "monitor.h"
  31 #include "fw_cfg.h"
  32 #include "hpet_emul.h"
  33 #include "smbios.h"
  34 #include "loader.h"
  35 #include "elf.h"
  36 #include "multiboot.h"
  37 #include "mc146818rtc.h"
  38 #include "msix.h"
  39 #include "sysbus.h"
  40 #include "sysemu.h"
  41 #include "device-assignment.h"
  42 #include "kvm.h"
  43
  44 /* output Bochs bios info messages */
  45 //#define DEBUG_BIOS
  46
  47 /* debug PC/ISA interrupts */
  48 //#define DEBUG_IRQ
  49
  50 #ifdef DEBUG_IRQ
  51 #define DPRINTF(fmt, ...)                                       \
  52     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  53 #else
  54 #define DPRINTF(fmt, ...)
  55 #endif
  56
  57 #define BIOS_FILENAME "bios.bin"
  58 #define EXTBOOT_FILENAME "extboot.bin"
  59 #define VAPIC_FILENAME "vapic.bin"
  60
  61 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  62
  63 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  64 #define ACPI_DATA_SIZE       0x10000
  65 #define BIOS_CFG_IOPORT 0x510
  66 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  67 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  68 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  69 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  70 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  71
  72 #define MSI_ADDR_BASE 0xfee00000
  73
  74 #define E820_NR_ENTRIES         16
  75
  76 struct e820_entry {
  77     uint64_t address;
  78     uint64_t length;
  79     uint32_t type;
  80 };
  81
  82 struct e820_table {
  83     uint32_t count;
  84     struct e820_entry entry[E820_NR_ENTRIES];
  85 };
  86
  87 static struct e820_table e820_table;
  88
  89 void isa_irq_handler(void *opaque, int n, int level)
  90 {
  91     IsaIrqState *isa = (IsaIrqState *)opaque;
  92
  93     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  94     if (n < 16) {
  95         qemu_set_irq(isa->i8259[n], level);
  96     }
  97     if (isa->ioapic)
  98         qemu_set_irq(isa->ioapic[n], level);
  99 };
 100
 101 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 102 {
 103 }
 104
 105 /* MSDOS compatibility mode FPU exception support */
 106 static qemu_irq ferr_irq;
 107
 108 void pc_register_ferr_irq(qemu_irq irq)
 109 {
 110     ferr_irq = irq;
 111 }
 112
 113 /* XXX: add IGNNE support */
 114 void cpu_set_ferr(CPUX86State *s)
 115 {
 116     qemu_irq_raise(ferr_irq);
 117 }
 118
 119 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 120 {
 121     qemu_irq_lower(ferr_irq);
 122 }
 123
 124 /* TSC handling */
 125 uint64_t cpu_get_tsc(CPUX86State *env)
 126 {
 127     return cpu_get_ticks();
 128 }
 129
 130 /* SMM support */
 131
 132 static cpu_set_smm_t smm_set;
 133 static void *smm_arg;
 134
 135 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 136 {
 137     assert(smm_set == NULL);
 138     assert(smm_arg == NULL);
 139     smm_set = callback;
 140     smm_arg = arg;
 141 }
 142
 143 void cpu_smm_update(CPUState *env)
 144 {
 145     if (smm_set && smm_arg && env == first_cpu)
 146         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 147 }
 148
 149
 150 /* IRQ handling */
 151 int cpu_get_pic_interrupt(CPUState *env)
 152 {
 153     int intno;
 154
 155     intno = apic_get_interrupt(env->apic_state);
 156     if (intno >= 0) {
 157         /* set irq request if a PIC irq is still pending */
 158         /* XXX: improve that */
 159         pic_update_irq(isa_pic);
 160         return intno;
 161     }
 162     /* read the irq from the PIC */
 163     if (!apic_accept_pic_intr(env->apic_state)) {
 164         return -1;
 165     }
 166
 167     intno = pic_read_irq(isa_pic);
 168     return intno;
 169 }
 170
 171 static void pic_irq_request(void *opaque, int irq, int level)
 172 {
 173     CPUState *env = first_cpu;
 174
 175     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 176     if (env->apic_state) {
 177         while (env) {
 178             if (apic_accept_pic_intr(env->apic_state)) {
 179                 apic_deliver_pic_intr(env->apic_state, level);
 180             }
 181             env = env->next_cpu;
 182         }
 183     } else {
 184         if (level)
 185             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 186         else
 187             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 188     }
 189 }
 190
 191 /* PC cmos mappings */
 192
 193 #define REG_EQUIPMENT_BYTE          0x14
 194
 195 static int cmos_get_fd_drive_type(int fd0)
 196 {
 197     int val;
 198
 199     switch (fd0) {
 200     case 0:
 201         /* 1.44 Mb 3"5 drive */
 202         val = 4;
 203         break;
 204     case 1:
 205         /* 2.88 Mb 3"5 drive */
 206         val = 5;
 207         break;
 208     case 2:
 209         /* 1.2 Mb 5"5 drive */
 210         val = 2;
 211         break;
 212     default:
 213         val = 0;
 214         break;
 215     }
 216     return val;
 217 }
 218
 219 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 220                          ISADevice *s)
 221 {
 222     int cylinders, heads, sectors;
 223     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 224     rtc_set_memory(s, type_ofs, 47);
 225     rtc_set_memory(s, info_ofs, cylinders);
 226     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 227     rtc_set_memory(s, info_ofs + 2, heads);
 228     rtc_set_memory(s, info_ofs + 3, 0xff);
 229     rtc_set_memory(s, info_ofs + 4, 0xff);
 230     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 231     rtc_set_memory(s, info_ofs + 6, cylinders);
 232     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 233     rtc_set_memory(s, info_ofs + 8, sectors);
 234 }
 235
 236 /* convert boot_device letter to something recognizable by the bios */
 237 static int boot_device2nibble(char boot_device)
 238 {
 239     switch(boot_device) {
 240     case 'a':
 241     case 'b':
 242         return 0x01; /* floppy boot */
 243     case 'c':
 244         return 0x02; /* hard drive boot */
 245     case 'd':
 246         return 0x03; /* CD-ROM boot */
 247     case 'n':
 248         return 0x04; /* Network boot */
 249     }
 250     return 0;
 251 }
 252
 253 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 254 {
 255 #define PC_MAX_BOOT_DEVICES 3
 256     int nbds, bds[3] = { 0, };
 257     int i;
 258
 259     nbds = strlen(boot_device);
 260     if (nbds > PC_MAX_BOOT_DEVICES) {
 261         error_report("Too many boot devices for PC");
 262         return(1);
 263     }
 264     for (i = 0; i < nbds; i++) {
 265         bds[i] = boot_device2nibble(boot_device[i]);
 266         if (bds[i] == 0) {
 267             error_report("Invalid boot device for PC: '%c'",
 268                          boot_device[i]);
 269             return(1);
 270         }
 271     }
 272     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 273     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 274     return(0);
 275 }
 276
 277 static int pc_boot_set(void *opaque, const char *boot_device)
 278 {
 279     return set_boot_dev(opaque, boot_device, 0);
 280 }
 281
 282 /* hd_table must contain 4 block drivers */
 283 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 284                   const char *boot_device, DriveInfo **hd_table,
 285                   FDCtrl *floppy_controller, ISADevice *s)
 286 {
 287     int val;
 288     int fd0, fd1, nb;
 289     int i;
 290
 291     /* various important CMOS locations needed by PC/Bochs bios */
 292
 293     /* memory size */
 294     val = 640; /* base memory in K */
 295     rtc_set_memory(s, 0x15, val);
 296     rtc_set_memory(s, 0x16, val >> 8);
 297
 298     val = (ram_size / 1024) - 1024;
 299     if (val > 65535)
 300         val = 65535;
 301     rtc_set_memory(s, 0x17, val);
 302     rtc_set_memory(s, 0x18, val >> 8);
 303     rtc_set_memory(s, 0x30, val);
 304     rtc_set_memory(s, 0x31, val >> 8);
 305
 306     if (above_4g_mem_size) {
 307         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 308         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 309         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 310     }
 311
 312     if (ram_size > (16 * 1024 * 1024))
 313         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 314     else
 315         val = 0;
 316     if (val > 65535)
 317         val = 65535;
 318     rtc_set_memory(s, 0x34, val);
 319     rtc_set_memory(s, 0x35, val >> 8);
 320
 321     /* set the number of CPU */
 322     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 323
 324     /* set boot devices, and disable floppy signature check if requested */
 325     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 326         exit(1);
 327     }
 328
 329     /* floppy type */
 330
 331     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 332     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 333
 334     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 335     rtc_set_memory(s, 0x10, val);
 336
 337     val = 0;
 338     nb = 0;
 339     if (fd0 < 3)
 340         nb++;
 341     if (fd1 < 3)
 342         nb++;
 343     switch (nb) {
 344     case 0:
 345         break;
 346     case 1:
 347         val |= 0x01; /* 1 drive, ready for boot */
 348         break;
 349     case 2:
 350         val |= 0x41; /* 2 drives, ready for boot */
 351         break;
 352     }
 353     val |= 0x02; /* FPU is there */
 354     val |= 0x04; /* PS/2 mouse installed */
 355     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 356
 357     /* hard drives */
 358
 359     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 360     if (hd_table[0])
 361         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s);
 362     if (hd_table[1])
 363         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s);
 364
 365     val = 0;
 366     for (i = 0; i < 4; i++) {
 367         if (hd_table[i]) {
 368             int cylinders, heads, sectors, translation;
 369             /* NOTE: bdrv_get_geometry_hint() returns the physical
 370                 geometry.  It is always such that: 1 <= sects <= 63, 1
 371                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 372                 geometry can be different if a translation is done. */
 373             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 374             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 375                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 376                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 377                     /* No translation. */
 378                     translation = 0;
 379                 } else {
 380                     /* LBA translation. */
 381                     translation = 1;
 382                 }
 383             } else {
 384                 translation--;
 385             }
 386             val |= translation << (i * 2);
 387         }
 388     }
 389     rtc_set_memory(s, 0x39, val);
 390 }
 391
 392 static void handle_a20_line_change(void *opaque, int irq, int level)
 393 {
 394     CPUState *cpu = opaque;
 395
 396     /* XXX: send to all CPUs ? */
 397     cpu_x86_set_a20(cpu, level);
 398 }
 399
 400 /***********************************************************/
 401 /* Bochs BIOS debug ports */
 402
 403 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 404 {
 405     static const char shutdown_str[8] = "Shutdown";
 406     static int shutdown_index = 0;
 407
 408     switch(addr) {
 409         /* Bochs BIOS messages */
 410     case 0x400:
 411     case 0x401:
 412         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 413         exit(1);
 414     case 0x402:
 415     case 0x403:
 416 #ifdef DEBUG_BIOS
 417         fprintf(stderr, "%c", val);
 418 #endif
 419         break;
 420     case 0x8900:
 421         /* same as Bochs power off */
 422         if (val == shutdown_str[shutdown_index]) {
 423             shutdown_index++;
 424             if (shutdown_index == 8) {
 425                 shutdown_index = 0;
 426                 qemu_system_shutdown_request();
 427             }
 428         } else {
 429             shutdown_index = 0;
 430         }
 431         break;
 432
 433         /* LGPL'ed VGA BIOS messages */
 434     case 0x501:
 435     case 0x502:
 436         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 437         exit(1);
 438     case 0x500:
 439     case 0x503:
 440 #ifdef DEBUG_BIOS
 441         fprintf(stderr, "%c", val);
 442 #endif
 443         break;
 444     }
 445 }
 446
 447 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 448 {
 449     int index = e820_table.count;
 450     struct e820_entry *entry;
 451
 452     if (index >= E820_NR_ENTRIES)
 453         return -EBUSY;
 454     entry = &e820_table.entry[index];
 455
 456     entry->address = address;
 457     entry->length = length;
 458     entry->type = type;
 459
 460     e820_table.count++;
 461     return e820_table.count;
 462 }
 463
 464 static void *bochs_bios_init(void)
 465 {
 466     void *fw_cfg;
 467     uint8_t *smbios_table;
 468     size_t smbios_len;
 469     uint64_t *numa_fw_cfg;
 470     int i, j;
 471
 472     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 473     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 474     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 475     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 476     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 477
 478     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 479     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 480     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 481     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 482
 483     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 484
 485     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 486     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 487     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 488                      acpi_tables_len);
 489     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 490
 491     smbios_table = smbios_get_table(&smbios_len);
 492     if (smbios_table)
 493         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 494                          smbios_table, smbios_len);
 495     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 496                      sizeof(struct e820_table));
 497
 498     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 499                      sizeof(struct hpet_fw_config));
 500     /* allocate memory for the NUMA channel: one (64bit) word for the number
 501      * of nodes, one word for each VCPU->node and one word for each node to
 502      * hold the amount of memory.
 503      */
 504     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 505     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 506     for (i = 0; i < smp_cpus; i++) {
 507         for (j = 0; j < nb_numa_nodes; j++) {
 508             if (node_cpumask[j] & (1 << i)) {
 509                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 510                 break;
 511             }
 512         }
 513     }
 514     for (i = 0; i < nb_numa_nodes; i++) {
 515         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 516     }
 517     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 518                      (1 + smp_cpus + nb_numa_nodes) * 8);
 519
 520     return fw_cfg;
 521 }
 522
 523 static long get_file_size(FILE *f)
 524 {
 525     long where, size;
 526
 527     /* XXX: on Unix systems, using fstat() probably makes more sense */
 528
 529     where = ftell(f);
 530     fseek(f, 0, SEEK_END);
 531     size = ftell(f);
 532     fseek(f, where, SEEK_SET);
 533
 534     return size;
 535 }
 536
 537 static void load_linux(void *fw_cfg,
 538                        const char *kernel_filename,
 539                        const char *initrd_filename,
 540                        const char *kernel_cmdline,
 541                        target_phys_addr_t max_ram_size)
 542 {
 543     uint16_t protocol;
 544     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 545     uint32_t initrd_max;
 546     uint8_t header[8192], *setup, *kernel, *initrd_data;
 547     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 548     FILE *f;
 549     char *vmode;
 550
 551     /* Align to 16 bytes as a paranoia measure */
 552     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 553
 554     /* load the kernel header */
 555     f = fopen(kernel_filename, "rb");
 556     if (!f || !(kernel_size = get_file_size(f)) ||
 557         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 558         MIN(ARRAY_SIZE(header), kernel_size)) {
 559         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 560                 kernel_filename, strerror(errno));
 561         exit(1);
 562     }
 563
 564     /* kernel protocol version */
 565 #if 0
 566     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 567 #endif
 568     if (ldl_p(header+0x202) == 0x53726448)
 569         protocol = lduw_p(header+0x206);
 570     else {
 571         /* This looks like a multiboot kernel. If it is, let's stop
 572            treating it like a Linux kernel. */
 573         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 574                            kernel_cmdline, kernel_size, header))
 575             return;
 576         protocol = 0;
 577     }
 578
 579     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 580         /* Low kernel */
 581         real_addr    = 0x90000;
 582         cmdline_addr = 0x9a000 - cmdline_size;
 583         prot_addr    = 0x10000;
 584     } else if (protocol < 0x202) {
 585         /* High but ancient kernel */
 586         real_addr    = 0x90000;
 587         cmdline_addr = 0x9a000 - cmdline_size;
 588         prot_addr    = 0x100000;
 589     } else {
 590         /* High and recent kernel */
 591         real_addr    = 0x10000;
 592         cmdline_addr = 0x20000;
 593         prot_addr    = 0x100000;
 594     }
 595
 596 #if 0
 597     fprintf(stderr,
 598             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 599             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 600             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 601             real_addr,
 602             cmdline_addr,
 603             prot_addr);
 604 #endif
 605
 606     /* highest address for loading the initrd */
 607     if (protocol >= 0x203)
 608         initrd_max = ldl_p(header+0x22c);
 609     else
 610         initrd_max = 0x37ffffff;
 611
 612     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 613         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 614
 615     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 616     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 617     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 618                      (uint8_t*)strdup(kernel_cmdline),
 619                      strlen(kernel_cmdline)+1);
 620
 621     if (protocol >= 0x202) {
 622         stl_p(header+0x228, cmdline_addr);
 623     } else {
 624         stw_p(header+0x20, 0xA33F);
 625         stw_p(header+0x22, cmdline_addr-real_addr);
 626     }
 627
 628     /* handle vga= parameter */
 629     vmode = strstr(kernel_cmdline, "vga=");
 630     if (vmode) {
 631         unsigned int video_mode;
 632         /* skip "vga=" */
 633         vmode += 4;
 634         if (!strncmp(vmode, "normal", 6)) {
 635             video_mode = 0xffff;
 636         } else if (!strncmp(vmode, "ext", 3)) {
 637             video_mode = 0xfffe;
 638         } else if (!strncmp(vmode, "ask", 3)) {
 639             video_mode = 0xfffd;
 640         } else {
 641             video_mode = strtol(vmode, NULL, 0);
 642         }
 643         stw_p(header+0x1fa, video_mode);
 644     }
 645
 646     /* loader type */
 647     /* High nybble = B reserved for Qemu; low nybble is revision number.
 648        If this code is substantially changed, you may want to consider
 649        incrementing the revision. */
 650     if (protocol >= 0x200)
 651         header[0x210] = 0xB0;
 652
 653     /* heap */
 654     if (protocol >= 0x201) {
 655         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 656         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 657     }
 658
 659     /* load initrd */
 660     if (initrd_filename) {
 661         if (protocol < 0x200) {
 662             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 663             exit(1);
 664         }
 665
 666         initrd_size = get_image_size(initrd_filename);
 667         if (initrd_size < 0) {
 668             fprintf(stderr, "qemu: error reading initrd %s\n",
 669                     initrd_filename);
 670             exit(1);
 671         }
 672
 673         initrd_addr = (initrd_max-initrd_size) & ~4095;
 674
 675         initrd_data = qemu_malloc(initrd_size);
 676         load_image(initrd_filename, initrd_data);
 677
 678         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 679         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 680         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 681
 682         stl_p(header+0x218, initrd_addr);
 683         stl_p(header+0x21c, initrd_size);
 684     }
 685
 686     /* load kernel and setup */
 687     setup_size = header[0x1f1];
 688     if (setup_size == 0)
 689         setup_size = 4;
 690     setup_size = (setup_size+1)*512;
 691     kernel_size -= setup_size;
 692
 693     setup  = qemu_malloc(setup_size);
 694     kernel = qemu_malloc(kernel_size);
 695     fseek(f, 0, SEEK_SET);
 696     if (fread(setup, 1, setup_size, f) != setup_size) {
 697         fprintf(stderr, "fread() failed\n");
 698         exit(1);
 699     }
 700     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 701         fprintf(stderr, "fread() failed\n");
 702         exit(1);
 703     }
 704     fclose(f);
 705     memcpy(setup, header, MIN(sizeof(header), setup_size));
 706
 707     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 708     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 709     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 710
 711     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 712     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 713     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 714
 715     option_rom[nb_option_roms] = "linuxboot.bin";
 716     nb_option_roms++;
 717 }
 718
 719 #define NE2000_NB_MAX 6
 720
 721 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 722                                               0x280, 0x380 };
 723 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 724
 725 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 726 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 727
 728 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 729 {
 730     struct soundhw *c;
 731
 732     for (c = soundhw; c->name; ++c) {
 733         if (c->enabled) {
 734             if (c->isa) {
 735                 c->init.init_isa(pic);
 736             } else {
 737                 if (pci_bus) {
 738                     c->init.init_pci(pci_bus);
 739                 }
 740             }
 741         }
 742     }
 743 }
 744
 745 void pc_init_ne2k_isa(NICInfo *nd)
 746 {
 747     static int nb_ne2k = 0;
 748
 749     if (nb_ne2k == NE2000_NB_MAX)
 750         return;
 751     isa_ne2000_init(ne2000_io[nb_ne2k],
 752                     ne2000_irq[nb_ne2k], nd);
 753     nb_ne2k++;
 754 }
 755
 756 int cpu_is_bsp(CPUState *env)
 757 {
 758     /* We hard-wire the BSP to the first CPU. */
 759     return env->cpu_index == 0;
 760 }
 761
 762 DeviceState *cpu_get_current_apic(void)
 763 {
 764     if (cpu_single_env) {
 765         return cpu_single_env->apic_state;
 766     } else {
 767         return NULL;
 768     }
 769 }
 770
 771 static DeviceState *apic_init(void *env, uint8_t apic_id)
 772 {
 773     DeviceState *dev;
 774     SysBusDevice *d;
 775     static int apic_mapped;
 776
 777     dev = qdev_create(NULL, "apic");
 778     qdev_prop_set_uint8(dev, "id", apic_id);
 779     qdev_prop_set_ptr(dev, "cpu_env", env);
 780     qdev_init_nofail(dev);
 781     d = sysbus_from_qdev(dev);
 782
 783     /* XXX: mapping more APICs at the same memory location */
 784     if (apic_mapped == 0) {
 785         /* NOTE: the APIC is directly connected to the CPU - it is not
 786            on the global memory bus. */
 787         /* XXX: what if the base changes? */
 788         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 789         apic_mapped = 1;
 790     }
 791
 792     msix_supported = 1;
 793
 794     return dev;
 795 }
 796
 797 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 798    BIOS will read it and start S3 resume at POST Entry */
 799 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 800 {
 801     ISADevice *s = opaque;
 802
 803     if (level) {
 804         rtc_set_memory(s, 0xF, 0xFE);
 805     }
 806 }
 807
 808 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 809 {
 810     CPUState *s = opaque;
 811
 812     if (level) {
 813         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 814     }
 815 }
 816
 817 static void pc_cpu_reset(void *opaque)
 818 {
 819     CPUState *env = opaque;
 820
 821     cpu_reset(env);
 822     env->halted = !cpu_is_bsp(env);
 823 }
 824
 825 CPUState *pc_new_cpu(const char *cpu_model)
 826 {
 827     CPUState *env;
 828
 829     if (cpu_model == NULL) {
 830 #ifdef TARGET_X86_64
 831         cpu_model = "qemu64";
 832 #else
 833         cpu_model = "qemu32";
 834 #endif
 835     }
 836
 837     env = cpu_init(cpu_model);
 838     if (!env) {
 839         fprintf(stderr, "Unable to find x86 CPU definition\n");
 840         exit(1);
 841     }
 842     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 843         env->cpuid_apic_id = env->cpu_index;
 844         env->apic_state = apic_init(env, env->cpuid_apic_id);
 845     }
 846     qemu_register_reset(pc_cpu_reset, env);
 847     pc_cpu_reset(env);
 848     return env;
 849 }
 850
 851 void pc_cpus_init(const char *cpu_model)
 852 {
 853     int i;
 854
 855     /* init CPUs */
 856     for(i = 0; i < smp_cpus; i++) {
 857         pc_new_cpu(cpu_model);
 858     }
 859 }
 860
 861 void pc_memory_init(ram_addr_t ram_size,
 862                     const char *kernel_filename,
 863                     const char *kernel_cmdline,
 864                     const char *initrd_filename,
 865                     ram_addr_t *below_4g_mem_size_p,
 866                     ram_addr_t *above_4g_mem_size_p)
 867 {
 868     char *filename;
 869     int ret, linux_boot, i;
 870     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 871     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 872     int bios_size, isa_bios_size;
 873     void *fw_cfg;
 874
 875     if (ram_size >= 0xe0000000 ) {
 876         above_4g_mem_size = ram_size - 0xe0000000;
 877         below_4g_mem_size = 0xe0000000;
 878     } else {
 879         below_4g_mem_size = ram_size;
 880     }
 881     *above_4g_mem_size_p = above_4g_mem_size;
 882     *below_4g_mem_size_p = below_4g_mem_size;
 883
 884     linux_boot = (kernel_filename != NULL);
 885
 886     /* allocate RAM */
 887     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 888     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 889     cpu_register_physical_memory(0x100000,
 890                  below_4g_mem_size - 0x100000,
 891                  ram_addr + 0x100000);
 892
 893     /* above 4giga memory allocation */
 894     if (above_4g_mem_size > 0) {
 895 #if TARGET_PHYS_ADDR_BITS == 32
 896         hw_error("To much RAM for 32-bit physical address");
 897 #else
 898         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 899         cpu_register_physical_memory(0x100000000ULL,
 900                                      above_4g_mem_size,
 901                                      ram_addr);
 902 #endif
 903     }
 904
 905
 906     /* BIOS load */
 907     if (bios_name == NULL)
 908         bios_name = BIOS_FILENAME;
 909     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 910     if (filename) {
 911         bios_size = get_image_size(filename);
 912     } else {
 913         bios_size = -1;
 914     }
 915     if (bios_size <= 0 ||
 916         (bios_size % 65536) != 0) {
 917         goto bios_error;
 918     }
 919     bios_offset = qemu_ram_alloc(bios_size);
 920     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 921     if (ret != 0) {
 922     bios_error:
 923         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 924         exit(1);
 925     }
 926     if (filename) {
 927         qemu_free(filename);
 928     }
 929     /* map the last 128KB of the BIOS in ISA space */
 930     isa_bios_size = bios_size;
 931     if (isa_bios_size > (128 * 1024))
 932         isa_bios_size = 128 * 1024;
 933     cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
 934                                  IO_MEM_UNASSIGNED);
 935     /* kvm tpr optimization needs the bios accessible for write, at least to qemu itself */
 936     cpu_register_physical_memory(0x100000 - isa_bios_size,
 937                                  isa_bios_size,
 938                                  (bios_offset + bios_size - isa_bios_size) /* | IO_MEM_ROM */);
 939
 940     if (extboot_drive) {
 941         option_rom[nb_option_roms++] = qemu_strdup(EXTBOOT_FILENAME);
 942     }
 943     option_rom[nb_option_roms++] = qemu_strdup(VAPIC_FILENAME);
 944
 945     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 946     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 947
 948     /* map all the bios at the top of memory */
 949     cpu_register_physical_memory((uint32_t)(-bios_size),
 950                                  bios_size, bios_offset | IO_MEM_ROM);
 951
 952     fw_cfg = bochs_bios_init();
 953     rom_set_fw(fw_cfg);
 954
 955     if (linux_boot) {
 956         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 957     }
 958
 959     for (i = 0; i < nb_option_roms; i++) {
 960         rom_add_option(option_rom[i]);
 961     }
 962 }
 963
 964 qemu_irq *pc_allocate_cpu_irq(void)
 965 {
 966     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 967 }
 968
 969 void pc_vga_init(PCIBus *pci_bus)
 970 {
 971     if (cirrus_vga_enabled) {
 972         if (pci_bus) {
 973             pci_cirrus_vga_init(pci_bus);
 974         } else {
 975             isa_cirrus_vga_init();
 976         }
 977     } else if (vmsvga_enabled) {
 978         if (pci_bus)
 979             pci_vmsvga_init(pci_bus);
 980         else
 981             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 982     } else if (std_vga_enabled) {
 983         if (pci_bus) {
 984             pci_vga_init(pci_bus, 0, 0);
 985         } else {
 986             isa_vga_init();
 987         }
 988     }
 989 }
 990
 991 static void cpu_request_exit(void *opaque, int irq, int level)
 992 {
 993     CPUState *env = cpu_single_env;
 994
 995     if (env && level) {
 996         cpu_exit(env);
 997     }
 998 }
 999
1000 void pc_basic_device_init(qemu_irq *isa_irq,
1001                           FDCtrl **floppy_controller,
1002                           ISADevice **rtc_state)
1003 {
1004     int i;
1005     DriveInfo *fd[MAX_FD];
1006     PITState *pit;
1007     qemu_irq rtc_irq = NULL;
1008     qemu_irq *a20_line;
1009     ISADevice *i8042;
1010     qemu_irq *cpu_exit_irq;
1011
1012     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1013
1014     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1015
1016     if (!no_hpet) {
1017         DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
1018
1019         for (i = 0; i < 24; i++) {
1020             sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1021         }
1022         rtc_irq = qdev_get_gpio_in(hpet, 0);
1023     }
1024     *rtc_state = rtc_init(2000, rtc_irq);
1025
1026     qemu_register_boot_set(pc_boot_set, *rtc_state);
1027
1028 #ifdef CONFIG_KVM_PIT
1029     if (kvm_enabled() && kvm_pit_in_kernel())
1030         pit = kvm_pit_init(0x40, isa_reserve_irq(0));
1031     else
1032 #endif
1033
1034     pit = pit_init(0x40, isa_reserve_irq(0));
1035
1036     pcspk_init(pit);
1037
1038     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1039         if (serial_hds[i]) {
1040             serial_isa_init(i, serial_hds[i]);
1041         }
1042     }
1043
1044     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1045         if (parallel_hds[i]) {
1046             parallel_init(i, parallel_hds[i]);
1047         }
1048     }
1049
1050     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
1051     i8042 = isa_create_simple("i8042");
1052     i8042_setup_a20_line(i8042, a20_line);
1053     vmmouse_init(i8042);
1054
1055     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1056     DMA_init(0, cpu_exit_irq);
1057
1058     for(i = 0; i < MAX_FD; i++) {
1059         fd[i] = drive_get(IF_FLOPPY, 0, i);
1060     }
1061     *floppy_controller = fdctrl_init_isa(fd);
1062 }
1063
1064 void pc_pci_device_init(PCIBus *pci_bus)
1065 {
1066     int max_bus;
1067     int bus;
1068
1069 #ifdef CONFIG_AMD_IOMMU
1070     amd_iommu_init(pci_bus);
1071 #endif
1072
1073     max_bus = drive_get_max_bus(IF_SCSI);
1074     for (bus = 0; bus <= max_bus; bus++) {
1075         pci_create_simple(pci_bus, -1, "lsi53c895a");
1076     }
1077
1078     if (extboot_drive) {
1079         DriveInfo *info = extboot_drive;
1080         int cyls, heads, secs;
1081
1082         if (info->type != IF_IDE && info->type != IF_VIRTIO) {
1083             bdrv_guess_geometry(info->bdrv, &cyls, &heads, &secs);
1084             bdrv_set_geometry_hint(info->bdrv, cyls, heads, secs);
1085         }
1086
1087         extboot_init(info->bdrv);
1088     }
1089
1090 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1091     if (kvm_enabled()) {
1092         add_assigned_devices(pci_bus, assigned_devices, assigned_devices_index);
1093     }
1094 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
1095 }