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imx31pdk: use rclk w/1MHz fallback
[openocd/openocdswd.git] / src / target / arm_adi_v5.c
blob34147967a7feda7fa526e670ba7b5c05a59f395e
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "arm.h"
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
75
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
104 {
105 uint32_t select_apsel = (apsel << 24) & 0xFF000000;
106
107 if (select_apsel != dap->apsel)
108 {
109 dap->apsel = select_apsel;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 */
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
116 }
117 }
118
119 /**
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
122 *
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
127 *
128 * @todo Rename to reflect it being specifically a MEM-AP function.
129 *
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
135 *
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 */
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
139 {
140 int retval;
141
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
144 {
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
148 return retval;
149 dap->ap_csw_value = csw;
150 }
151 if (tar != dap->ap_tar_value)
152 {
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
156 return retval;
157 dap->ap_tar_value = tar;
158 }
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
162 return ERROR_OK;
163 }
164
165 /**
166 * Asynchronous (queued) read of a word from memory or a system register.
167 *
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
173 *
174 * @return ERROR_OK for success. Otherwise a fault code.
175 */
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
177 uint32_t *value)
178 {
179 int retval;
180
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
183 */
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
187 return retval;
188
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
190 }
191
192 /**
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
195 *
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
200 *
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
203 */
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
205 uint32_t *value)
206 {
207 int retval;
208
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
211 return retval;
212
213 return dap_run(dap);
214 }
215
216 /**
217 * Asynchronous (queued) write of a word to memory or a system register.
218 *
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
224 *
225 * @return ERROR_OK for success. Otherwise a fault code.
226 */
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
228 uint32_t value)
229 {
230 int retval;
231
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
234 */
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
238 return retval;
239
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
241 value);
242 }
243
244 /**
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
247 *
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
252 *
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
254 */
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
256 uint32_t value)
257 {
258 int retval = mem_ap_write_u32(dap, address, value);
259
260 if (retval != ERROR_OK)
261 return retval;
262
263 return dap_run(dap);
264 }
265
266 /*****************************************************************************
267 * *
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
269 * *
270 * Write a buffer in target order (little endian) *
271 * *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
274 {
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 uint8_t* pBuffer = buffer;
278
279 count >>= 2;
280 wcount = count;
281
282 /* if we have an unaligned access - reorder data */
283 if (adr & 0x3u)
284 {
285 for (writecount = 0; writecount < count; writecount++)
286 {
287 int i;
288 uint32_t outvalue;
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
290
291 for (i = 0; i < 4; i++)
292 {
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
294 outvalue >>= 8;
295 adr++;
296 }
297 pBuffer += sizeof(uint32_t);
298 }
299 }
300
301 while (wcount > 0)
302 {
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
306 blocksize = wcount;
307
308 /* handle unaligned data at 4k boundary */
309 if (blocksize == 0)
310 blocksize = 1;
311
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
314 return retval;
315
316 for (writecount = 0; writecount < blocksize; writecount++)
317 {
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
320 if (retval != ERROR_OK)
321 break;
322 }
323
324 if ((retval = dap_run(dap)) == ERROR_OK)
325 {
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
329 }
330 else
331 {
332 errorcount++;
333 }
334
335 if (errorcount > 1)
336 {
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
338 return retval;
339 }
340 }
341
342 return retval;
343 }
344
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
346 uint8_t *buffer, int count, uint32_t address)
347 {
348 int retval = ERROR_OK;
349 int wcount, blocksize, writecount, i;
350
351 wcount = count >> 1;
352
353 while (wcount > 0)
354 {
355 int nbytes;
356
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
359
360 if (wcount < blocksize)
361 blocksize = wcount;
362
363 /* handle unaligned data at 4k boundary */
364 if (blocksize == 0)
365 blocksize = 1;
366
367 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
368 if (retval != ERROR_OK)
369 return retval;
370 writecount = blocksize;
371
372 do
373 {
374 nbytes = MIN((writecount << 1), 4);
375
376 if (nbytes < 4)
377 {
378 retval = mem_ap_write_buf_u16(dap, buffer,
379 nbytes, address);
380 if (retval != ERROR_OK)
381 {
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32 ", count 0x%x",
384 address, count);
385 return retval;
386 }
387
388 address += nbytes >> 1;
389 }
390 else
391 {
392 uint32_t outvalue;
393 memcpy(&outvalue, buffer, sizeof(uint32_t));
394
395 for (i = 0; i < nbytes; i++)
396 {
397 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
398 outvalue >>= 8;
399 address++;
400 }
401
402 memcpy(&outvalue, buffer, sizeof(uint32_t));
403 retval = dap_queue_ap_write(dap,
404 AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
406 break;
407
408 if ((retval = dap_run(dap)) != ERROR_OK)
409 {
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32 ", count 0x%x",
412 address, count);
413 return retval;
414 }
415 }
416
417 buffer += nbytes >> 1;
418 writecount -= nbytes >> 1;
419
420 } while (writecount);
421 wcount -= blocksize;
422 }
423
424 return retval;
425 }
426
427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
428 {
429 int retval = ERROR_OK;
430
431 if (count >= 4)
432 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
433
434 while (count > 0)
435 {
436 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
437 if (retval != ERROR_OK)
438 return retval;
439 uint16_t svalue;
440 memcpy(&svalue, buffer, sizeof(uint16_t));
441 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
442 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
443 if (retval != ERROR_OK)
444 break;
445
446 retval = dap_run(dap);
447 if (retval != ERROR_OK)
448 break;
449
450 count -= 2;
451 address += 2;
452 buffer += 2;
453 }
454
455 return retval;
456 }
457
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
459 uint8_t *buffer, int count, uint32_t address)
460 {
461 int retval = ERROR_OK;
462 int wcount, blocksize, writecount, i;
463
464 wcount = count;
465
466 while (wcount > 0)
467 {
468 int nbytes;
469
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
472
473 if (wcount < blocksize)
474 blocksize = wcount;
475
476 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
477 if (retval != ERROR_OK)
478 return retval;
479 writecount = blocksize;
480
481 do
482 {
483 nbytes = MIN(writecount, 4);
484
485 if (nbytes < 4)
486 {
487 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
488 if (retval != ERROR_OK)
489 {
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32 ", count 0x%x",
492 address, count);
493 return retval;
494 }
495
496 address += nbytes;
497 }
498 else
499 {
500 uint32_t outvalue;
501 memcpy(&outvalue, buffer, sizeof(uint32_t));
502
503 for (i = 0; i < nbytes; i++)
504 {
505 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
506 outvalue >>= 8;
507 address++;
508 }
509
510 memcpy(&outvalue, buffer, sizeof(uint32_t));
511 retval = dap_queue_ap_write(dap,
512 AP_REG_DRW, outvalue);
513 if (retval != ERROR_OK)
514 break;
515
516 if ((retval = dap_run(dap)) != ERROR_OK)
517 {
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32 ", count 0x%x",
520 address, count);
521 return retval;
522 }
523 }
524
525 buffer += nbytes;
526 writecount -= nbytes;
527
528 } while (writecount);
529 wcount -= blocksize;
530 }
531
532 return retval;
533 }
534
535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
536 {
537 int retval = ERROR_OK;
538
539 if (count >= 4)
540 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
541
542 while (count > 0)
543 {
544 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 if (retval != ERROR_OK)
546 return retval;
547 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
548 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
549 if (retval != ERROR_OK)
550 break;
551
552 retval = dap_run(dap);
553 if (retval != ERROR_OK)
554 break;
555
556 count--;
557 address++;
558 buffer++;
559 }
560
561 return retval;
562 }
563
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
566 */
567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
568 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
569 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
570
571 /**
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
578 */
579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
580 int count, uint32_t address)
581 {
582 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
583 uint32_t adr = address;
584 uint8_t* pBuffer = buffer;
585
586 count >>= 2;
587 wcount = count;
588
589 while (wcount > 0)
590 {
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
594 */
595 blocksize = max_tar_block_size(dap->tar_autoincr_block,
596 address);
597 if (wcount < blocksize)
598 blocksize = wcount;
599
600 /* handle unaligned data at 4k boundary */
601 if (blocksize == 0)
602 blocksize = 1;
603
604 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
605 address);
606 if (retval != ERROR_OK)
607 return retval;
608
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
614 */
615
616 /* Scan out first read */
617 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
618 DPAP_READ, 0, NULL, NULL);
619 if (retval != ERROR_OK)
620 return retval;
621 for (readcount = 0; readcount < blocksize - 1; readcount++)
622 {
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
626 */
627 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
628 DPAP_READ, 0, buffer + 4 * readcount,
629 &dap->ack);
630 if (retval != ERROR_OK)
631 return retval;
632 }
633
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
636 */
637 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
638 DPAP_READ, 0, buffer + 4 * readcount,
639 &dap->ack);
640 if (retval != ERROR_OK)
641 return retval;
642
643 retval = dap_run(dap);
644 if (retval != ERROR_OK)
645 {
646 errorcount++;
647 if (errorcount <= 1)
648 {
649 /* try again */
650 continue;
651 }
652 LOG_WARNING("Block read error address 0x%" PRIx32, address);
653 return retval;
654 }
655 wcount = wcount - blocksize;
656 address += 4 * blocksize;
657 buffer += 4 * blocksize;
658 }
659
660 /* if we have an unaligned access - reorder data */
661 if (adr & 0x3u)
662 {
663 for (readcount = 0; readcount < count; readcount++)
664 {
665 int i;
666 uint32_t data;
667 memcpy(&data, pBuffer, sizeof(uint32_t));
668
669 for (i = 0; i < 4; i++)
670 {
671 *((uint8_t*)pBuffer) =
672 (data >> 8 * (adr & 0x3));
673 pBuffer++;
674 adr++;
675 }
676 }
677 }
678
679 return retval;
680 }
681
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
683 uint8_t *buffer, int count, uint32_t address)
684 {
685 uint32_t invalue;
686 int retval = ERROR_OK;
687 int wcount, blocksize, readcount, i;
688
689 wcount = count >> 1;
690
691 while (wcount > 0)
692 {
693 int nbytes;
694
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
697 if (wcount < blocksize)
698 blocksize = wcount;
699
700 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
701 if (retval != ERROR_OK)
702 return retval;
703
704 /* handle unaligned data at 4k boundary */
705 if (blocksize == 0)
706 blocksize = 1;
707 readcount = blocksize;
708
709 do
710 {
711 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
712 if (retval != ERROR_OK)
713 return retval;
714 if ((retval = dap_run(dap)) != ERROR_OK)
715 {
716 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
717 return retval;
718 }
719
720 nbytes = MIN((readcount << 1), 4);
721
722 for (i = 0; i < nbytes; i++)
723 {
724 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
725 buffer++;
726 address++;
727 }
728
729 readcount -= (nbytes >> 1);
730 } while (readcount);
731 wcount -= blocksize;
732 }
733
734 return retval;
735 }
736
737 /**
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
744 */
745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
746 int count, uint32_t address)
747 {
748 uint32_t invalue, i;
749 int retval = ERROR_OK;
750
751 if (count >= 4)
752 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
753
754 while (count > 0)
755 {
756 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
757 if (retval != ERROR_OK)
758 return retval;
759 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
760 if (retval != ERROR_OK)
761 break;
762
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
765 break;
766
767 if (address & 0x1)
768 {
769 for (i = 0; i < 2; i++)
770 {
771 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
772 buffer++;
773 address++;
774 }
775 }
776 else
777 {
778 uint16_t svalue = (invalue >> 8 * (address & 0x3));
779 memcpy(buffer, &svalue, sizeof(uint16_t));
780 address += 2;
781 buffer += 2;
782 }
783 count -= 2;
784 }
785
786 return retval;
787 }
788
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
791 *
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
794 */
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
796 uint8_t *buffer, int count, uint32_t address)
797 {
798 uint32_t invalue;
799 int retval = ERROR_OK;
800 int wcount, blocksize, readcount, i;
801
802 wcount = count;
803
804 while (wcount > 0)
805 {
806 int nbytes;
807
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
810
811 if (wcount < blocksize)
812 blocksize = wcount;
813
814 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
815 if (retval != ERROR_OK)
816 return retval;
817 readcount = blocksize;
818
819 do
820 {
821 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
822 if (retval != ERROR_OK)
823 return retval;
824 if ((retval = dap_run(dap)) != ERROR_OK)
825 {
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
827 return retval;
828 }
829
830 nbytes = MIN(readcount, 4);
831
832 for (i = 0; i < nbytes; i++)
833 {
834 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
835 buffer++;
836 address++;
837 }
838
839 readcount -= nbytes;
840 } while (readcount);
841 wcount -= blocksize;
842 }
843
844 return retval;
845 }
846
847 /**
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
854 */
855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
856 int count, uint32_t address)
857 {
858 uint32_t invalue;
859 int retval = ERROR_OK;
860
861 if (count >= 4)
862 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
863
864 while (count > 0)
865 {
866 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
867 if (retval != ERROR_OK)
868 return retval;
869 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
870 if (retval != ERROR_OK)
871 return retval;
872 retval = dap_run(dap);
873 if (retval != ERROR_OK)
874 break;
875
876 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
877 count--;
878 address++;
879 buffer++;
880 }
881
882 return retval;
883 }
884
885 /*--------------------------------------------------------------------------*/
886
887
888 /* FIXME don't import ... just initialize as
889 * part of DAP transport setup
890 */
891 extern const struct dap_ops jtag_dp_ops;
892
893 /*--------------------------------------------------------------------------*/
894
895 /**
896 * Initialize a DAP. This sets up the power domains, prepares the DP
897 * for further use, and arranges to use AP #0 for all AP operations
898 * until dap_ap-select() changes that policy.
899 *
900 * @param dap The DAP being initialized.
901 *
902 * @todo Rename this. We also need an initialization scheme which account
903 * for SWD transports not just JTAG; that will need to address differences
904 * in layering. (JTAG is useful without any debug target; but not SWD.)
905 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
906 */
907 int ahbap_debugport_init(struct adiv5_dap *dap)
908 {
909 uint32_t idreg, romaddr, dummy;
910 uint32_t ctrlstat;
911 int cnt = 0;
912 int retval;
913
914 LOG_DEBUG(" ");
915
916 /* JTAG-DP or SWJ-DP, in JTAG mode */
917 dap->ops = &jtag_dp_ops;
918
919 /* Default MEM-AP setup.
920 *
921 * REVISIT AP #0 may be an inappropriate default for this.
922 * Should we probe, or take a hint from the caller?
923 * Presumably we can ignore the possibility of multiple APs.
924 */
925 dap->apsel = !0;
926 dap_ap_select(dap, 0);
927
928 /* DP initialization */
929
930 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
931 if (retval != ERROR_OK)
932 return retval;
933
934 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
935 if (retval != ERROR_OK)
936 return retval;
937
938 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
939 if (retval != ERROR_OK)
940 return retval;
941
942 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
943 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
944 if (retval != ERROR_OK)
945 return retval;
946
947 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
948 if (retval != ERROR_OK)
949 return retval;
950 if ((retval = dap_run(dap)) != ERROR_OK)
951 return retval;
952
953 /* Check that we have debug power domains activated */
954 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
955 {
956 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
957 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
958 if (retval != ERROR_OK)
959 return retval;
960 if ((retval = dap_run(dap)) != ERROR_OK)
961 return retval;
962 alive_sleep(10);
963 }
964
965 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
966 {
967 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
968 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
969 if (retval != ERROR_OK)
970 return retval;
971 if ((retval = dap_run(dap)) != ERROR_OK)
972 return retval;
973 alive_sleep(10);
974 }
975
976 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
977 if (retval != ERROR_OK)
978 return retval;
979 /* With debug power on we can activate OVERRUN checking */
980 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
981 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
982 if (retval != ERROR_OK)
983 return retval;
984 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
985 if (retval != ERROR_OK)
986 return retval;
987
988 /*
989 * REVISIT this isn't actually *initializing* anything in an AP,
990 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
991 * Should it? If the ROM address is valid, is this the right
992 * place to scan the table and do any topology detection?
993 */
994 retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
995 if (retval != ERROR_OK)
996 return retval;
997 retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
998 if (retval != ERROR_OK)
999 return retval;
1000
1001 if ((retval = dap_run(dap)) != ERROR_OK)
1002 return retval;
1003
1004 LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
1005 ", Debug ROM Address 0x%" PRIx32,
1006 dap->apsel, idreg, romaddr);
1007
1008 return ERROR_OK;
1009 }
1010
1011 /* CID interpretation -- see ARM IHI 0029B section 3
1012 * and ARM IHI 0031A table 13-3.
1013 */
1014 static const char *class_description[16] ={
1015 "Reserved", "ROM table", "Reserved", "Reserved",
1016 "Reserved", "Reserved", "Reserved", "Reserved",
1017 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1018 "Reserved", "OptimoDE DESS",
1019 "Generic IP component", "PrimeCell or System component"
1020 };
1021
1022 static bool
1023 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1024 {
1025 return cid3 == 0xb1 && cid2 == 0x05
1026 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1027 }
1028
1029 static int dap_info_command(struct command_context *cmd_ctx,
1030 struct adiv5_dap *dap, int apsel)
1031 {
1032 int retval;
1033 uint32_t dbgbase, apid;
1034 int romtable_present = 0;
1035 uint8_t mem_ap;
1036 uint32_t apselold;
1037
1038 /* AP address is in bits 31:24 of DP_SELECT */
1039 if (apsel >= 256)
1040 return ERROR_INVALID_ARGUMENTS;
1041
1042 apselold = dap->apsel;
1043 dap_ap_select(dap, apsel);
1044 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1045 if (retval != ERROR_OK)
1046 return retval;
1047 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1048 if (retval != ERROR_OK)
1049 return retval;
1050 retval = dap_run(dap);
1051 if (retval != ERROR_OK)
1052 return retval;
1053
1054 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1055 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1056 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1057 if (apid)
1058 {
1059 switch (apid&0x0F)
1060 {
1061 case 0:
1062 command_print(cmd_ctx, "\tType is JTAG-AP");
1063 break;
1064 case 1:
1065 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1066 break;
1067 case 2:
1068 command_print(cmd_ctx, "\tType is MEM-AP APB");
1069 break;
1070 default:
1071 command_print(cmd_ctx, "\tUnknown AP type");
1072 break;
1073 }
1074
1075 /* NOTE: a MEM-AP may have a single CoreSight component that's
1076 * not a ROM table ... or have no such components at all.
1077 */
1078 if (mem_ap)
1079 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1080 dbgbase);
1081 }
1082 else
1083 {
1084 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1085 }
1086
1087 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1088 if (romtable_present)
1089 {
1090 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1091 uint16_t entry_offset;
1092
1093 /* bit 16 of apid indicates a memory access port */
1094 if (dbgbase & 0x02)
1095 command_print(cmd_ctx, "\tValid ROM table present");
1096 else
1097 command_print(cmd_ctx, "\tROM table in legacy format");
1098
1099 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1100 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1101 if (retval != ERROR_OK)
1102 return retval;
1103 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1104 if (retval != ERROR_OK)
1105 return retval;
1106 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1107 if (retval != ERROR_OK)
1108 return retval;
1109 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1110 if (retval != ERROR_OK)
1111 return retval;
1112 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1113 if (retval != ERROR_OK)
1114 return retval;
1115 retval = dap_run(dap);
1116 if (retval != ERROR_OK)
1117 return retval;
1118
1119 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1120 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1121 ", CID2 0x%2.2x"
1122 ", CID1 0x%2.2x"
1123 ", CID0 0x%2.2x",
1124 (unsigned) cid3, (unsigned)cid2,
1125 (unsigned) cid1, (unsigned) cid0);
1126 if (memtype & 0x01)
1127 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1128 else
1129 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1130 "Dedicated debug bus.");
1131
1132 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1133 entry_offset = 0;
1134 do
1135 {
1136 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1137 if (retval != ERROR_OK)
1138 return retval;
1139 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1140 if (romentry&0x01)
1141 {
1142 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1143 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1144 uint32_t component_base;
1145 unsigned part_num;
1146 char *type, *full;
1147
1148 component_base = (dbgbase & 0xFFFFF000)
1149 + (romentry & 0xFFFFF000);
1150
1151 /* IDs are in last 4K section */
1152
1153
1154 retval = mem_ap_read_atomic_u32(dap,
1155 component_base + 0xFE0, &c_pid0);
1156 if (retval != ERROR_OK)
1157 return retval;
1158 c_pid0 &= 0xff;
1159 retval = mem_ap_read_atomic_u32(dap,
1160 component_base + 0xFE4, &c_pid1);
1161 if (retval != ERROR_OK)
1162 return retval;
1163 c_pid1 &= 0xff;
1164 retval = mem_ap_read_atomic_u32(dap,
1165 component_base + 0xFE8, &c_pid2);
1166 if (retval != ERROR_OK)
1167 return retval;
1168 c_pid2 &= 0xff;
1169 retval = mem_ap_read_atomic_u32(dap,
1170 component_base + 0xFEC, &c_pid3);
1171 if (retval != ERROR_OK)
1172 return retval;
1173 c_pid3 &= 0xff;
1174 retval = mem_ap_read_atomic_u32(dap,
1175 component_base + 0xFD0, &c_pid4);
1176 if (retval != ERROR_OK)
1177 return retval;
1178 c_pid4 &= 0xff;
1179
1180 retval = mem_ap_read_atomic_u32(dap,
1181 component_base + 0xFF0, &c_cid0);
1182 if (retval != ERROR_OK)
1183 return retval;
1184 c_cid0 &= 0xff;
1185 retval = mem_ap_read_atomic_u32(dap,
1186 component_base + 0xFF4, &c_cid1);
1187 if (retval != ERROR_OK)
1188 return retval;
1189 c_cid1 &= 0xff;
1190 retval = mem_ap_read_atomic_u32(dap,
1191 component_base + 0xFF8, &c_cid2);
1192 if (retval != ERROR_OK)
1193 return retval;
1194 c_cid2 &= 0xff;
1195 retval = mem_ap_read_atomic_u32(dap,
1196 component_base + 0xFFC, &c_cid3);
1197 if (retval != ERROR_OK)
1198 return retval;
1199 c_cid3 &= 0xff;
1200
1201
1202 command_print(cmd_ctx,
1203 "\t\tComponent base address 0x%" PRIx32
1204 ", start address 0x%" PRIx32,
1205 component_base,
1206 /* component may take multiple 4K pages */
1207 component_base - 0x1000*(c_pid4 >> 4));
1208 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1209 (int) (c_cid1 >> 4) & 0xf,
1210 /* See ARM IHI 0029B Table 3-3 */
1211 class_description[(c_cid1 >> 4) & 0xf]);
1212
1213 /* CoreSight component? */
1214 if (((c_cid1 >> 4) & 0x0f) == 9) {
1215 uint32_t devtype;
1216 unsigned minor;
1217 char *major = "Reserved", *subtype = "Reserved";
1218
1219 retval = mem_ap_read_atomic_u32(dap,
1220 (component_base & 0xfffff000) | 0xfcc,
1221 &devtype);
1222 if (retval != ERROR_OK)
1223 return retval;
1224 minor = (devtype >> 4) & 0x0f;
1225 switch (devtype & 0x0f) {
1226 case 0:
1227 major = "Miscellaneous";
1228 switch (minor) {
1229 case 0:
1230 subtype = "other";
1231 break;
1232 case 4:
1233 subtype = "Validation component";
1234 break;
1235 }
1236 break;
1237 case 1:
1238 major = "Trace Sink";
1239 switch (minor) {
1240 case 0:
1241 subtype = "other";
1242 break;
1243 case 1:
1244 subtype = "Port";
1245 break;
1246 case 2:
1247 subtype = "Buffer";
1248 break;
1249 }
1250 break;
1251 case 2:
1252 major = "Trace Link";
1253 switch (minor) {
1254 case 0:
1255 subtype = "other";
1256 break;
1257 case 1:
1258 subtype = "Funnel, router";
1259 break;
1260 case 2:
1261 subtype = "Filter";
1262 break;
1263 case 3:
1264 subtype = "FIFO, buffer";
1265 break;
1266 }
1267 break;
1268 case 3:
1269 major = "Trace Source";
1270 switch (minor) {
1271 case 0:
1272 subtype = "other";
1273 break;
1274 case 1:
1275 subtype = "Processor";
1276 break;
1277 case 2:
1278 subtype = "DSP";
1279 break;
1280 case 3:
1281 subtype = "Engine/Coprocessor";
1282 break;
1283 case 4:
1284 subtype = "Bus";
1285 break;
1286 }
1287 break;
1288 case 4:
1289 major = "Debug Control";
1290 switch (minor) {
1291 case 0:
1292 subtype = "other";
1293 break;
1294 case 1:
1295 subtype = "Trigger Matrix";
1296 break;
1297 case 2:
1298 subtype = "Debug Auth";
1299 break;
1300 }
1301 break;
1302 case 5:
1303 major = "Debug Logic";
1304 switch (minor) {
1305 case 0:
1306 subtype = "other";
1307 break;
1308 case 1:
1309 subtype = "Processor";
1310 break;
1311 case 2:
1312 subtype = "DSP";
1313 break;
1314 case 3:
1315 subtype = "Engine/Coprocessor";
1316 break;
1317 }
1318 break;
1319 }
1320 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1321 (unsigned) (devtype & 0xff),
1322 major, subtype);
1323 /* REVISIT also show 0xfc8 DevId */
1324 }
1325
1326 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1327 command_print(cmd_ctx,
1328 "\t\tCID3 0%2.2x"
1329 ", CID2 0%2.2x"
1330 ", CID1 0%2.2x"
1331 ", CID0 0%2.2x",
1332 (int) c_cid3,
1333 (int) c_cid2,
1334 (int)c_cid1,
1335 (int)c_cid0);
1336 command_print(cmd_ctx,
1337 "\t\tPeripheral ID[4..0] = hex "
1338 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1339 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1340 (int) c_pid1, (int) c_pid0);
1341
1342 /* Part number interpretations are from Cortex
1343 * core specs, the CoreSight components TRM
1344 * (ARM DDI 0314H), and ETM specs; also from
1345 * chip observation (e.g. TI SDTI).
1346 */
1347 part_num = (c_pid0 & 0xff);
1348 part_num |= (c_pid1 & 0x0f) << 8;
1349 switch (part_num) {
1350 case 0x000:
1351 type = "Cortex-M3 NVIC";
1352 full = "(Interrupt Controller)";
1353 break;
1354 case 0x001:
1355 type = "Cortex-M3 ITM";
1356 full = "(Instrumentation Trace Module)";
1357 break;
1358 case 0x002:
1359 type = "Cortex-M3 DWT";
1360 full = "(Data Watchpoint and Trace)";
1361 break;
1362 case 0x003:
1363 type = "Cortex-M3 FBP";
1364 full = "(Flash Patch and Breakpoint)";
1365 break;
1366 case 0x00d:
1367 type = "CoreSight ETM11";
1368 full = "(Embedded Trace)";
1369 break;
1370 // case 0x113: what?
1371 case 0x120: /* from OMAP3 memmap */
1372 type = "TI SDTI";
1373 full = "(System Debug Trace Interface)";
1374 break;
1375 case 0x343: /* from OMAP3 memmap */
1376 type = "TI DAPCTL";
1377 full = "";
1378 break;
1379 case 0x906:
1380 type = "Coresight CTI";
1381 full = "(Cross Trigger)";
1382 break;
1383 case 0x907:
1384 type = "Coresight ETB";
1385 full = "(Trace Buffer)";
1386 break;
1387 case 0x908:
1388 type = "Coresight CSTF";
1389 full = "(Trace Funnel)";
1390 break;
1391 case 0x910:
1392 type = "CoreSight ETM9";
1393 full = "(Embedded Trace)";
1394 break;
1395 case 0x912:
1396 type = "Coresight TPIU";
1397 full = "(Trace Port Interface Unit)";
1398 break;
1399 case 0x921:
1400 type = "Cortex-A8 ETM";
1401 full = "(Embedded Trace)";
1402 break;
1403 case 0x922:
1404 type = "Cortex-A8 CTI";
1405 full = "(Cross Trigger)";
1406 break;
1407 case 0x923:
1408 type = "Cortex-M3 TPIU";
1409 full = "(Trace Port Interface Unit)";
1410 break;
1411 case 0x924:
1412 type = "Cortex-M3 ETM";
1413 full = "(Embedded Trace)";
1414 break;
1415 case 0xc08:
1416 type = "Cortex-A8 Debug";
1417 full = "(Debug Unit)";
1418 break;
1419 default:
1420 type = "-*- unrecognized -*-";
1421 full = "";
1422 break;
1423 }
1424 command_print(cmd_ctx, "\t\tPart is %s %s",
1425 type, full);
1426 }
1427 else
1428 {
1429 if (romentry)
1430 command_print(cmd_ctx, "\t\tComponent not present");
1431 else
1432 command_print(cmd_ctx, "\t\tEnd of ROM table");
1433 }
1434 entry_offset += 4;
1435 } while (romentry > 0);
1436 }
1437 else
1438 {
1439 command_print(cmd_ctx, "\tNo ROM table present");
1440 }
1441 dap_ap_select(dap, apselold);
1442
1443 return ERROR_OK;
1444 }
1445
1446 COMMAND_HANDLER(handle_dap_info_command)
1447 {
1448 struct target *target = get_current_target(CMD_CTX);
1449 struct arm *arm = target_to_arm(target);
1450 struct adiv5_dap *dap = arm->dap;
1451 uint32_t apsel;
1452
1453 switch (CMD_ARGC) {
1454 case 0:
1455 apsel = dap->apsel;
1456 break;
1457 case 1:
1458 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1459 break;
1460 default:
1461 return ERROR_COMMAND_SYNTAX_ERROR;
1462 }
1463
1464 return dap_info_command(CMD_CTX, dap, apsel);
1465 }
1466
1467 COMMAND_HANDLER(dap_baseaddr_command)
1468 {
1469 struct target *target = get_current_target(CMD_CTX);
1470 struct arm *arm = target_to_arm(target);
1471 struct adiv5_dap *dap = arm->dap;
1472
1473 uint32_t apsel, apselsave, baseaddr;
1474 int retval;
1475
1476 apselsave = dap->apsel;
1477 switch (CMD_ARGC) {
1478 case 0:
1479 apsel = dap->apsel;
1480 break;
1481 case 1:
1482 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1483 /* AP address is in bits 31:24 of DP_SELECT */
1484 if (apsel >= 256)
1485 return ERROR_INVALID_ARGUMENTS;
1486 break;
1487 default:
1488 return ERROR_COMMAND_SYNTAX_ERROR;
1489 }
1490
1491 if (apselsave != apsel)
1492 dap_ap_select(dap, apsel);
1493
1494 /* NOTE: assumes we're talking to a MEM-AP, which
1495 * has a base address. There are other kinds of AP,
1496 * though they're not common for now. This should
1497 * use the ID register to verify it's a MEM-AP.
1498 */
1499 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1500 if (retval != ERROR_OK)
1501 return retval;
1502 retval = dap_run(dap);
1503 if (retval != ERROR_OK)
1504 return retval;
1505
1506 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1507
1508 if (apselsave != apsel)
1509 dap_ap_select(dap, apselsave);
1510
1511 return retval;
1512 }
1513
1514 COMMAND_HANDLER(dap_memaccess_command)
1515 {
1516 struct target *target = get_current_target(CMD_CTX);
1517 struct arm *arm = target_to_arm(target);
1518 struct adiv5_dap *dap = arm->dap;
1519
1520 uint32_t memaccess_tck;
1521
1522 switch (CMD_ARGC) {
1523 case 0:
1524 memaccess_tck = dap->memaccess_tck;
1525 break;
1526 case 1:
1527 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1528 break;
1529 default:
1530 return ERROR_COMMAND_SYNTAX_ERROR;
1531 }
1532 dap->memaccess_tck = memaccess_tck;
1533
1534 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1535 dap->memaccess_tck);
1536
1537 return ERROR_OK;
1538 }
1539
1540 COMMAND_HANDLER(dap_apsel_command)
1541 {
1542 struct target *target = get_current_target(CMD_CTX);
1543 struct arm *arm = target_to_arm(target);
1544 struct adiv5_dap *dap = arm->dap;
1545
1546 uint32_t apsel, apid;
1547 int retval;
1548
1549 switch (CMD_ARGC) {
1550 case 0:
1551 apsel = 0;
1552 break;
1553 case 1:
1554 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1555 /* AP address is in bits 31:24 of DP_SELECT */
1556 if (apsel >= 256)
1557 return ERROR_INVALID_ARGUMENTS;
1558 break;
1559 default:
1560 return ERROR_COMMAND_SYNTAX_ERROR;
1561 }
1562
1563 dap_ap_select(dap, apsel);
1564 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1565 if (retval != ERROR_OK)
1566 return retval;
1567 retval = dap_run(dap);
1568 if (retval != ERROR_OK)
1569 return retval;
1570
1571 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1572 apsel, apid);
1573
1574 return retval;
1575 }
1576
1577 COMMAND_HANDLER(dap_apid_command)
1578 {
1579 struct target *target = get_current_target(CMD_CTX);
1580 struct arm *arm = target_to_arm(target);
1581 struct adiv5_dap *dap = arm->dap;
1582
1583 uint32_t apsel, apselsave, apid;
1584 int retval;
1585
1586 apselsave = dap->apsel;
1587 switch (CMD_ARGC) {
1588 case 0:
1589 apsel = dap->apsel;
1590 break;
1591 case 1:
1592 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1593 /* AP address is in bits 31:24 of DP_SELECT */
1594 if (apsel >= 256)
1595 return ERROR_INVALID_ARGUMENTS;
1596 break;
1597 default:
1598 return ERROR_COMMAND_SYNTAX_ERROR;
1599 }
1600
1601 if (apselsave != apsel)
1602 dap_ap_select(dap, apsel);
1603
1604 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1605 if (retval != ERROR_OK)
1606 return retval;
1607 retval = dap_run(dap);
1608 if (retval != ERROR_OK)
1609 return retval;
1610
1611 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1612 if (apselsave != apsel)
1613 dap_ap_select(dap, apselsave);
1614
1615 return retval;
1616 }
1617
1618 static const struct command_registration dap_commands[] = {
1619 {
1620 .name = "info",
1621 .handler = handle_dap_info_command,
1622 .mode = COMMAND_EXEC,
1623 .help = "display ROM table for MEM-AP "
1624 "(default currently selected AP)",
1625 .usage = "[ap_num]",
1626 },
1627 {
1628 .name = "apsel",
1629 .handler = dap_apsel_command,
1630 .mode = COMMAND_EXEC,
1631 .help = "Set the currently selected AP (default 0) "
1632 "and display the result",
1633 .usage = "[ap_num]",
1634 },
1635 {
1636 .name = "apid",
1637 .handler = dap_apid_command,
1638 .mode = COMMAND_EXEC,
1639 .help = "return ID register from AP "
1640 "(default currently selected AP)",
1641 .usage = "[ap_num]",
1642 },
1643 {
1644 .name = "baseaddr",
1645 .handler = dap_baseaddr_command,
1646 .mode = COMMAND_EXEC,
1647 .help = "return debug base address from MEM-AP "
1648 "(default currently selected AP)",
1649 .usage = "[ap_num]",
1650 },
1651 {
1652 .name = "memaccess",
1653 .handler = dap_memaccess_command,
1654 .mode = COMMAND_EXEC,
1655 .help = "set/get number of extra tck for MEM-AP memory "
1656 "bus access [0-255]",
1657 .usage = "[cycles]",
1658 },
1659 COMMAND_REGISTRATION_DONE
1660 };
1661
1662 const struct command_registration dap_command_handlers[] = {
1663 {
1664 .name = "dap",
1665 .mode = COMMAND_EXEC,
1666 .help = "DAP command group",
1667 .chain = dap_commands,
1668 },
1669 COMMAND_REGISTRATION_DONE
1670 };
1671
1672
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